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ROHM develops the “AG16xFNxx Series,” a lineup of 80V power MOSFETs designed for 48V power supply systems, which are becoming increasingly common in automotive applications.

In the automotive sector, power demand is increasing, particularly in high-end vehicle models. 48V power supply systems are gaining attention as a highly efficient alternative to conventional 12V power supply systems. With widespread adoption expected around 2030, there is a growing need for 80V power MOSFETs capable of delivering even lower power losses than standard 100V devices.

ROHM’s new products enable downsizing in comparison to standard automotive MOSFET packages such as the TO-252 (6.6 × 10.0mm) by adopting the HPLF5060 (4.9 × 6.0mm) and DFN3333 (3.3 × 3.3mm) packages.

The HPLF5060 features Gull-Wing Leads, while the DFN3333 features Wettable Flank Technology, which contributes to improved reliability on PCBs (Printed Circuit Boards). Furthermore, by adopting Copper Clip Junction Technology to enhance heat dissipation, these devices are capable of handling high currents. All models comply with the automotive reliability standard AEC-Q101, ensuring high reliability.

The product lineup of these packages will be further expanded in the near future. In addition, development of TOLG (TO-Leaded with Gullwing, 9.9 × 11.7mm) packaged products has begun, with continued expansion of the lineup of high-power, high-reliability 80V MOSFETs.

Application Examples

Automotive 48V systems: Main inverter control circuits, electric motors, electric water pumps, etc.

The post ROHM Launches AG16xFNxx Series MOSFETs for Automotive 48V Power Supply Systems appeared first on ELE Times.

When chip design and verification teams start a new project, they recognize the need for models that capture the design at a high level of abstraction. However, they tend to focus on acquiring or creating models of the IP blocks used to implement the device’s core functionality, while overlooking network-on-chip (NoC) interconnect IP until it’s too late.

Modeling and simulation evolution

As chip designs grew from a handful of gates in the 1970s to hundreds of IP blocks connected by complex interconnect fabrics in the 2020s, modeling and simulation evolved to keep pace. Early approaches modeled everything at the gate level, providing complete visibility, but they quickly became impractical as complexity increased.

The industry’s first major step up in abstraction was the register transfer level (RTL). These models describe how data moves between registers on each clock cycle, maintaining bit-level and cycle-level accuracy. To this day, RTL simulation remains the gold standard for functional correctness and final sign-off. The trad-eoff is speed. Because the RTL models every signal transition, meaningful simulations can take hours or even days.

Figure 1 The integration of functional blocks and interconnects increased over time. Source: Arteris

To address this, engineers introduced cycle-accurate models. These preserve timing at the clock-cycle level but avoid modeling every individual signal. They capture events as they happen without describing every bit flip, thereby making them ideal for performance analysis. Designers can evaluate latency, bandwidth, and contention with high confidence while running simulations fast enough to explore architectural alternatives.

At an even higher level of abstraction is transaction-level modeling (TLM). Rather than modeling signals and clock cycles, TLM focuses on high-level transactions, such as moving data across the system. By abstracting away low-level implementation details, TLM can enable simulations that run orders of magnitude faster than RTL. This speed makes it practical to test hundreds of scenarios and quickly explore different design options.

TLM models also underpin virtual prototypes, enabling software to run on a simulated hardware platform long before silicon is available. This enables early hardware–software co-verification and faster overall development.

System complexity increases

Modern system-on-chips (SoCs) are sophisticated ecosystems in which processors, accelerators, memory subsystems, and NoC interconnect fabrics must work in concert with complex software stacks.

This interaction adds another layer of complexity because software must be verified in the context of the hardware throughout the design process. RTL simulation continues to play a critical role, particularly for final validation and corner-case debugging. However, it’s simply too slow to support meaningful software development at scale. Higher-level models, especially TLM-based virtual prototypes, enable software teams to begin work early while hardware teams continue refining the design.

If all of this sounds challenging, it becomes even more so in the era of chiplets and multi-die systems. Modern designs increasingly partition functionality across multiple dies, sometimes mixing process nodes, vendors, and packaging technologies. Data must move not only within a die, but across die boundaries. Some of this traffic is non-coherent, while other portions must maintain cache coherency, depending on the system architecture.

Figure 2 Here is how die-to-die options look like in NoC designs. Source: Arteris

The result is a heterogeneous communication fabric that is far more complex than the simple buses of the past. In such environments, performance is no longer determined solely by the compute elements themselves. Instead, it depends heavily on how efficiently data can move between them. Increasing data movement complexity—driven by heterogeneous compute, coherence requirements, and chiplet architectures—makes overall system performance difficult to predict without appropriate modelling.

Beyond the IP blocks

That same modeling discipline must extend to the NoC interconnect. In modern designs, NoCs are no longer passive conduits. They are first-order determinants of system performance. A contemporary SoC may contain multiple NoCs, some coherent, some non-coherent, and some forming bridges between chiplets. These interconnect fabrics are highly configurable, with parameters governing topology, bandwidth, arbitration policies, buffering, and quality-of-service (QoS) mechanisms.

This means NoCs must be modeled at the same levels of abstraction as the rest of the system. Transaction-level models support rapid exploration and system-level integration. Cycle-accurate models enable detailed performance analysis, and RTL models remain essential for final verification and implementation. Crucially, these models must be consistent with one another, enabling smooth progression from architectural intent to implementation reality.

Equally important is the ability to analyze the results generated by these models. These analysis capabilities enable designers to examine key performance indicators—including bandwidth utilization, latency, congestion, contention, buffering efficiency, and QoS behavior—across the NoC fabric. Rather than forcing engineers to sift through enormous amounts of low-level simulation data, the modeling environment presents targeted performance insights that help teams quickly identify bottlenecks, validate architectural assumptions, and compare alternative configurations.

This kind of system-level analysis is valuable in complex chiplet-based designs. Architects can use automatically generated SystemC TLM models to study NoC behavior earlier and help create and iterate NoC topologies faster.

From Exploration to implementation

Increasingly, commercial NoC providers are offering higher-level models alongside their RTL implementations. In many cases, however, these models are added as an afterthought, a bolt-on capability that may not fully reflect the behavior of the final implementation. What’s emerging as a best practice is a more integrated approach in which modeling is not an add-on but a foundational element of the design flow.

Arteris, for instance, offers FlexGen interconnect IP for non-coherent interconnects and Ncore for cache-coherent fabrics. These solutions are supported by a continuum of models, from transaction-level to cycle-accurate to RTL, designed to be consistent and correct by construction.

The result is a design methodology that enables teams to explore, validate, and refine their architectures early, with confidence that their insights will carry forward into implementation. In a world where performance margins are tight, schedules are unforgiving, and complexity continues to grow, the ability to move fast and get it right the first time may be the most valuable model of all.

Rocco Jonack is principal corporate application engineer at Arteris, where he works on advanced SoC architecture modeling, virtual prototyping, and performance analysis for complex semiconductor systems.

Related Content

• SoC design: What’s next for NoCs?
• How NoC architecture solves MCU design challenges
• Smarter SoC Design for Agile Teams and Tight Deadlines
• Why verification matters in network-on-chip (NoC) design
• NoC configuration tool takes makes complex SoC design easier

The post Model your IPs and your NoCs appeared first on EDN.