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Футбольний турнір до 20-річчя Держспецзв'язку України Інформація КП чт, 06/18/2026 - 13:00

India’s leading UAV manufacturing startup, BonV Aero, is set to establish a 30-acre drone manufacturing campus in Khordha, Odisha. Envisioned as a first-of-its-kind concept in India, the facility will combine the latest UAV manufacturing with a curated visitor experience, offering firsthand engagement with the UAV ecosystem.

“The first time I saw a drone take flight, it left a lasting impression on me and shaped the path I chose,” said Satyabrata Satapathy, co-founder & CEO, BonV Aero. “Through BonV’s Drone Park, I hope to spark that same sense of awe and possibility in every visitor, especially young, aspiring minds who will go on to shape and secure India’s UAV future.”

That ecosystem is envisioned to take shape across the ₹300 crore facility. The campus will reimagine conventional manufacturing by bringing together advanced assembly lines and a Centre of Excellence alongside training rooms and certification halls open to pilots and technicians. At its core, the BonV Experience Centre will be designed to inspire and engage, offering something for everyone from knowledge seekers to thrill seekers. Thoughtfully designed visitor spaces, the campus will blur the lines between industry and experience, creating a destination that feels as much like a hub of innovation as it does a manufacturing facility.

Most UAV and defence manufacturing facilities in India keep visitors out. BonV Aero Drone Park does the opposite, opening its gates in a structured and guided manner to those seeking to understand how drones are designed, built, and flown all within a single integrated site, added Satapathy.

Moreover, the deep tech firm expects the facility to create over 1,000 jobs across manufacturing, research, and pilot training over the next two years, and sees the campus as a step toward making Odisha a hub for the wider drone economy, not just a production base. The launch comes as Indian states compete for investment in drone manufacturing, backed by federal production-linked incentives and a push for domestic UAV components. Odisha’s ambitious Aerospace and Defence Manufacturing Policy and the B-MAAN scheme for the aviation sector were cited as reasons for the company’s decision to set up in the state.

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Всеукраїнський хакатон із комп'ютерного зору та робототехніки для школярів kpi чт, 06/18/2026 - 12:18

Every PCB designer has experienced it. A design progresses through schematic capture and layout only to reveal problems during verification, simulation, design review, or manufacturing preparation. A differential pair violates a critical constraint. A return path is compromised. A fabrication limitation was overlooked. A proven solution from a previous design was recreated rather than reused.

The result is familiar: additional iterations, schedule delays, increased costs, and engineering resources consumed by preventable rework.

For decades, many organizations have accepted this cycle as a normal part of PCB development. As design complexity continues to increase, however, this approach is becoming increasingly difficult to sustain. High-speed interfaces, power integrity requirements, signal integrity challenges, miniaturization, manufacturability demands, and compressed development schedules are all converging simultaneously. The traditional response—adding more reviews, more manual checks, and more engineering effort—does not scale.

In today’s design environment, productivity can no longer be measured by the amount of effort expended. It must be measured by how effectively engineering knowledge is captured, applied, reused, and enforced throughout the design process. This is where automation and abstraction are fundamentally changing how successful engineering organizations approach PCB design.

Rethinking productivity in PCB design

Historically, productivity improvements were often achieved by increasing engineering resources or extending design schedules. While those approaches may provide temporary relief, they do little to address the root causes of inefficiency. The reality is that many PCB development processes remain heavily dependent on manual intervention.

As design complexity increases, these manual approaches create significant risk. Constraints are often defined inconsistently. Verification occurs after implementation. Design knowledge resides primarily with individual engineers. Reuse is informal and dependent upon who remembers what was done on a previous project. The challenge is not a lack of engineering talent. The challenge is that manual processes struggle to keep pace with the increasing demands placed on modern electronic systems.

True productivity improvements come not from performing more work, but from eliminating unnecessary work altogether. More importantly, they come from preventing problems before they occur.

Automation: Enforcing design intent in real time

Automation represents a shift from manual execution to intelligent process control. Automation-assisted PCB design environments provide the ability to define electrical, physical, manufacturing, and reliability requirements as constraints that are continuously enforced throughout implementation.

Rather than relying on engineers to manually identify violations after routing is complete, constraint-driven design environments can evaluate compliance in real time. This enables:

• Continuous enforcement of electrical and physical design rules
• Real-time verification during placement and routing
• Guided routing aligned with signal and power integrity requirements
• Automated validation of manufacturing constraints
• Automated generation of manufacturing deliverables

The significance of this shift extends beyond simple efficiency gains. When design rules are evaluated continuously throughout implementation, engineers spend less time identifying problems and more time solving higher-value design challenges. Design intent becomes embedded within the process itself rather than residing solely in engineering documentation or individual expertise.

The result is improved design quality, reduced rework, greater predictability, and shorter development cycles. Simply put, designs become correct by construction rather than corrected after construction.

Engineering knowledge should not leave with the engineer

One of the most significant challenges facing engineering organizations today is the management of institutional knowledge. Many companies still depend heavily on the experience of senior engineers to ensure successful implementation of complex designs. While expertise remains invaluable, this approach creates an inherent scalability problem.

When critical knowledge exists primarily in the minds of individual contributors, organizations become vulnerable to personnel changes, inconsistent execution, and repeated mistakes. The departure of a key engineer should not result in the loss of years of accumulated design intelligence. Automation provides a mechanism for capturing and institutionalizing engineering knowledge.

Constraints, routing strategies, manufacturing requirements, design guidelines, and verification methodologies can be embedded directly within the design environment. Rather than relying on tribal knowledge, organizations can create repeatable engineering processes that consistently produce successful outcomes. The objective is not to replace engineering expertise. The objective is to amplify it and make it scalable across teams, programs, and future generations of designers.

Abstraction: Simplifying complexity through reuse

As systems become more sophisticated, managing every design detail at the individual net level becomes increasingly inefficient. This is where abstraction becomes a powerful productivity enabler. Abstraction allows engineers to work at higher levels of design intent by encapsulating proven solutions into reusable building blocks.

Examples include:

• Reusable hierarchical design blocks
• Standardized constraint templates
• Proven interface implementations
• Reference architectures
• Verified subsystem designs
• Reusable placement and routing methodologies

Design reuse is often misunderstood as simply copying circuitry from a previous project. Effective reuse goes much further. It involves capturing validated circuitry, proven constraints, routing topologies, placement strategies, manufacturing knowledge, and verification data so that future projects can build upon prior success rather than recreating it from scratch.

The difference is significant. Instead of repeatedly solving the same problems, engineering teams can focus their efforts on innovation and differentiation. This transforms design knowledge from a project-specific asset into an organizational asset.

From design automation to intent-driven design

Individually, automation and abstraction provide substantial benefits. Together they enable a more profound transformation: intent-driven design.

In an intent-driven workflow, engineers focus on defining system objectives, performance requirements, and design constraints. The design environment then continuously enforces those requirements throughout implementation. This reduces reliance on manual interpretation while improving consistency across teams and projects.

Intent-driven methodologies help ensure that:

• Design requirements remain aligned throughout implementation
• Constraints are applied consistently
• Reuse strategies are standardized
• Verification becomes continuous rather than sequential
• Manufacturing considerations are addressed earlier in the process

The result is a more predictable design flow that reduces ambiguity and improves overall engineering effectiveness.

Overcoming the adoption barrier

Despite the benefits, many organizations hesitate to adopt advanced automation and abstraction methodologies. The most common concern is the upfront investment required to define constraints, establish reusable design frameworks, and standardize engineering processes. From the perspective of an individual project, these activities can appear to add time. From the perspective of the organization, however, they represent investments in long-term scalability.

Every reusable design block created today can eliminate future engineering effort. Every validated constraint template can prevent future design errors. Every automated verification process can reduce future iterations. Over time, these benefits multiply.

Organizations that continue relying primarily on manual processes often find themselves trapped in a cycle where increasing complexity demands increasing effort. Organizations that invest in automation and abstraction create systems that scale with complexity, rather than being overwhelmed by it.

Connecting design intent across the product lifecycle

The value of automation and abstraction extends beyond PCB layout. Today’s products are increasingly developed within digital engineering ecosystems where requirements, simulation, design, manufacturing, and test activities must remain connected.

Traditional workflows often rely on disconnected tools and fragmented data sources. This creates opportunities for miscommunication, inconsistent implementation, and costly delays. On the other hand, a connected digital thread helps maintain continuity of design intent throughout the product lifecycle by linking:

• System requirements
• Architecture development
• PCB design and layout
• Simulation and verification
• Manufacturing preparation
• Test and validation

This continuity improves traceability, reduces information loss, and supports a model-based engineering approach where decisions are informed by connected data rather than isolated activities. As organizations continue advancing toward digital engineering and digital twin methodologies, the ability to maintain and leverage design intelligence throughout the lifecycle will become increasingly important.

Capture, reuse, and apply design intelligence

The future of PCB design will not be defined by how many hours engineers spend pushing traces or performing repetitive verification tasks. It will be defined by how effectively organizations capture, reuse, and apply engineering intelligence throughout the design process.

Automation and abstraction are not about replacing engineering expertise. They are about amplifying it. When constraints are defined once and enforced consistently, when proven design knowledge can be reused across programs, and when design intent remains connected throughout the product lifecycle, engineering teams gain something far more valuable than incremental productivity improvements: they establish predictability.

The organizations that embrace this shift will be better positioned to manage increasing design complexity, accelerate development cycles, and deliver higher-quality products with greater confidence. In an industry where complexity continues to grow faster than available engineering resources, success will increasingly belong to those who can transform engineering knowledge into scalable engineering intelligence.

Stephen V. Chavez is a principal printed circuit engineer with over three decades of experience. He is acknowledged globally as an industry Subject Matter Expert (SME) in PCB design. He is also an author, blogger, podcast host and is currently a principal technical product marketing manager with Siemens EDA.

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AXT Inc of Fremont, CA, USA — which makes gallium arsenide (GaAs), indium phosphide (InP) and germanium (Ge) substrates and raw materials at plants in China — says that its subsidiary Beijing Tongmei Xtal Technology Co Ltd has entered into a long-term supply agreement to reserve production capacity and raw-material allocation for, and grant supply priority to, Nanjing Casela Technologies Corporation Ltd...

Про підсумки конкурсу "Екоінноватор" Інформація КП чт, 06/18/2026 - 11:04

Elethron Ltd of London, UK and ATMOS Space Cargo GmbH of Lichtenau, Baden-Württemberg, Germany have concluded a joint engineering campaign to map and bridge the critical interfaces and operational architecture required to integrate Elethron’s microgravity materials processing lab into ATMOS’ PHOENIX free-flying reusable orbital transfer and return vehicle (OTRV), an uncrewed transportation system for controlled cargo transport, operations and return from low Earth orbit (LEO)...

Keysight Technologies, Inc. joins the Siemens Digital Industries Software Technology Partner Program. The collaboration gives customers access to Keysight Eggplant Test, an AI-driven test automation solution, to validate their digital engineering and product lifecycle management (PLM) environments.

Manufacturers face growing pressure to shorten development cycles while managing increasingly complex software-driven products. As engineering teams rely on digital tools like PLM platforms, testing those workflows, integrations, and system performance has become a significant operational challenge, with manual processes too slow and inconsistent to address at scale.

Siemens Digital Industries Software develops solutions for engineering, manufacturing, and product lifecycle management. Through the partnership, customers using the Teamcenter software can deploy Keysight Eggplant Test, an AI-driven test design and generation solution, to validate their enterprise applications and engineering workflows before they reach production.

Gareth Smith, Software Quality Engineering General Manager at Keysight, said: “As PLM environments grow in complexity, organizations need a reliable, AI-driven way to validate software before it reaches production. By joining the Siemens Digital Industries Software Solution Partner Program, engineers can use Keysight Eggplant Test to reduce the risk of undetected issues when upgrades or integrations are released, maintaining system performance and reliability at every stage of the product lifecycle.”

Resources

• White Paper: The Business Case for PLM Test Automation
• Survey: Complexity Overload and Bottleneck Struggles: The Hidden Costs of Manual PLM Testing
• Data Sheet: Testing the Product Lifecycle Management (PLM) Process with Keysight Eggplant Test

The post Keysight and Siemens Collaborate on AI-Driven Test Automation appeared first on ELE Times.

Aehr Test Systems of Fremont, CA, USA — which provides solutions for testing, burning-in and stabilizing semiconductor devices in wafer-level, singulated die, and packaged-part form — has received a follow-on production order for a fully automated FOX-XP wafer-level burn-in (WLBI) system, for delivery within the next six months. The system is configured to test nine wafers in parallel, and includes a fully integrated WaferPak Auto Aligner, and a full set of FOX WaferPak Contactors...

I have some nimo tubes, so i'm just showcasing them here. submitted by /u/EmptyWater7775 [link] [comments]

About a month ago I posted my credit-card sized computer project here and was honestly overwhelmed by the response - and thanks for all the encouraging feedback, that really helped a lot! One thing that came up repeatedly was people asking how it was actually built, so here I have some more details on the actual process. It's actually a bit of a hassle to take photos while working with dangerous chemicals, but it was worth it for sure! Honestly, my first thought after seeng this first picture was like "dang, this is nowhere as clean as I thought..." to the naked eye, everything looks precise and flawless, until you take photos with macro lens mounted on a mirrorless camera. But honestly, this kind of is satisfying too: Not only you can see all the impurities, but also every single overflow of solder paste, which doesn't even look like paste anymore as you can see the microscopic solder balls swimming in flux. Some areas needed some manual rework with additional solder paste, and the bridge over there was a result of my single layer limitation for now. And yes, I see it's almost shorting with another net but it luckily turned out fine. And regarding the actual etching process, that was described in my GitHub repo, but it was basically the normal method of etching PCBs with the difference of using copper foil with kapton tape as substrate. Curing the photoresist layer, developing it with a 5% sodium carbonate solution, etching it with ferric chloride, and lastly stripping the remaining photoresist with a 2% sodium hydroxide solution. Optionally solder mask if needed, but I skipped that step with this one. It's somewhat workable to get fast iterations but has the drawbacks of being extremely fragile. On some photos you can see how uneven the PCB is even though I taped it stretched onto a flat, rigid surface. Note that the pictures of each step is made on different runs, so you might spot some differences as result of trying different techniques. I already ordered a proper PCB from a fab, once that arrives, the Muxcard will be actually durable enough to be used as a daily driver. And for those who asked: Yes, I do plan to launch this soon. And if you're interested, you can find more details on the GitHub page :) But this post is more about these cool pictures I wanted to share here first, I'll add them into the repo as well as reddit doesn't seem to support including pictures in the text body. If there's anything you're curious about, feel free to ask - I'll try my best to answer every comment! :) submitted by /u/krauseler [link] [comments]

Allegro DVT’s Pulsar D400 series of multi-format video decoder IP now supports real-time AV2 decoding for advanced SoCs and ASICs. AV2, developed by the Alliance for Open Media, is an open, royalty-free video compression specification designed for next-generation streaming applications. As the successor to AV1, it improves compression efficiency, delivering high-quality video at significantly lower bitrates.

With AV2 capability, the Pulsar D400 series enables streaming applications up to 8K resolution with ultra-low-latency decoding (down to the sub-frame). Its multi-codec architecture supports H.264, HEVC, VVC, VP9, and AV1, while reducing silicon footprint, DDR memory bandwidth requirements, and power consumption.

 Allegro DVT also provides AV2 development and validation tools, including the Sirius AV2 Test Suites and Astralis AV2 Bitstream Analyzer, along with silicon-proven IP and compliance expertise.

Pulsar D400 product page 

Allegro DVT 

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EPC’s EPC99132 evaluation board is a GaN-based three-phase inverter for small BLDC motor drives in drones and robotic wrists. The design is built around the EPC33110, a 100-V, 20-A three-phase ePower Stage module that integrates three half bridges (six eGaN FETs), gate drivers, level shifters, and bootstrap circuitry in a 6×6.5-mm QFN package.

The EPC33110 co-packaged module requires a 5-V supply and supports 3.3-V or 5-V logic inputs. Its integrated eGaN FETs feature typical on-resistance values of 11.7 mΩ (high-side) and 13 mΩ (low-side). Performance testing demonstrated continuous current delivery of 11 ARMS per phase in a 48-V robotic joint at switching frequencies up to 100 kHz.

The EPC91132 evaluation board operates from a 10-V to 60-V DC input and integrates an MCU, regulated power supplies, DC bus voltage sensing, and current sensing. It also includes an onboard magnetic encoder for rotor position and speed control. The inverter is 23 mm in diameter, making it suitable for small drone motors.

The EPC91132 is priced at $406.25. Design support materials, including schematics, bill of materials, and Gerber files, are available for download on the product page.

EPC99132 product page

Efficient Power Conversion 

The post GaN inverter board drives compact BLDC motors appeared first on EDN.

GigaDevice offers the GD32E512 and GD32E252 MCUs purpose-built for high-speed and low-speed optical modules, respectively. The devices target applications in AI data centers, cloud infrastructure, telecommunications networks, and access networks.

The GD32E512 features an Arm Cortex-M33 core operating at 120 MHz and integrates I3C support for high-bandwidth, low-latency, high-density communications in next-generation optical modules. Its peripheral set includes two 12-bit ADCs, up to eight 12-bit DACs, two comparators, two op amps, three I²C interfaces, and one MDIO interface, enabling monitoring, control, and management functions in a compact 3×3-mm chip-scale package.

Powered by an Arm Cortex-M23 core operating at 72 MHz, the GD32E252 delivers a balance of performance, integration, and efficiency for cost-sensitive and lower-speed optical connectivity applications. The MCU integrates one 12-bit ADC, four 12-bit DACs, one comparator, one I²S interface, and three I²C interfaces in a choice of QFN package options. 

GD32E512 product page 

GD32E252 product page

GigaDevice

The post MCUs optimize control in optical modules appeared first on EDN.

A smart load switch from Diodes features low on-resistance for reliable power sequencing and rail control in automotive applications. Designated the DML1012ALDSQ, it integrates an N-channel MOSFET with 8-mΩ RDS(ON), minimizing conduction losses and reducing heat generation. The single-channel device is well suited for ADAS, infotainment platforms, and display clusters.

The switch supports a 0.8-V to 1.5×VBIAS input range and operates from a 3.2-V to 5.5-V bias supply, allowing flexibility across subsystem power rail domains. A junction-to-case thermal resistance of 8°C/W enables up to 6 A of continuous output current under appropriate thermal conditions, while low 28-µA quiescent current from VBIAS improves efficiency during power gating and reduces standby power consumption. Together, these features deliver precise system-level power sequencing.

For automotive power management applications, the DML1012ALDSQ integrates controlled output voltage slew rate, quick output discharge, and undervoltage lockout (UVLO) protection features. Controlled slew rate minimizes inrush current during startup, while quick output discharge fully discharges downstream components during shutdown. UVLO disables operation when the supply voltage falls below a safe threshold, helping ensure predictable system behavior.

Prices for the DML1012ALDSQ start at $0.17 each in 1000-piece quantities.

DML1012ALDSQ product page

Diodes Inc.

The post Smart switch simplifies automotive power sequencing appeared first on EDN.

TI’s BQ79826Z-Q1 automotive battery monitor supports up to 26 cells in series and is stackable to 128 devices. Its integrated electrochemical impedance spectroscopy (EIS) engine detects early signs of thermal runaway inside battery cells, helping improve safety and performance in EVs and energy storage systems.

The BQ79826Z-Q1 combines real-time diagnostics with predictive battery monitoring to help extend battery life. According to TI, the 26-channel chip delivers the highest cell-count monitoring in its class, tracking up to 44% more channels than previous generations. The higher channel count can reduce the number of monitoring devices and associated components required in a battery pack.

With voltage accuracy of less than 2 mV across the full -40°C to +125°C temperature range and a dedicated ADC for each channel, the BQ79826Z-Q1 enables more accurate state-of-charge and state-of-health estimation. These measurements can improve EV range prediction while supporting battery performance and longevity. EIS measurements are up to five times faster than those of previous devices, enabling more frequent battery diagnostics and earlier detection of cell degradation.

Preproduction quantities of the BQ79826Z-Q1 are available on TI.com, with production expected by the end of 2026.

BQ79826Z-Q1 product page

Texas Instruments 

The post Battery monitor combines EIS with high cell count appeared first on EDN.

КПІ першим серед університетів України приєднався до BankID НБУ на некомерційних умовах kpi ср, 06/17/2026 - 18:56

Інновації КПІ ім. Ігоря Сікорського на INSCIENCE Conference KPI4U-2 ср, 06/17/2026 - 17:58

Відбулася конференція "Бізнес, інновації, менеджмент: проблеми та перспективи" Інформація КП ср, 06/17/2026 - 17:55

19 наукових видань КПІ ім. Ігоря Сікорського включено до Переліку фахових видань України категорії «Б» kpi ср, 06/17/2026 - 15:36