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[group 4b][variant 4b] 0x0_ = MISC Opcode Name Description 0x00 NOP No operation 0x01 HLT Halt CPU execution 0x02 INT Trigger software interrupt 0x03 CLC Clear carry flag 0x04 SEC Set carry flag 0x05 CLI Clear interrupt enable flag (disable interrupts) 0x06 STI Set interrupt enable flag (enable interrupts) 0x1_ = MOV Opcode Operands Description 0x10 reg, reg Copy value from register to register 0x11 reg, [mem] Load value from memory address into register 0x12 [mem], reg Store register value to memory address 0x13 reg, #imm Load immediate value into register 0x14 [mem], [mem] Copy value from memory address to memory address 0x15 [mem], #imm Store immediate value to memory address 0x16 reg, [reg] Load value from address held in register (pointer read) 0x17 [reg], reg Store register value to address held in register (pointer write) 0x2_ = ALU Opcode Name Description 0x20 ADD Add register to accumulator 0x21 ADC Add register to accumulator with carry 0x22 SUB Subtract register from accumulator 0x23 SBB Subtract register from accumulator with borrow 0x24 AND Bitwise AND with accumulator 0x25 OR Bitwise OR with accumulator 0x26 XOR Bitwise XOR with accumulator 0x27 NOT Bitwise NOT of accumulator 0x28 CMP Compare (subtract without storing result, sets flags only) 0x29 INC Increment register by 1 0x2A DEC Decrement register by 1 0x2B SHL Shift left, MSB goes to carry, LSB set to 0 0x2C SHR Shift right, LSB goes to carry, MSB set to 0 0x2D ROL Rotate left through carry, MSB goes to carry, carry goes to LSB 0x2E ROR Rotate right through carry, LSB goes to carry, carry goes to MSB 0x3_ = JUMP Opcode Name Description 0x30 JMP Unconditional jump to address 0x31 JZ Jump if zero flag set 0x32 JNZ Jump if zero flag clear 0x33 JC Jump if carry flag set 0x34 JNC Jump if carry flag clear 0x35 JS Jump if sign flag set (result negative) 0x36 JO Jump if overflow flag set 0x4_ = STACK/CALL Opcode Name Description 0x40 PUSH Push register onto stack, decrement SP 0x41 POP Pop value from stack into register, increment SP 0x42 CALL Push PC onto stack, jump to address 0x43 RET Pop PC from stack, return to caller 0x44 IRET Pop PC and flags from stack, return from interrupt handler Github repo with all docs and files: https://github.com/mrFavoslav/8bit-cpu-MESAx8 The 8-bit ALU might not work perfectly at the moment. I recently moved some parts of the design around, so there's a good chance a few wires got messed up or misaligned in the process. Any feedback or bug catching is highly appreciated! I'll be posting my progress here and on https://www.favoslav.cz/blog/ submitted by /u/_Favo_ [link] [comments]

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📰 Газета "Київський політехнік" № 21-22 за 2026 (.pdf) Інформація КП пт, 06/05/2026 - 17:59

A new technology addresses a key performance barrier limiting the use of GaN-on-silicon semiconductors in mainstream RF applications. According to Scott Bibaud, president and CEO of Atomera, this will change the economics of GaN in RF by unlocking breakthrough RF performance on low-cost silicon substrates.

Gallium nitride (GaN) devices for high-performance RF applications are typically built on silicon carbide (SiC) substrates; while they offer robust performance, they are also costly and difficult to scale. On the other hand, silicon substrates offer a lower-cost, more scalable foundation with the potential to support larger wafer sizes and greater compatibility with standard silicon manufacturing.

However, GaN-on-silicon underperforms in RF applications due to parasitic channel losses that reduce efficiency, especially at high frequencies. Enter Atomera’s Mears Silicon Technology (MST), which claims to reduce these losses while offering robust linearity and lower-cost GaN solutions for 5G and other high-frequency RF devices.

MST—a quantum-engineered thin-film technology—introduces a thin, oxygen-modified layer near the surface of the silicon wafer to create a more favorable platform for GaN growth, making silicon a more viable foundation for high-performance RF devices. This controlled layer modifies the silicon lattice structure and helps block the diffusion of electrical dopants. That, in turn, improves crystal quality at the GaN-silicon interface.

MST can improve various wafer-level reliability measures in nitrided oxide planar devices. Source: Atomera

Incize, which provides characterization and modeling services for RF semiconductors, has performed RF characterization of the first MST-enabled samples. The Belgian company reports a substantial reduction in parasitic interface charge and a significant reduction in RF losses.

“Beyond the small-signal improvements, the large-signal results are particularly compelling,” said Mostafa Emam, founder and CEO of Incize. “Then there is a linearity benefit that extends into the high-power regime, approaching performance levels typically associated with advanced RF SOI technologies.”

In Atomera’s own testing, MST enabled more than a 10x reduction in parasitic channel charge, reducing a key mechanism of RF power loss and supporting improved high-frequency GaN device performance. The test data also shows that MST enables devices to handle significant power while maintaining signal quality—linearity—under stress.

Robert Mears, founder and CTO of Atomera, is quick to add that linearity is a top concern for RF designers. “The new data shows MST GaN-on-silicon achieving both the ultra-low RF losses and linearity metrics of advanced trap-rich RF SOI,” he said. “At the benchmark input power of 30 mW, the linearity is exceptional, 1000x better than the GaN-on-silicon reference wafer.”

Atomera, a semiconductor materials and technology licensing company, is based in Los Gatos, California.

Related Content

• GaN on silicon or SiC?
• A Guide to GaN-on-Silicon
• A brief history of gallium nitride (GaN) semiconductors
• Why RF Technologies Should Consider GaN Over Silicon
• GaN-on-Si Technology Makes Headway in RF Applications

The post The RF-ready GaN-on-silicon with lower parasitic losses appeared first on EDN.

The South Wales-based compound semiconductor cluster CSconnected has published its Strength in Places Fund (SIPF) impact report 2026, marking the conclusion of a transformative program that has established South Wales as a globally recognized hub for compound semiconductor innovation...

Next-generation AI and data-center power electronics are placing new demands on switching performance, efficiency and reliability. Meeting those demands requires high-fidelity switching data that reflects real device and module behaviour under realistic operating conditions...

Tiny defects inside a quantum material may hold the key to battery-free electronics powered by energy already floating around us. Credit: AI/ScienceDaily.com Scientists have uncovered a new way to control an unusual quantum phenomenon that could one day help power electronic devices without batteries.

An international research team led by Professor Dongchen Qi from the Queensland University of Technology (QUT) School of Chemistry and Physics and Professor Xiao Renshaw Wang from Nanyang Technological University in Singapore investigated the physics behind the nonlinear Hall effect (NLHE), a quantum phenomenon with significant potential for future energy-harvesting technologies.

Unlike the classical Hall effect, the NLHE can convert alternating electrical signals directly into direct current. This means energy from wireless transmissions or other ambient sources could potentially be transformed into usable electricity without relying on conventional diodes or other bulky electronic components. The NLHE is a sophisticated quantum phenomenon in condensed matter physics where a voltage is generated perpendicular to an applied alternating current, even in the absence of a magnetic field, Professor Qi said.

“This effect allows us to convert alternating signals straight into direct current, which is what’s needed to power electronic devices. In principle, it means sensors or chips that could operate without batteries, drawing energy from their environment.”

Quantum Material Shows Stable Performance at Room Temperature

To better understand how the effect works, the researchers examined a high-quality topological material known for its unusual electronic behavior. Their experiments showed that the nonlinear Hall effect remains stable even at room temperature, an important step toward practical applications outside the laboratory. The team also discovered that temperature plays a key role in determining both the strength and direction of the electrical voltage produced by the material.

How Defects and Atomic Vibrations Control the Effect

At lower temperatures, tiny imperfections within the material had the greatest influence on the quantum effect. As temperatures increased, naturally occurring vibrations in the crystal structure became more important. This shift caused the direction of the generated electrical signal to reverse, revealing a previously unseen mechanism for controlling the phenomenon.

“Once you understand what’s happening inside the material, you can design devices to take advantage of it,” Professor Qi said.

That’s when quantum effects stop being abstract and start becoming useful — supporting future applications ranging from self-powered sensors and wearable technology to ultra-fast components for next-generation wireless networks. The findings provide new insight into how quantum materials behave and could help researchers develop smaller, faster, and more energy-efficient technologies that harvest power from their surroundings.

 

The post Scientists discover a Quantum Effect that Eliminate Batteries appeared first on ELE Times.

Editor’s note: This is a multi-part series on how to design a digital-controlled PFC. Previous entries: 

• How to design a digital-controlled PFC, Part 1
• How to design a digital-controlled PFC, Part 2
• How to design a digital-controlled PFC, Part 3

High efficiency is a mandatory requirement in some applications, especially in data centers. The recently announced 80 Plus Ruby certification sets the highest efficiency standard for data center power-supply units (PSUs), as shown in Table 1. The new efficiency requirement is not only higher than 80 Plus Titanium at each load condition, but also requires 90% efficiency at a 5% load, which has never been specified before.

 

 

 

80 Plus test type	230V internal redundant
Percentage of rated load	5%	10%	20%	50%	100%
80 Plus Titanium		90%	94%	96%	91%
80 Plus Ruby	90%	91%	95%	96.5%	92%

Table 1 “Ruby” is the most recent and most stringent of the 80 Plus certification levels

With totem-pole bridgeless power factor correction (PFC) offering the best efficiency among all PFC topologies, digital control can further push the efficiency capabilities of this topology to new levels. In the fourth and final installment of this series, I will first introduce several digital methods to improve efficiency and then discuss some special PFC requirements including re-rush current control, electrical metering (e-metering) and PFC with a baby boost converter.

Dynamic dead time to achieve ZVS for synchronous switch

Theoretically, the PFC synchronous switch can operate with zero voltage switching (ZVS), but there must be a proper dead time between when the boost switch turns off and the synchronous switch turns on. As illustrated in Figure 1, assuming a positive cycle, when boost switch Q2 turns off, the inductor current (IL) starts to charge the output capacitance (COSS) of Q2 and discharge the output capacitance COSS of Q1, and the switch-node voltage rises.

If Q1 turns on before the switch-node voltage rises to the output voltage (VOUT), this is hard switching, and the switching losses are high. If Q1 turns on too late after the switch-node voltage rises to VOUT, the current will conduct in the third quadrant of Q1 with diode-like behavior. Since the gallium nitride field-effect transistor used for Q1 has a higher VSD drop compared to a silicon metal-oxide semiconductor field-effect transistor body diode, this induces a higher third-quadrant conduction loss.

Figure 1 This equivalent circuit describes a PFC synchronous switch during dead time. (Source: Texas Instruments)

Ideally, Q1 should turn on at the exact moment when the switch-node voltage rises to VOUT. Given the IL, VOUT and COSS of Q1 and Q2, the following equation calculates the time to charge the switch node from 0 to VOUT:

You can use firmware to dynamically adjust the dead time calculated from the equation to maintain ZVS for the synchronous switch.

CCM_TCM multimode control

A totem-pole bridgeless PFC can operate in either continuous conduction mode (CCM) or triangular current mode (TCM); each has its advantages and disadvantages. Table 2 provides a high-level comparison between the two modes.

	CCM operation	TCM operation
Pros	Low peak-to-peak IL ripple. Simple control.	ZVS.
Cons	Hard switching – high switching losses.	High peak-to-peak IL ripple. Requires multiphase interleaved operation to reduce current ripple for high-power applications, resulting in low power density and high costs. Complex control.

Table 2 Continuous conduction mode (CCM) and triangular current mode (TCM) options both have pros and cons for totem-pole power factor correction (PFC) operation purposes.

Ideally, the totem-pole bridgeless PFC could operate with multimode, as shown in Figure 2. At heavy loads or at the peak of an AC half cycle, the desired PFC input current is high and the PFC operates in CCM mode. When the load reduces or around the AC zero-crossing area where the desired PFC input current is low, the PFC switches to TCM mode and operates with ZVS.

Compared to pure CCM mode, this multimode operation has better efficiency at light loads because of ZVS. Compared to pure TCM mode, because the inductor current ripple is much lower, there is no need to use multiphase interleaved operation; therefore, this multimode operation significantly reduces the size and system costs. By combining the advantages of both CCM and TCM, this multimode operation can meet both high-efficiency and high-power-density requirements.

Figure 2 CCM_TCM multimode operation can meet both high-efficiency and high-power-density requirements. (Source: Texas Instruments)

Reference 1 provides details about this control method and its implementation. Figure 3 compares the efficiency (tested on the same board) between this CCM_TCM multimode control method and traditional CCM control, with efficiency improving as much as 2%.

(a)	(b)

Figure 3 CCM_TCM multimode control delivers efficiency improvements versus traditional CCM control in both low line (a) and high line (b) environments. (Source: Texas Instruments)

Special burst mode – AC cycle skipping

Burst mode is widely used to improve efficiency at light loads. Unlike traditional pulse-width modulation (PWM) pulse-skipping burst mode, where you skip PWM pulses randomly, here I would like to introduce a special burst mode: AC cycle skipping, which is you skip one or more AC cycles in light loads.

In other words, you would turn the PFC off for one or more AC cycles and turn the PFC back on for the next AC cycle. The turnon and turnoff instance occurs at the AC zero crossing such that the whole AC cycle is skipped. Since PFC turnon and turnoff at inductor current equal zero, there is less stress and electromagnetic interference.

The number of AC cycles to skip is reverse-proportional to the load; the lighter the load, the more AC cycles skipped. Figure 4 shows the skipping of one and two AC cycles, respectively. Channel 1 is the AC voltage, and channel 4 is the AC current.

(a)	(b)

Figure 4 Shown here is AC cycle skipping at a light loads: one cycle (a) and two cycles (b). (Source: Texas Instruments)

Once the PFC turns off, the switching losses, driving losses and reverse-recovery losses all drop to zero, and the power losses are just the PFC standby power.

When turning off the PFC to skip AC cycles, both the current loop and voltage loop need to be frozen; otherwise, the integrators in those loops will build up to generate a big PWM pulse when the PFC turns back on, causing a large current spike.

Determining whether the PFC enters a light load requires the load information. Normally there is no current sensor at the PFC output; therefore, it’s not possible to directly measure the output load. However, because the PFC voltage-loop output is proportional to the load, you can use the voltage-loop output as a rough indicator to determine whether the PFC is operating with a light load.

If you must precisely skip an appropriate number of AC cycles to maintain VOUT ripple within a specified range, you will need accurate load information, which you can obtain through an integrated e-meter function that I will discuss after the next section.

A big concern with AC cycle skipping is the VOUT drop during a load transient. Assuming that a load step-up occurs when the PFC is off, VOUT may drop too much.

To address this issue, you can compare VOUT to a predefined threshold through a comparator. Once VOUT is below this threshold, the PFC will immediately exit burst mode, disable AC cycle skipping, and return to normal operation. The PFC will handle the transient response as if there is no such special burst mode.

AC cycle skipping can also help reduce total harmonic distortion (THD) at light loads. Reference 2 compares THD with and without this method.

Re-rush current limit

The AC input voltage could suddenly drop out when PFC is operating normally. Since the load is still applied, the PFC VOUT could drop to a lower value. Then, when the AC voltage returns, if the AC input voltage is higher than VOUT, there will be an inrush current. This current is called the re-rush current.

Previously, the re-rush current was unspecified and there was no special control action for this event, it solely relied on the power-stage components’ ability to handle re-rush current. Test results show that re-rush current can jump more than 10 times higher than the PFC-rated maximum input current. Such a high re-rush current can either damage the power supply or reduce its lifetime.

The recently released Modular Hardware System– Common Redundant Power Supply (M-CRPS) specification requires limiting re-rush current when the input voltage resumes after an input brownout or blackout event on the power supply used in a data center. As shown in Figure 5, the root-mean-square (RMS) value of re-rush current should not exceed 5 times the maximum PSU rating over one-half cycle of input frequency, or 3.5 times the maximum PSU rating over one cycle of input frequency. In addition, the input current of the PSU should settle to a value less than or equal to two times the maximum PSU rating of the PSU within two cycles of the input frequency after applying the AC input.

Figure 5 The Modular Hardware System– Common Redundant Power Supply (M-CRPS) specification documents limits on both re-rush current and timing. (Source: Texas Instruments)

Reference 3 provides a firmware-based solution to handle this re-rush current so that when the AC voltage comes back from dropout, both the re-rush current (when VIN > VOUT) and the non-re-rush current (when VIN < VOUT) are well controlled – not exceeding the M-CRPS limit specification, but high enough to rapidly boost VOUT.

E-metering

Power supplies in data centers are required to measure the input power in real time and report the measurement to the host; this is called e-metering. The M-CRPS specification requires an input power measurement error within ±1% when the load is >125W, within ±1.25W when the load is between 50W and 125W, and within ±5W when the load is <50W. To achieve such high measurement accuracy, the e-meter function is traditionally implemented through a dedicated metering device, as shown in Figure 6a.

(a)	(b)

Figure 6 These circuit diagrams show a traditional e-meter and PFC control (a), as well as combining an e-meter with PFC control (b). (Source: Texas Instruments)

A current shunt placed on the PFC input side senses the input current, with a voltage divider (not shown in Figure 6a) across the AC line and AC neutral senses the input voltage. A dedicated metering device receives this current and voltage information and calculates the input power and input RMS current information, sending the results to the host.

With a digital controller, since analog-to-digital converters (ADCs) of the microcontroller (MCU) are measuring both the input voltage and input current, it becomes possible to integrate the e-meter function into PFC control code. Figure 6b shows this e-meter configuration.

A current shunt senses the input current and an isolated delta-sigma modulator (the AMC1306 from Texas Instruments) measures the voltage drop across the current shunt. The delta-sigma modulator output is sent to the PFC controller MCU. The current information will be used for both e-metering and PFC current-loop control. A voltage divider senses the input voltage, which is then measured by the MCU’s ADC directly, just as in traditional PFC control. Reference 4 has more details about e-meter implementation and calculation.

Integrating e-meter functionality into PFC control code eliminates the need for a dedicated metering device, not only reducing system costs, but also simplifying printed circuit board layout and expediting the design process.

PFC with a baby boost converter

In server applications, a bulk capacitor (CBULK in Figure 7) is required to hold PSU output in regulation for more than 10mS after AC dropout. To accomplish this, a 3kW server PSU would need a total capacitance of over 1.3mF, which would consume at least 30% of the overall space. To improve power density, you must reduce the bulk capacitance.

Adding a baby boost converter between PFC and DC/DC, as shown in Figure 7 and described in Reference 5, can achieve high power density. The baby boost converter is a compact boost converter that only operates during AC dropout events.

Figure 7 A PFC with a baby boost converter can achieve high power density. (Source: Texas Instruments)

Figure 8 is a flow chart of baby boost converter operation. During normal operation, the baby boost converter is off and bypassed by a BYPASS FET Q4. When AC line dropout occurs and VBULK drops to a certain level, Q4 turns off, and the baby boost converter turns on to allow VBB to maintain its nominal value. If AC power returns, VBULK will rise; once VBULK rises to a certain level, MCU turns off the baby boost converter, turns on BYPASS FET Q4, and the PFC resumes normal operation.

Figure 8 This flow chart outlines the various stages of baby boost converter operation.

Conclusion

I hope that the information imparted in this series enables you to design your own digital-controlled PFC and meet ever-more-strict specifications. You will find that digital control is so flexible that is possible to implement advanced control algorithms that would be difficult to implement with analog control. A digital-controlled power supply also offers impressive performance.

References

1. Sun, Bosheng. “A novel CCM-TCM multimode control method for totem-pole bridgeless PFC.” Texas Instruments Analog Design Journal article, literature No. SLYT877, 1Q 2026.
2. Sun, Bosheng. “AC cycle skipping improves PFC light-load efficiency.” Texas Instruments Analog Design Journal article, literature No. SLYT585, 3Q 2014.
3. Sun, Bosheng. “How to limit PFC re-rush current.” Texas Instruments Analog Design Journal article, literature No. SLYT865, 1Q 2025.
4. Sun, Bosheng. “A low-cost and high-accuracy e-meter solution.” EDN, Aug. 26, 2024.
5. Yu, Sheng-Yang, Benjamin Genereaux, and LiehChung Yin. “Improve power density with a baby boost converter in a PFC circuit.” Texas Instruments Analog Design Journal article, literature No. SLYT830, 2Q 2022.

Related Content

• How to design a digital-controlled PFC, Part 1
• How to design a digital-controlled PFC, Part 2
• How to design a digital-controlled PFC, Part 3
• A low-cost and high-accuracy e-meter solution

The post How to design a digital-controlled PFC, Part 4 appeared first on EDN.

India’s electronics manufacturing and design ecosystem marks a major infrastructure milestone with the inauguration of VVDN Technologies’ state-of-the-art Surface Mount Technology (SMT) line and Mechanical Innovation Park in Manesar. The launch highlights a broader structural shift in the nation’s industrial capacity, driven by targeted policy frameworks like the Make in India initiative.

According to data shared by Electronics and IT Minister Ashwini Vaishnaw during the deployment event, the sector’s manufacturing output has scaled fivefold over the last decade. This production surge is closely paired with an aggressive outward trade trajectory; electronics exports scaled six times over the same ten-year period, officially crossing the ₹3,25,000 crore threshold.

Deepening the Component Ecosystem

To transition from system-level assembly to deep-tech component localization, the government recently greenlit a dedicated electronic component manufacturing scheme. This policy framework is engineered to structurally mature the domestic supply chain, mitigate dependencies on imported sub-assemblies, and catalyze industrial workforce expansion. Currently, the electronics manufacturing sector accounts for an employment base of approximately 25 lakh individuals.

IP Safeguards and Supply Chain Resilience

Minister Vaishnaw emphasized that international hardware brands are increasingly anchoring their production pipelines in India due to two main technical and regulatory pillars:

• Enhanced Product Quality Standards: Rising yields and tighter quality control metrics across domestic fabrication and assembly lines.
• Robust Intellectual Property (IP) Safeguards: Tighter legal and technical frameworks protecting proprietary design architectures.

The state’s forward-looking roadmap relies on an integrated stack combining design-led innovation, manufacturing scaling, specialized technical skilling, and trusted hardware innovation. To secure long-term operational resilience against global market disruptions, India is actively focusing on securing diverse rare earth supply chains, establishing a trusted hardware baseline anchored tightly to IP protection and advanced engineering.

The post India’s Electronics Boost: SMT Expansion & Strategic Localization appeared first on ELE Times.

Introduction: When Power Defines the Limits of AI

As artificial intelligence expands across industries, the focus has shifted from just computing performance. Now, power systems under high-density AI infrastructure are the main constraint. Modern data centres with accelerator-rich clusters have intense and highly variable power demands.

When thousands of processing units ramp up at once, even millisecond-scale fluctuations in power delivery can ripple across racks, affecting performance and system stability. In such environments, power is not just a utility; it is a key determinant of operational reliability and scalability.

This shift is transforming data centre engineering. Jensen Huang says, “AI data centres are fundamentally different; they require new architectures for computing, networking, and power.” Power system transformation now drives the next generation of AI workloads.

The Evolving Power Profile of AI Workloads

AI workloads create distinct electrical behaviour compared to traditional enterprise applications. They rely on synchronised processing, with multiple accelerators running in parallel and quickly shifting between low and peak utilisation. These shifts cause sharp transient loads that immediately stress the power delivery network.

From an engineering standpoint, this poses two challenges. Infrastructure must deliver sustained power throughout training cycles and respond instantly to fluctuations while maintaining stable voltage. These demands set strict requirements for the entire power chain, from facility-level supply to board-level voltage regulators.

Power delivery now focuses on responsiveness, stability, and coordination, not just capacity.

Core Challenges in Maintaining Power Stability

A key challenge is managing transient load response. When multiple accelerators increase power draw simultaneously, the system must maintain stable voltage levels despite demand spikes. Any delay or inefficiency in response can cause voltage droop, affecting performance and stressing electrical components.

High-density deployment is also a major issue. AI-focused racks concentrate large power demand in tight physical spaces, making power distribution more complex. This concentration increases reliance on efficient conversion stages and highlights inefficiencies in traditional power architecture. Workload variability complicates the scenario. Training workloads, which involve running machine learning models to improve their performance, sustain high power consumption over long periods. Inference workloads, which use trained models to make predictions or classifications, create intermittent, bursty demand. At scale, these differences produce unpredictable aggregate loads that challenge conventional provisioning.

Overlaying these challenges is the tight coupling between power and thermal behaviour. As power increases, heat rises. This raises cooling requirements. This interdependency forms a feedback loop. Inefficiencies in one domain amplify stress in the other, so coordinated design is essential.

When Power Instability Becomes System Risk

In AI-driven environments, power instability does not remain localized; it propagates through the system, often with compounding effects. Even minor inconsistencies in power delivery can trigger a chain of operational issues, including:

• Accelerator throttling, reducing computational efficiency
• Node-level interruptions that disrupt distributed workloads
• Thermal stress escalation, impacting hardware reliability
• Increased overhead in workload redistribution and recovery

Such events may not always lead to immediate failure, but they degrade system performance and resilience over time. This makes it clear that power stability must be engineered proactively, rather than treated as an afterthought.

Engineering Approaches to Strengthen Power Stability

Addressing these challenges requires a shift to integrated, system-level engineering. The transformation begins with redesigning power-delivery architectures. Modern systems are optimised to improve transient response and maintain stable voltage levels under rapidly changing load conditions. Enhanced conversion efficiency and improved distribution reduce losses and maintain consistency.

Real-time monitoring and adaptive control are just as vital. By continuously tracking power use across nodes and racks, data centres can spot anomalies early and automatically adjust power allocation. This makes power management a dynamic, intelligent system rather than a static provisioning task.

Another critical advancement lies in workload-aware orchestration. Rather than treating compute demand as separate from infrastructure constraints, modern systems align workload scheduling with power availability. Distributing tasks more intelligently and avoiding synchronised demand peaks helps operators maintain a balanced, stable power profile.

To manage upstream variability, data centres are adding energy buffering solutions. Short-term storage helps absorb sudden spikes and smooth out power fluctuations. This decouples compute demand from instant grid changes, improving resilience and ensuring continuity during disturbances.

At a broader level, the integration of hardware and software design is becoming indispensable. Accelerators are being optimised for energy efficiency, while orchestration layers increasingly incorporate power-awareness into scheduling decisions. As Satya Nadella has emphasised, “Every layer of the computing stack must evolve to meet the demands of AI.” Power infrastructure is now a critical part of this evolution.

Power as a First-Class Resource

A defining shift in AI data centre design is recognising power as a first-class system resource, equal to compute and memory. This view requires coordinated management of compute clusters, networking, cooling systems, and energy delivery.

By treating power as a shared and dynamic resource, operators can optimise utilisation, reduce localised stress points, and improve overall system efficiency. This integrated approach represents a departure from traditional designs, in which power was often treated as a fixed constraint rather than an actively managed variable.

Industry Direction: Scaling Within Constraints

As organizations expand AI infrastructure, a clear divergence is emerging. Hyperscale operators are investing in purpose-built architectures designed to handle high-density, high-variability workloads. In contrast, many enterprise data centres are adapting existing infrastructure, often encountering limitations in power delivery and cooling capacity.

At the same time, sustainability considerations are becoming increasingly prominent. Energy efficiency is no longer optional—it is a critical factor influencing design decisions. This convergence of performance, reliability, and sustainability is shaping the next phase of data center evolution.

Future Outlook: Toward Autonomous Energy Management

Looking ahead, the future of AI-driven data centres lies in intelligent, self-regulating power systems. These systems will leverage predictive models to anticipate workload-driven demand, dynamically optimize energy distribution, and integrate seamlessly with evolving energy sources. In this emerging paradigm, AI will play a dual role-not only driving demand but also enabling smarter infrastructure management. As Sundar Pichai has noted, “AI will shape the infrastructure that powers it.” This feedback loop will define the trajectory of next-generation data centres.

Conclusion: Power Stability as the True Constraint of AI Growth

AI’s rapid progress brings huge computational power, but also exposes a major limit: delivering stable, efficient, and resilient power at scale. Power instability hurts performance, reliability, hardware life, and operational efficiency.

To meet these challenges, the industry must adopt a holistic approach. This should integrate advanced power delivery architectures, real-time adaptive control, and system-level optimisation. The evolution of AI infrastructure will depend on the effective combination of these elements.

Here, power stability is not just a support; it is the main constraint. The future of AI depends less on speed or scale and more on the reliability of the energy sustaining it.

The post Enhancing Power Stability in AI-Driven Data Centres: Emerging Engineering Approaches appeared first on ELE Times.

The Internet of Things (IoT) is expected to connect tens of billions of devices over the coming decade. One of the most significant challenges facing this expansion is the power supply. Conventional batteries increase maintenance costs, create environmental waste, limit device lifetimes, and become impractical in large-scale deployments. Energy-harvesting micro-power technologies are emerging as a transformative solution, enabling autonomous devices that derive energy from their surrounding environment. By harvesting radio-frequency signals, thermal gradients, mechanical vibrations, and ambient light, next-generation IoT nodes can operate for years—or potentially indefinitely—without battery replacement.
For electronics engineers, energy harvesting represents a convergence of ultra-low-power electronics, advanced materials, power management ICs, and wireless communication technologies.

A new generation of Energy-Harvesting Micro-Power Systems is poised to overcome this limitation. Instead of relying solely on batteries, these devices extract energy from their environment—capturing radio frequency (RF) signals, body heat, ambient light, and mechanical vibrations—to power sensors, processors, and wireless communication modules.
For electronics engineers, energy harvesting represents more than an incremental improvement. It is enabling the development of self-powered, maintenance-free IoT networks capable of operating for years without human intervention. As ultra-low-power electronics continue to mature, battery-free devices are expected to become a cornerstone of Industry 4.0, smart cities, healthcare wearables, and environmental monitoring systems.

Energy harvesting is moving IoT design away from the “battery-first” model toward ultra-low-power, maintenance-light nodes that capture energy from their surroundings. In practice, that means converting ambient light, RF energy, thermal gradients, vibration, or motion into usable electrical power, then storing and regulating it for a sensor, MCU, and radio burst. The result is a class of devices that can run where wiring is expensive or battery replacement is impractical.
For working electronics engineers, the key shift is not just the harvester itself; it is the full power chain. A successful design needs a harvester, an energy-storage element, cold-start circuitry, and a PMIC that can regulate tiny input power levels while protecting the load. Vendors also emphasize maximum power point tracking and ultra-low quiescent current because harvested power is often measured in microwatts or low milliwatts, not watts.

The most promising ambient sources map well to real deployment environments. RF harvesting is attractive for low-power tags and short-duty-cycle nodes because it can turn broadcast energy into a regulated supply, though received power is usually small and distance-dependent. Thermal harvesting uses temperature differences, including body heat or industrial heat gradients, and is a strong fit for wearables and machinery-adjacent sensors. Vibration and piezoelectric harvesting are natural choices for motors, pumps, rotating equipment, and transport assets.

Several companies are actively building this ecosystem. Silicon Labs positions its EFR32xG22E energy-harvesting family around battery-less operation and reference designs for solar-powered and RF-powered batteryless tags, aimed at asset tracking and similar use cases. EnOcean’s wireless sensors and switches harvest energy from motion, light, and temperature differences for maintenance-free building and industrial applications. Powercast focuses on RF energy harvesting for low microwatt and low milliwatt applications, including RFID and wearables.

Thermal and multi-source harvesting are also well covered by major component vendors. STMicroelectronics offers energy-harvesting and solar-charging ICs for ambient light or thermal differences, and its SPV1050 supports thermoelectric and PV harvesting with MPPT. e-peas describes product families for photovoltaic, thermal, RF, and vibration harvesting, with thermal and vibration sources explicitly sized for the microwatt-to-millwatt range. Texas Instruments has also published low-power harvesters for light, heat, and vibration sources, highlighting battery-free operation for sensor networks and wearables.
For engineers, the design challenge is usually energy budgeting, not RF protocol selection. The load profile must fit the harvested envelope: deep sleep for most of the time, brief wake-ups for sensing and transmitting, and enough storage to survive startup and energy gaps. In many cases, the “batteryless” node still includes a supercapacitor or thin-film storage element, but the maintenance burden drops sharply because the system no longer depends on periodic battery replacement.
Where this is headed is clear: battery-free or battery-minimal IoT nodes will first win in asset tracking, smart buildings, wearables, industrial condition monitoring, shelf labels, and distributed sensing, where installation and service costs dominate. The best near-term opportunities are not power-hungry always-on devices, but ultra-low-duty-cycle systems that can tolerate intermittent energy while still delivering useful telemetry. That is exactly the niche energy harvesting is becoming ready to fill.

Companies Leading Energy-Harvesting Micro-Power Innovation

e-peas: A pioneer in energy-harvesting PMICs. Key focus areas include: Solar harvesting, Thermal harvesting, Vibration harvesting, Battery-free IoT platforms. Their AEM-series PMICs are widely used in autonomous sensor nodes.

STMicroelectronics: Develops ultra-low-power microcontrollers and energy-management solutions for industrial IoT. Contributions include: STM32 ultra-low-power MCUs, Energy harvesting reference designs, and smart industrial sensing platforms.

Texas Instruments: Offers energy-harvesting power-management ICs and ultra-low-power processors. Applications include: Wireless sensing, Building automation, and smart metering.

Analog Devices: A leader in vibration energy harvesting. Products support: Predictive maintenance, Condition monitoring, Industrial automation

Wiliot: Known for battery-free Bluetooth tags powered by ambient radio-frequency energy. Applications include: Supply chain visibility, Retail tracking, Smart packaging. Their technology demonstrates practical, large-scale RF-powered IoT deployments.

Powercast: Specializes in wireless power transfer and RF energy harvesting. Solutions include: RF transmitters, Power receivers, Battery-free sensors. Used extensively in industrial and logistics applications.

EnOcean: A pioneer in self-powered wireless switches and building automation systems. Its products harvest energy from: Button presses, Indoor light, Temperature differences.

Schneider Electric: Integrates energy-harvesting sensors into smart-building and industrial-management systems. Focus areas include: Energy efficiency, Building automation, and Sustainable infrastructure.

The Road Ahead

The convergence of Energy harvesting, Ultra-low-power electronics, AI-enabled edge processing, and advanced semiconductor materials is creating a new class of autonomous devices.
Research laboratories are already developing systems capable of operating continuously on harvested microwatts while performing local machine learning inference. As semiconductor power consumption continues to decline, the vision of truly maintenance-free IoT networks becomes increasingly realistic.
For electronics engineers, the next decade will not simply be about designing lower-power products—it will be about designing products that generate their own power.

Conclusion

Energy-harvesting micro-power technology is rapidly becoming a foundational enabler of the next generation of IoT systems. As ultra-low-power electronics, advanced materials, and intelligent power-management architectures continue to mature, the vision of maintenance-free, battery-independent sensor networks is moving from research laboratories into commercial reality. For electronics engineers, mastery of energy harvesting, power optimization, and autonomous sensing architectures will be essential skills in the coming decade. The future IoT ecosystem will not merely communicate wirelessly—it will increasingly power itself from the energy already present in its environment.

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Courtesy DefTech Bharat & DefTech Con Knowledge Desk

Future wars will be won not only by superior weapons, but by superior sensing, networking, electronic dominance, and AI-driven decision-making across the electromagnetic spectrum.

The future battlefield will be defined not merely by firepower but by dominance of the electromagnetic spectrum. Across the world, military planners are investing heavily in electronic warfare (EW), artificial intelligence, software-defined systems, autonomous platforms, and resilient communications. For defence electronics engineers, this transformation presents an unprecedented opportunity to develop agile, intelligent, and rapidly deployable systems capable of operating in highly contested environments.

Recent military operations have demonstrated that information superiority and electronic dominance can determine mission success before the first kinetic strike is launched. The growing convergence of electronic warfare, advanced semiconductors, cognitive computing, and network-centric operations is reshaping how next-generation defence systems are designed.

The Electronic Battlefield Has Changed

Traditional electronic warfare systems were largely platform-centric, consisting of dedicated radar warning receivers, jammers, communication intercept systems, and electronic countermeasures operating independently. Today’s battlefield is radically different.

Modern EW is increasingly becoming a “system-of-systems” architecture where satellites, drones, radars, communication networks, command centers, and autonomous platforms work together as a unified electronic ecosystem.

This shift allows military forces to sense, decide, and act faster than their adversaries. The ability to identify a threat, process intelligence, distribute information, and launch a response within seconds has become a decisive advantage.

For design engineers, the challenge is no longer building standalone equipment but creating modular, networked systems capable of functioning as part of a larger digital battlespace.

Operation Sindoor: A Lesson in Modern Electronic Warfare

India’s Operation Sindoor demonstrated the growing importance of electronic warfare, intelligence fusion, and precision targeting in modern military operations.

While many operational details remain classified, publicly available assessments indicate that the operation reflected a high degree of integration between surveillance systems, communication networks, precision-guided weapons, and command-and-control architectures.

The success of such operations depends heavily on several electronic warfare capabilities:

• Real-time intelligence gathering
• Electronic support measures (ESM)
• Radar and communication signal monitoring
• Secure data networks
• Precision navigation and targeting
• Integrated command systems

The operation highlighted a critical reality of modern warfare: victory increasingly depends on controlling information and the electromagnetic spectrum.

Modern military forces are now investing heavily in systems that can detect enemy emissions, disrupt hostile communications, protect friendly networks, and maintain operational effectiveness even under electronic attack.

Gallium Nitride: The Foundation of Next-Generation RF Systems

One of the most significant advances in defence electronics is the adoption of Gallium Nitride (GaN) semiconductor technology.

Traditional radar and electronic warfare transmitters relied on traveling-wave tubes and other vacuum-tube technologies that required large cooling systems and bulky infrastructure.

For defence designers, this translates directly into reduced Size, Weight, Power, and Cost (SWaP-C).

Modern Active Electronically Scanned Array (AESA) radars, airborne jammers, counter-drone systems, and electronic attack platforms increasingly rely on GaN technology to achieve higher performance within smaller form factors.

The result is the ability to deploy powerful electronic warfare capabilities on tactical vehicles, unmanned systems, and even portable soldier-carried platforms.

Cognitive AI: The New EW Operator

Conventional electronic warfare systems depend on predefined threat libraries. However, modern adversaries employ agile waveforms, frequency hopping, low-probability-of-intercept communications, and adaptive radar systems.

To counter these threats, defence engineers are embedding artificial intelligence directly into EW platforms.

Once a signal is identified, the system can automatically generate optimal jamming, spoofing, or deception strategies without requiring human intervention.

The future electronic battlefield will increasingly be fought by autonomous systems capable of learning and adapting in real time.

Modular Open Systems Architecture (MOSA)

Another major trend transforming defence electronics is the adoption of Modular Open Systems Architecture (MOSA).

Historically, defence systems were highly customized and difficult to upgrade. Introducing a new capability often required extensive hardware redesign.

MOSA changes this paradigm by promoting standardized interfaces and plug-and-play architectures.

At the heart of this approach is the Software-Defined Radio (SDR).

This flexibility dramatically reduces lifecycle costs and accelerates technology refresh cycles.

As threats evolve faster than traditional procurement cycles, MOSA provides a practical path to continuous capability enhancement.

GNSS-Free Navigation: Operating When GPS Fails

One of the most important lessons from contemporary conflicts is the vulnerability of satellite navigation systems.

GPS jamming and spoofing have become routine tactics on modern battlefields.

As a result, defence designers are increasingly focusing on GNSS-independent navigation solutions.

Emerging systems combine:

• Inertial Navigation Systems (INS)
• Terrain contour matching
• Visual navigation
• RF beacon triangulation
• LTE and 5G positioning
• Sensor fusion algorithms

Artificial intelligence combines these inputs to maintain accurate positioning even when satellite signals are unavailable.

For autonomous systems, missiles, drones, and tactical vehicles, GNSS resilience is rapidly becoming a mission-critical capability.

AI-Driven SWaP-C Optimization

The pressure to reduce Size, Weight, Power, and Cost continues to influence every defence program.

Machine learning is now being used to optimize engineering trade-offs before physical prototypes are built.

AI-assisted design platforms can evaluate:

• RF chain performance
• Thermal management
• Antenna placement
• Power consumption
• Electromagnetic compatibility
• Structural constraints

Digital twin technology allows engineers to test thousands of virtual configurations, dramatically reducing development time and improving design quality.

The integration of AI into the design process is becoming as important as AI within the deployed system itself.

DefTech Bharat: Accelerating India’s Defence Innovation Ecosystem

As India’s defence technology ecosystem expands, industry platforms are playing a critical role in connecting innovators, manufacturers, startups, system integrators, armed forces, and policymakers.

DefTech Bharat is an innovation-led defence technology platform that brings together companies, engineers, startups, OEMs, and government stakeholders to showcase next-generation solutions across defence electronics, software, hardware, testing, telematics, AI, drones, quantum technologies, autonomous systems, and cyber defence. For innovators working on electronic warfare, secure communications, GaN-based RF hardware, modular SDR platforms, and GNSS-resilient navigation, it provides a timely venue to demonstrate technologies, exchange ideas, and build partnerships with the wider defence ecosystem. By combining exhibition, technical engagement, and B2B networking, DefTech Bharat positions itself as a launchpad for rapidly deployable, out-of-the-box defence solutions.

For innovators developing:

• Electronic warfare systems
• AI-enabled defence platforms
• Software-defined radios
• GaN-based RF solutions
• Counter-drone technologies
• Autonomous vehicles
• Secure communication systems

DefTech Bharat provides a valuable opportunity to demonstrate capabilities, interact with defence stakeholders, and explore collaborative development opportunities.

The platform enables technology providers to showcase working prototypes, advanced subsystems, and deployable solutions to government agencies, defence organizations, OEMs, and strategic partners.

As India pursues self-reliance in defence technologies under the Atmanirbhar Bharat initiative, such platforms serve as catalysts for innovation, commercialization, and technology transfer.

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The convergence of neuroscience, electronics, and artificial intelligence is driving one of the most transformative technological revolutions of the 21st century: Brain-Computer Interfaces (BCIs) and neurotechnology. Once confined to science fiction, BCIs are now rapidly evolving into practical systems capable of enabling direct communication between the human brain and external electronic devices. For electronics engineers, this emerging domain offers exciting opportunities in embedded systems, signal processing, flexible electronics, biomedical instrumentation, and AI-driven hardware development.

The Rise of Brain-Computer Interfaces

A Brain-Computer Interface is a system that acquires neural signals, processes them, and translates them into commands for computers, prosthetics, or other electronic systems. Traditional BCIs relied on electroencephalography (EEG), where electrodes placed on the scalp measure brainwave activity. While non-invasive EEG systems remain important for research and healthcare applications, recent advances in high-density electrode arrays and implantable bioelectronics are dramatically improving signal quality and functionality.

Modern BCIs can now interpret neural activity with remarkable precision, enabling paralyzed individuals to control robotic limbs, type text using thought alone, and even regain limited speech capabilities. The integration of machine learning algorithms with neural signal acquisition hardware has accelerated these developments significantly.

High-resolution brain–computer interface with electrode scalability and minimally invasive surgery

 

Flexible Bioelectronics: A Game Changer

One of the biggest engineering challenges in neurotechnology has been the mechanical mismatch between rigid electronic devices and soft biological tissues. Conventional silicon-based implants often trigger inflammation or degrade over time due to tissue damage. Flexible bioelectronics are solving this issue.

Flexible neural interfaces are built using biocompatible materials such as polyimide, graphene, conductive polymers, and ultra-thin gold traces. These devices can bend and stretch with brain tissue, reducing long-term damage and improving signal stability. Engineers are also exploring bioresorbable electronics that safely dissolve in the body after completing their function.

For electronics engineers, flexible electronics require innovation in several areas:

• Low-power integrated circuit design
• Stretchable conductive materials
• Miniaturized sensor architectures
• Wireless power transfer systems
• High-speed neural signal amplification

These systems must operate reliably while consuming extremely low power to minimize heat generation near sensitive neural tissue.

 High-Density Electrode Arrays and Neural Mapping

High-density electrode arrays are enabling researchers to record thousands of neurons simultaneously. Companies and research institutions are developing microelectrode arrays with unprecedented spatial resolution, allowing detailed mapping of neural activity patterns.

Advanced semiconductor fabrication techniques are making it possible to integrate thousands of microscopic electrodes onto a single chip. These arrays are combined with custom ASICs (Application-Specific Integrated Circuits) for signal amplification, filtering, analog-to-digital conversion, and wireless communication.

The data bandwidth generated by these systems is enormous. A next-generation BCI may process gigabits of neural data every second, creating major opportunities for engineers specializing in:

• Edge AI processing
• FPGA-based neural computing
• Real-time DSP systems
• Wireless telemetry
• Neuromorphic processors

Neuromorphic engineering, inspired by the architecture of the human brain, is becoming particularly important for efficient neural data processing. Unlike conventional processors, neuromorphic chips mimic biological neural networks and consume significantly less power.

Applications Transforming Healthcare

Healthcare remains the most promising application area for BCIs and neurotechnology. Neuroprosthetics are helping amputees control robotic limbs using brain signals with increasing accuracy and natural movement. Cochlear implants and retinal prostheses are restoring sensory functions to patients with hearing and vision impairments.

In neurological diagnostics, implantable neural sensors can monitor epilepsy, Parkinson’s disease, and other disorders in real time. Closed-loop neurostimulation systems can detect abnormal brain activity and automatically deliver corrective electrical stimulation.

Researchers are also investigating memory enhancement, depression treatment, and cognitive rehabilitation through targeted neural stimulation. These advancements depend heavily on reliable biomedical electronics and ultra-low-noise analog front-end design.

Patient controlling robotic prosthetic arm using BCI technology

Challenges and Ethical Considerations

Despite rapid progress, significant challenges remain. Neural signals are extremely weak and susceptible to noise, requiring sophisticated filtering and signal conditioning techniques. Long-term implant reliability, cybersecurity, and wireless communication safety are also major concerns.

Ethical issues surrounding cognitive enhancement, neural privacy, and brain data ownership are becoming increasingly important. As BCIs evolve from medical devices to consumer technologies, electronics engineers will play a critical role in designing secure and responsible systems.

Power management is another key challenge. Implantable devices require efficient energy harvesting or wireless charging technologies to avoid repeated surgical battery replacement. Advances in ultra-low-power electronics and energy-efficient communication protocols will be essential.

The Future of Neurotechnology

The future of BCIs lies in seamless human-machine integration. Emerging systems may eventually enable direct brain-to-brain communication, immersive virtual reality control, and advanced cognitive augmentation. Artificial intelligence combined with adaptive neural interfaces could create highly personalized neuroprosthetic systems capable of learning and evolving with users.

For electronics engineers, neurotechnology represents a multidisciplinary field where expertise in electronics, embedded systems, materials science, AI, and biomedical engineering converge. As the boundaries between biology and electronics continue to blur, BCIs are poised to become one of the defining technologies of the coming decades.

The era of intelligent bioelectronic systems has begun — and electronics engineers are at the center of this technological transformation.

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For more than five decades, the computing industry has relied on the von Neumann architecture, where memory and processing units are physically separated. While this architecture has enabled remarkable advances in computing power, it also faces significant challenges in today’s data-driven world. The continuous movement of data between memory and processors consumes enormous amounts of energy and creates performance bottlenecks, particularly in artificial intelligence (AI) and edge computing applications.

To address these limitations, researchers and semiconductor companies are increasingly turning to a radically different approach inspired by nature’s most efficient computing system—the human brain. Neuromorphic computing represents a paradigm shift in processor design, enabling machines to process information more like biological neural networks while consuming a fraction of the energy required by conventional systems.

Understanding Neuromorphic Computing

Neuromorphic computing refers to the design of hardware systems that mimic the structure and operation of the human brain. Unlike traditional processors that execute instructions sequentially, neuromorphic chips consist of artificial neurons and synapses that operate in parallel and communicate through event-driven signals known as spikes.

The human brain contains approximately 86 billion neurons interconnected through trillions of synapses. Despite this immense complexity, the brain operates on roughly 20 watts of power—less than many household light bulbs. Neuromorphic engineers aim to replicate this extraordinary efficiency in silicon.

In a neuromorphic system:

• Artificial neurons process incoming signals.
• Synapses store connection strengths and learning parameters.
• Information is transmitted only when meaningful events occur.
• Memory and computation are closely integrated.
• Learning can occur directly on the device.

This architecture significantly reduces the energy and latency associated with moving data between separate memory and processing units.

Why Traditional Architectures Are Reaching Their Limits

Modern AI applications generate enormous volumes of data from sensors, cameras, microphones, and connected devices. Conventional CPUs and GPUs must continuously shuttle this data between memory and processing cores, creating what is commonly known as the “memory wall.”

Key limitations include: High Power Consumption, Latency Challenges and Scalability Constraints. Neuromorphic computing addresses these challenges by bringing memory, learning, and processing closer together in a brain-like architecture.

Event-Driven Processing: The Key to Efficiency

One of the most innovative aspects of neuromorphic systems is event-driven computation. Traditional processors operate continuously, executing clock cycles whether useful work is being performed or not. Neuromorphic chips, however, remain largely inactive until significant events occur.

For example, consider a surveillance camera monitoring a quiet corridor. A conventional AI processor continuously analyzes every video frame. A neuromorphic processor only activates when movement or a meaningful change is detected. The result is intelligent systems that can remain operational for extended periods without frequent charging or cloud connectivity.

Real-Time Learning at the Edge

One of the most promising capabilities of neuromorphic hardware is on-device learning. Traditional AI systems are typically trained in data centers and deployed as fixed models. Updating these models often requires cloud access, large datasets, and significant computational resources.

Neuromorphic chips can adapt continuously based on experience, much like biological brains. This capability enables: Personalized Wearables, Autonomous Robots, Smart Sensors and Adaptive Industrial Systems. Such capabilities are particularly valuable in environments where network connectivity is limited or unavailable.

Applications Across Industries: Autonomous Vehicles: Self-driving vehicles process enormous amounts of sensory information from cameras, radar, LiDAR, and ultrasonic sensors. Healthcare and Wearables: Smart medical devices require continuous monitoring while maintaining long battery life. Industrial Automation: Factories increasingly rely on intelligent edge devices for predictive maintenance, quality inspection, and process optimization. Aerospace and Defense: Autonomous drones and surveillance systems benefit from low-power AI processing capable of operating independently in challenging environments. Internet of Things (IoT): Billions of connected devices generate vast quantities of sensor data.

Leading Neuromorphic Hardware Developments

Several organizations are actively advancing neuromorphic technology: Intel Corporation has developed the Loihi family of neuromorphic research chips capable of on-chip learning and adaptive processing. IBM pioneered large-scale neuromorphic architectures with its TrueNorth processor. European Human Brain Project has invested heavily in brain-inspired computing research. Numerous startups are developing specialized neuromorphic solutions for edge AI, robotics, and industrial applications.

Technical Challenges Ahead

Despite significant progress, neuromorphic computing remains an emerging field. Key challenges include: Programming Complexity: Developing software for spiking neural networks differs substantially from conventional programming methodologies. Ecosystem Maturity: Tools, frameworks, and standards remain less mature than those available for CPUs, GPUs, and traditional AI accelerators. Commercial Scalability: Manufacturing and integrating neuromorphic hardware into mainstream products requires further technological advancement and industry adoption. Benchmarking Difficulties: Comparing neuromorphic performance against conventional systems remains challenging because the architectures operate fundamentally differently.

The Future of Brain-Inspired Computing

As AI increasingly moves from centralized data centers to intelligent edge devices, energy efficiency and real-time adaptability become critical requirements. Neuromorphic computing offers a compelling solution by emulating the principles that make the human brain remarkably powerful and efficient.

Rather than replacing traditional CPUs and GPUs entirely, neuromorphic processors are likely to emerge as specialized accelerators for applications requiring low power consumption, continuous learning, and rapid decision-making at the edge.

For working engineers, neuromorphic computing represents more than just another processor innovation. It signals the beginning of a new computing paradigm where machines learn, adapt, and respond with unprecedented efficiency. As edge AI, robotics, autonomous systems, and wearable technologies continue to expand, brain-inspired architectures may become a foundational component of next-generation intelligent systems.

Neuromorphic computing is redefining how engineers think about processing, memory, and intelligence. By mimicking the brain’s structure and operation, neuromorphic chips achieve remarkable energy efficiency while enabling real-time learning and adaptation.

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Introduction: When Speed Outpaces Validation

Enterprise software is no longer built for stability. It is built for continuous change. Modern systems evolve over distributed architectures, cloud-native platforms, and microservice ecosystems, with release cycles measured in days rather than months. Against this rapid evolution, the customary boundaries of testing are being fundamentally redefined.

Validation, once a discrete phase in the development lifecycle, now operates under constant pressure to keep pace with rapid deployment. The challenge is no longer simply guaranteeing correctness, but doing so continuously, at scale, and amid mounting system complexity.

Conventional automation frameworks, designed for predictability and control, are beginning to show their limitations. As systems evolve dynamically, static test scripts and rule-based execution models struggle to remain effective. It is within this context that AI-augmented test automation is emerging not as a replacement, but as an essential evolution of how enterprise systems are validated.

From Scripted Automation to Adaptive Testing Systems

Traditional automation has long relied on predefined scripts and deterministic workflows. While this strategy delivers consistency, it is inherently rigid. Even minor changes in application interfaces or workflows is able to disrupt test execution, causing frequent maintenance cycles that consume time and engineering effort.

AI introduces adaptability into this equation, fundamentally shifting the testing landscape. By using historical data, execution patterns, and system behaviour, AI-augmented frameworks can interpret changes and operate dynamically. As a result, testing systems begin to move past static execution toward context-aware validation, where decisions are informed by data rather than predefined rules alone.

This shift isn’t incremental; it is a redefinition of automation itself. Testing no longer centres solely on executing what is known, but on intelligently responding to what changes. As Satya Nadella has emphasised, “Every company is becoming a software company, and agility is key regarding innovation.” In such an environment, testing must evolve into an enabler of that agility, not a constraint on it.

The Scaling Challenge: Complexity at Enterprise Level

At enterprise scale, testing is not simply about validating features—it is about ensuring the coordinated functioning of distributed systems. Applications span multiple services, environments, and configurations, each introducing its own layer of variability.

What makes this challenge particularly significant is not just the volume of test cases, but the rate at which they become outdated. As systems change, test suites expand, execution times increase, and maintenance overhead grows disproportionately.

The core pressures can be summarized as:

• Expanding and continuously evolving test suites
• Increasing difficulty in maintaining reliable test execution
• The need for comprehensive coverage across diverse system states

These challenges do not scale linearly—they compound. Without intelligent optimization, testing becomes a bottleneck, slowing down the very innovation it is meant to support. AI-augmented automation addresses this by introducing prioritization, reducing redundancy, and aligning testing efforts with actual system risk.

Resilience Through Self-Healing Automation

One of the most tangible advancements enabled by AI is the concept of self-healing automation. In traditional systems, test failures often result from minor interface changes—renamed elements, altered layouts, or modified identifiers. These failures require manual intervention, creating inefficiencies in otherwise automated workflows.

AI-driven systems mitigate this limitation by recognizing patterns and relationships within application structures. Instead of failing immediately, they can identify alternative elements or pathways, allowing tests to continue execution. This capability significantly reduces maintenance cycles and enhances overall system resilience.

More importantly, it shifts the role of automation from a fragile executor to a robust validation layer capable of adapting alongside the applications it tests.

Intelligent Test Design: From Coverage to Risk-Based Validation

A critical evolution in AI-augmented testing also lies in how test cases are generated and optimised. Established approaches often prioritise exhaustive coverage, leading to large but inefficient test suites. In contrast, AI enables a more strategic model—one that focuses on risk, impact, and system operation.

More specifically, by analysing historical defects, usage patterns, and code changes, AI systems can identify which areas of an application are most likely to fail and prioritise testing accordingly. This switch from coverage-driven to risk-based validation amounts to a significant improvement in both capability and effectiveness.

Instead of attempting to execute all possible scenarios, testing becomes targeted and adaptive, ensuring that critical paths receive the highest level of scrutiny, thus increasing the effectiveness of the entire process.

Continuous Testing in High-Velocity Pipelines

Integrating testing into CI/CD pipelines has fundamentally changed how software is delivered. While the speed of these pipelines is transformative, it also introduces challenges. Testing must provide rapid, reliable feedback without becoming a performance bottleneck.

AI addresses this by introducing decision intelligence into test execution. Rather than running all tests indiscriminately, systems select and prioritise tests based on relevance to recent changes. This reduces execution time while maintaining validation quality.

In this model, testing is no longer a passive checkpoint; it becomes an active, intelligent participant in the delivery pipeline, continuously adjusting to the system’s evolving state.

From Test Execution to Quality Intelligence

Looking beyond automation and execution, AI delivers a wider transformation: the evolution of testing into a source of engineering intelligence. By analysing large volumes of test data, system logs, and defect histories, AI systems can discover patterns that inform not only testing strategies but also system design decisions.

This shift repositions testing from a reactive activity to an anticipatory capability. Instead of identifying defects after they occur, systems can predict possible failure points and guide engineering efforts toward more robust designs.

In this sense, testing acts not only as a validation function but also as a contributor to overall system quality and reliability.

Human Expertise in an AI-Augmented Ecosystem

Despite the growing role of AI, human expertise remains central to the testing process. AI excels at handling scale, pattern recognition, and repetitive execution, but it lacks contextual judgment and domain-specific insight.

Human testers bring critical thinking, scenario understanding, and strategic supervision capabilities that cannot be fully automated. The most effective testing environments are therefore not AI-driven in isolation, but AI-augmented, where people and computers’ capabilities complement each other.

This balance ensures that, as efficiency improves, the depth and reliability of validation are not compromised.

Adoption Realities: Engineering and Integration Challenges

The adoption of AI-augmented testing is not free from challenges. Integrating intelligent systems into existing enterprise environments requires careful planning, particularly in data quality, tool compatibility, and workflow alignment.

Organisations must ensure sufficient data is available to train AI models effectively, while also preserving transparency in decision-making. Integration with legacy systems can make deployments more complex, requiring incremental adoption strategies.

These considerations highlight an important reality: the transition to AI-augmented testing is as much an organisational shift as it is a technological one.

Future Outlook: Toward Autonomous Testing Ecosystems

Going forward, the trajectory of test automation points toward increasing autonomy. AI systems are expected to take on more responsibility in managing test lifecycles, from generation and execution to optimisation and maintenance.

Future systems will not only execute tests but also constantly learn from outcomes, improving strategies and adjusting to evolving system behaviour. This progression moves testing closer to a self-sustaining ecosystem, where validation progresses alongside the software it supports.

As Sundar Pichai has noted, “AI is one of the most profound technologies we are working on.” Its application in testing demonstrates a broader transformation, one in which intelligence becomes embedded in the core of engineering processes.

Conclusion: Redefining the Role of Testing in Enterprise Systems

AI-augmented test automation represents more than an enhancement of existing practices; it constitutes a fundamental change in how enterprise systems are validated. In an age distinguished by speed, scale, and complexity, established approaches are no longer sufficient.

Testing must evolve into an intelligent, adaptive capability, one that not only verifies system operation but also actively contributes to its reliability and dependability. AI enables this transformation by introducing adaptability, insight, and capability into every stage of the testing lifecycle.

As enterprise systems continue to grow in complexity, the role of AI in testing will become increasingly central. The future of quality assurance will not be defined by how extensively systems are tested, but by how intelligently they are validated consistently, efficiently, and at scale.

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Any discussion of modern AI system performance must include MLCommons and its MLPerf benchmark suite, which has become the industry’s de facto standard for measuring machine learning performance. Since its debut in 2018, MLPerf has provided a neutral, peer-reviewed framework for comparing hardware and software platforms across a broad range of AI workloads.

The original MLPerf benchmarks reflected the dominant AI workloads of the late 2010s. Early inference tests focused on models such as image classification with ResNet-50, natural language processing with Bidirectional Encoder Representations from Transformers (BERT), object detection with RetinaNet, and recommendation with Deep Learning Recommendation Model (DLRM).

These workloads were important and representative at the time, but they shared one characteristic: they were highly parallel and relatively easy to map onto GPU architectures.

For several years, benchmark results reinforced a simple narrative. Each new generation of accelerators delivered higher throughput, lower latency, and better energy efficiency. Because the workloads aligned well with GPU strengths, the benchmark curves rose steadily and predictably.

The generative AI shockwave: Rewriting the rules of MLPerf

Autoregressive LLMs introduced a fundamentally different inference pattern. Prompt processing remained highly parallel, but token generation became sequential and memory bound. Suddenly, raw TeraFLOPS no longer told the whole story.

MLPerf began incorporating this new reality in stages. Inference v4.0 introduced the first LLM benchmark based on Meta platform Llama 2 70B. This benchmark measured token throughput and provided the industry with its first standardized method for comparing LLM inference systems.

MLPerf Inference v5.0 released in 2025 significantly expanded the generative AI focus. It added Llama 3.1 405B Instruct, a 405-billion parameter model with a 128,000-token context window. The benchmark also introduced an interactive variant of Llama 2 70B that imposed strict limits on Time to First Token (TTFT) and Time Per Output Token (TPOT), two metrics that directly capture user experience in conversational applications.

These additions were pivotal because they exposed the core weakness of GPU-based inference systems. When unconstrained by latency, GPUs could buffer requests, create large batches, and deliver excellent throughput. Under interactive latency limits, batching opportunities shrank, hardware utilization dropped, and throughput fell sharply.

In other words, MLPerf began measuring not just how fast a system could run under ideal conditions, but also how responsive it remained under realistic conditions.

Inference disaggregation: Optimization of resources

This evolution reached another milestone in MLPerf Inference v5.1 and the emerging v6.x era. The benchmark suite broadened its focus to include increasingly sophisticated workloads, including reasoning models such as DeepSeek-R1 and more demanding long-context applications. At the same time, submissions began showcasing system-level optimizations such as inference disaggregation, where prompt processing and decoding are assigned to different accelerator pools.

Disaggregation has become one of the most consequential developments in modern inference benchmarking.

Historically, MLPerf treated each benchmark run as a single system under test, leaving vendors free to optimize their hardware and software stacks as they saw fit. As long as submissions complied with accuracy and latency requirements, any architectural technique was fair game.

This openness allowed participants to introduce increasingly sophisticated serving strategies. One of the most effective has been the separation of prefill and generation across distinct groups of accelerators. The prefill cluster handles the compute-intensive prompt processing stage, while the generation cluster focuses exclusively on token decoding.

In controlled benchmark scenarios, where prompt lengths and output lengths are known in advance, disaggregation can produce dramatic gains. By eliminating interference between the two phases, systems reduce preemption and improve latency-sensitive throughput.

Yet this raises an important question. Does the benchmark still measure accelerator capability, or is it increasingly measuring system orchestration? The answer is both.

Modern AI performance depends on the interaction between processor, memory hierarchy, interconnect fabric, runtime software, and serving algorithms. MLPerf has evolved accordingly. It now rewards system-level innovation rather than isolated chip performance.

That shift is entirely appropriate, but it also means benchmark results must be interpreted carefully.

A disaggregated configuration optimized for long document summarization may perform brilliantly in MLPerf while delivering more modest benefits in production environments where workloads vary continuously. Real-world deployments must cope with unpredictable prompt lengths, bursty traffic, and rapidly changing ratios of prefill to generation demand.

Consequently, MLPerf increasingly measures a system’s ability to align resources with a known workload profile. This is a valuable metric, but it’s not synonymous with universal real-world performance.

Illustrative comparison: MLPerf 5.x versus MLPerf 6.x

Table below illustrates how benchmark methodology evolved as MLPerf shifted from throughput-oriented LLM tests to more latency-sensitive and system-aware workloads. The numbers are representative rather than exact, but they reflect the broad trends seen in published results and vendor disclosures.

Publicly discussed MLPerf inference results based on Llama 3.1 405B LLM run on a leading-edge GPU-based processor in three scenarios (off-line, server mode, and interactive mode) highlight MLPerf’s evolution. Source: Author

From chip benchmark to system benchmark

The history of MLPerf mirrors the evolution of AI itself.

The early benchmark suites focused on relatively static workloads that aligned naturally with the strengths of GPU architectures. Tasks such as image recognition, recommendation systems, and conventional deep learning inference relied heavily on dense matrix operations and large-scale parallelism, allowing GPUs to demonstrate exceptional throughput and scalability. In that era, benchmark leadership was closely associated with raw compute capability, memory bandwidth, and increasingly larger accelerator configurations.

The rise of generative AI fundamentally changed that equation.

As autoregressive LLMs became the dominant workload, MLPerf evolved accordingly, introducing larger models, longer context windows, interactive server scenarios, and increasingly strict latency constraints. These additions exposed a critical reality: while GPUs remain extraordinarily efficient during the highly parallel prefill phase, they are far less efficient during token generation, where inference becomes sequential, memory-bound, and heavily dependent on latency-sensitive execution.

This shift transformed the meaning of benchmark performance.

Modern MLPerf results no longer measure the capabilities of an isolated accelerator alone. Instead, they measure the effectiveness of an entire inference architecture.

Disaggregation, scheduling policies, key-value (KV) cache management, streaming pipelines, runtime orchestration, and workload balancing have become just as important as the underlying silicon itself. In many cases, the benchmark winner is no longer the system with the most compute power, but the one that most effectively adapts a fundamentally sequential workload to hardware originally designed for massively parallel graphics and HPC computation.

As a result, benchmark interpretation has become significantly more nuanced. The headline numbers increasingly reflect how intelligently the system orchestrates resources across racks of accelerators, separates prefill from generation, minimizes preemption, and maintains throughput under realistic latency constraints. MLPerf has evolved from a pure hardware benchmark into a broader measure of system architecture and software orchestration.

At the same time, this evolution reveals something even more profound. The latest MLPerf 6.x requirements implicitly highlight the growing limitations of conventional GPU architectures for real-time LLM inference. The industry has reached a point where increasingly sophisticated scheduling mechanisms and disaggregated serving infrastructures are being used to compensate for a deeper architectural mismatch between autoregressive inference and massively parallel processors.

In many respects, the benchmark itself is beginning to suggest the next major transition in AI infrastructure design.

Rather than continuing to optimize architectures originally developed for graphics rendering and parallel numerical computing, the future may require entirely new inference-centric architectures built specifically for the unique characteristics of the LLM generation. Such architectures would need to deliver high utilization and low latency even with very small batch sizes—potentially down to a single user request—while minimizing data movement, reducing memory bottlenecks, and supporting continuous token generation without relying on increasingly complex orchestration layers to hide inefficiencies.

In that sense, MLPerf has become more than a benchmark suite. It is now a window into the architectural tensions shaping the future of AI computing, revealing both the extraordinary adaptability of modern accelerator systems and the growing need for a fundamentally new class of inference hardware designed from the ground up for the realities of autoregressive AI.

Lauro Rizzatti is a business development executive with Vsora, a technology company offering semiconductor solutions that redefine design performance. He is a noted chip design verification consultant and industry expert on hardware emulation.

Editor’s Note

This is Part 2 of the mini-series that examines how LLM inference forced changes to MLPerf benchmarking. In Part 1, contributor Lauro Rizzattti analyzes LLM inference across its two processing phases—prefill versus generation—and highlights how this workflow exposes structural inefficiencies in GPU-based accelerators.

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The post MLPerf and the rise of latency-aware LLM benchmarking appeared first on EDN.

By Tzu-Yi Lee

Revolutionizing semiconductor fabrication, ALD, ALE, and NBE deliver atomic-scale precision, driving unprecedented performance and scalability in next-generation miniaturized devices.

Introduction

With the rapid growth of the semiconductor industry, Moore’s law has become a core guiding principle for the continuous advancement of electronic devices. Moore’s law predicts that the number of transistors will double every two years, a trend that is driving the continued reduction in device and circuit size. As the size of semiconductor devices shrinks further, the complexity and accuracy of the manufacturing process increase dramatically, requiring the introduction of ultra-precision and ultra-fine technologies into the semiconductor process to ensure device performance and reliability. Among these technologies, etching and deposition are particularly crucial as they form the foundation for achieving high-performance semiconductor devices. They play an essential role in enabling device miniaturization and increasing functional density. Fig. illustrates the trend in semiconductor manufacturing technology from 2000 to 2035, reflecting advancements beyond Moore’s law and incorporating more-than-Moore principles. As transistor technology evolves to Integrated Circuit (IC) evolves, we can see a progression from scale devices and wires to scale basic logic units to scale system functions. Early developments in transistor technology, such as geometric scaling at the 90 nm node, included introducing strained Si and using copper (Cu) for back-end-of-line (BEOL) interconnections. Over time, technological advances drove transistors to 40 nm and 28 nm nodes, when the use of high-k gate dielectrics and metal gate technologies appeared, marking the era of equivalent scaling. With the further development of process technology, from 20 nm to 7 nm, transistor technology entered the era of heterogeneous scaling (post-Moore scaling), which included the widespread use of fin field-effect transistors (FinFETs). FinFETs provide superior channel control due to their three-dimensional structure, which allows the gate to surround the channel on multiple sides, enhancing gate control and reducing short-channel effects. In recent years, the introduction of gate-all-around (GAA) transistors, an advanced technology, has further shrunk device size and provided better control of short-channel effects, reduced leakage current, and enhanced switching performance. As technology nodes advance to 5 nm and beyond, innovations such as GAA transistors provide better control of short-channel effects, reduced leakage, and enhanced performance. Future scaling is expected to incorporate compound field-effect transistors (CFETs), 2D semiconductors, and hybrid integration, which not only sustain Moore’s law but also expand into more-than-Moore functionalities, such as photonic integration, quantum technologies, and neuromorphic computing. These advancements heavily rely on nanoscale etching and deposition processes, such as atomic layer deposition (ALD), atomic layer etching (ALE), and neutral beam etching (NBE), which are critical in achieving the precision and performance required for next-generation devices. This article shows how these advanced techniques drive semiconductor fabrication, supporting continued progress and enabling breakthroughs beyond Moore’s law.

Fig. 1. Evolution of transistor density and gate length in ICs.

Definition and background

The etching process involves removing a material from a surface through chemical or physical methods, which typically plays a key role in semiconductor manufacturing. Precise control of this process, including major factors such as etch depth, etch profile, surface roughness, and uniformity, is critical to ensuring the performance and reliability of micro- and nanoelectronic devices. Wet etching, which utilizes a chemical reaction in a bath environment, is known for its low cost, ease of implementation, and high material selectivity. Conversely, dry etching is performed through physical and chemical reactions in a vacuum chamber, providing greater precision depth control, profile selectivity, and the ability to define critical feature dimensions.

Atomic layer etching (ALE)

ALE is a highly precise technique critical for fabricating nanoscale semiconductor devices. By alternating between adsorption and reaction steps, ALE achieves the removal of single atomic layers per cycle, providing exceptional control and minimizing surface roughness. This method, derived from ALD techniques, involves sequential exposure to different reactive gases, with intermediate purging steps to ensure precise layer-by-layer removal and maintain atomic-scale accuracy. ALE is particularly advantageous in the fabrication of advanced 3D integrated circuits (3D ICs) and memory devices. In 3D IC manufacturing, ALE addresses the challenges of creating complex 3D transistor architectures, such as GAA and multi-bridge-channel FETs (MBCFETs). By enabling atomic-scale etching, ALE provides exceptional control over morphology and depth, ensuring precise patterning for nanoscale features.

Neutral-beam etching (NBE)

NBE represents a significant advancement in the etching processes for GaN-based HEMTs and light-emitting diodes (LEDs). This method effectively addresses the critical challenge of plasma-induced damage, which is prevalent in conventional etching techniques such as ICP-RIE. GaN materials are highly valued in the semiconductor industry for high-power and high-frequency applications. However, achieving normally-off operation in GaN-based HEMTs remains challenging due to the plasma-induced damage associated with techniques such as gate recessing. NBE offers a potential solution to minimize such damage and enhance device performance.

Deposition techniques

Thin film technology is an advanced approach aimed at improving the structural, electrical, magnetic, optical, and mechanical properties of bulk materials. It has found widespread application in semiconductor devices, integrated circuits, transistors, liquid crystal displays, light-emitting diodes, solar cells, sensors, and micro-electromechanical systems (MEMSs). The distinctive properties of thin film materials are crucial for the technological advancement of various electronic, electrical, magnetic, and optical devices. These films are created using various physical or chemical methods, each of which is essential for producing ultra-thin materials known for their uniform, conformal, and controllable thickness. As atomic and near-atomic scale manufacturing (ACSM) evolves, the necessity of depositing high-quality, impurity-free thin films for laminated structures becomes crucial.

The future of ALD, ALE, and NBE technologies is promising as ongoing advancements continue to address the evolving demands of semiconductor manufacturing. Numerous optimization strategies have been employed to enhance their precision and efficiency. In particular, controlling deposition thickness in ALD, achieving atomic-level etching with ALE, and minimizing surface damage through NBE have proven crucial for improving device performance. Geometrical parameters such as layer thickness, etch depth, and surface passivation have significant impacts on device reliability and durability. Addressing thermal management, particularly in high-power applications, becomes essential as devices scale further. Future efforts could explore the use of more thermally conductive substrates and the refinement of etching profiles to minimize defects and improve device performance. Additionally, optimizing contact technologies to reduce resistance and ensure smooth surface morphology will be critical. Looking ahead, further research should focus on enhancing the uniformity and precision of these processes for advanced applications in micro-LEDs, high-speed communications, and optoelectronics. Future research should consider the performance capabilities of ALD, ALE, and NBE technologies to promote the development of next-generation semiconductor devices.

The post Advances in core technologies for semiconductor manufacturing appeared first on ELE Times.

The state cabinet on Wednesday approved an amendment to the state’s Semiconductor Policy-2024 to fine-tune and adapt it to specific needs under the India Semiconductor Mission. Officials said the amendment would provide greater flexibility to investors. An official said that the move would accelerate the establishment of semiconductor units, support India’s efforts to build a domestic semiconductor ecosystem, and reduce dependence on imports of critical eleсtronic components. An official spokesperson said that the changes were aimed at providing policy support for investors and aligning the framework with the Centre’s India Semiconductor Mission. The Semiconductor Policy-2024 was notified on Jan 19, 2024, and will remain in force for five years. Officials said that the amendments would not entail any additional financial burden on the state exchequer.

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