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Почесна відзнака Вченої ради КПІ ім. Ігоря Сікорського Григорію Лупаренку KPI4U-2 вт, 06/30/2026 - 17:30

Advanced AI systems are forcing the semiconductor industry to rethink the boundary between silicon, package, board, power delivery, memory, cooling, and manufacturing. For several years, the dominant discussion has centered on advanced packaging capacity, high-bandwidth memory (HBM) integration, large interposers, organic substrate constraints, glass-core substrates, and scaling limits of 2.5D and 3D integration.

That discussion remains valid. But a deeper system question is emerging. What happens if the package substrate is no longer the center of the system-integration hierarchy? This question becomes especially important when comparing three architectural directions:

• CoWoS-style 2.5D integration
• Wafer-scale integration
• CoWoP/chip-on-wafer-on-platform-PCB concepts

Each approach is trying to solve the same industry problem: how to scale AI compute density, memory bandwidth, transient power delivery, thermal control, and multi-die integration beyond the physical limits of conventional packaging stacks. However, each architecture moves the bottleneck to a different place.

Chip-on-Wafer-on-Substrate (CoWoS) makes advanced packaging central to AI and high-performance compute (HPC) scaling. Next, wafer-scale integration pushes silicon integration to the extreme. Finally, Chip-on-Wafer-on-PCB (CoWoP) may create a new middle architecture where the platform PCB becomes part of the governed realization corridor.

Therefore, it’s not only a packaging phenomenon; it’s also about system realization.

CoWoS: The proven advanced packaging path

CoWoS has become one of the most important advanced-packaging architectures for AI accelerators and HPC silicon. It enables logic die, HBM stacks, and high-density interconnect to be integrated through an interposer and then connected to a package substrate and board.

The strength of CoWoS is apparent. It provides high-density die-to-die and die-to-HBM connectivity, supports large AI/HPC modules, and has become a production-proven integration path for high-bandwidth systems. However, CoWoS also exposes the limits of the modern package stack. See the complex corridor below:

Die/HBM → interposer → package substrate → PCB → voltage regulator module (VRM)/system

The package substrate must support escape routing, power delivery network (PDN) distribution, coefficient of thermal expansion (CTE) transition, mechanical stability, manufacturing yield, decoupling strategy, signal integrity (SI)/power integrity (PI) control, warpage management, and board attach reliability. And as package size increases, these challenges become more critical.

Many of the hardest problems in advanced AI packaging aren’t located in silicon; they occur in the package and package-to-board realization path.

• Warpage
• Substrate availability
• Package size
• Thermal gradients
• PDN impedance
• Loop inductance
• dI/dt response
• Decoupling placement
• SI/PI discontinuities
• Manufacturing complexity

In other words, CoWoS is powerful, but the package substrate becomes a major convergence burden. This is why glass-core substrates are receiving so much attention.

Glass substrates help, but they don’t remove corridor

Glass can improve dimensional stability, reduce warpage, provide better CTE control, support finer routing environments, and improve vertical power-delivery paths with through-glass vias (TGVs). For large AI/HPC packages and future electro-optical integration, these advantages are meaningful.

But glass should not be treated as a complete escape from package realization complexity. In most practical glass-core substrate architectures, the glass is primarily the core and the build-up layers still there. That means many high-speed routing-density challenges remain concentrated in the top build-up structure.

Moreover, bottom-side routing through the core is still not equivalent to short top-side interconnect. Signals passing through TGVs and returning through lower layers still face discontinuities, parasitics, reference-plane challenges, and SI/PI governance requirements.

So, glass changes the package problem, but it does not eliminate it. This distinction matters because CoWoP is not simply about replacing one substrate material with another. It’s about asking whether the realization hierarchy itself can change.

Wafer-scale integration: The extreme silicon path

Wafer-scale integration takes a different route. Instead of assembling many dies through a package-level integration strategy, it expands the silicon system itself. The result is an extremely large compute fabric with direct wafer-level integration, specialized power delivery, cooling, redundancy, and system infrastructure.

This can be technically powerful because it removes many conventional package boundaries and creates a very large on-wafer compute fabric. At the same time, however, wafer-scale integration does not eliminate realization complexity. It relocates it.

The board, power architecture, cooling system, mechanical structure, redundancy strategy, yield-management approach, and system-level service model must all adapt around a very large silicon platform. A useful way to summarize the difference is that wafer-scale integration expands silicon until the system must adapt around it. That can be attractive for certain AI workloads and specialized systems, but it’s not necessarily the most flexible path for every AI accelerator, custom ASIC, chiplet platform, or memory-rich architecture.

CoWoP: A possible middle architecture

CoWoP is interesting because it may offer a third path. Instead of the traditional path comprising die/HBM, interposer, package substrate and PCB, CoWoP points toward a shorter realization path.

Die/HBM → interposer/wafer-level structure → platform PCB

The deeper architectural value is not simply cost reduction. The deeper value is that CoWoP may change the power, memory, mechanical, and system-realization architecture. If the package substrate is reduced or removed, the system no longer needs to carry as much of the convergence burden through three separate layers: interposer, package substrate, and PCB.

Instead, the corridor becomes more direct. However, this directness should not be oversimplified. A realistic CoWoP architecture cannot simply assume that a fine-pitch silicon interposer can land directly onto a platform or PCB without a transition strategy.

The most important challenge may be the transition between wafer/interposer precision and PCB manufacturability. That transition may define whether CoWoP becomes a practical system architecture or remains only an attractive concept.

Dr. Moh Kolbehdari is senior director of IC/packaging at Socionext US.

Editor’s Note

This is Part 1 of the mini-series on advanced packaging. Part 2 continues with the advanced CoWoP concept: pitch translation, transition patches, VRM and memory placement, UCIe routing, and trusted realization governance.

Related Content

• True Wafer-Level Packaging
• Wafer Level Chip Size Package (WLCSP) Guidelines
• Intel’s Embarrassment of Riches: Advanced Packaging
• Nvidia, TSMC, and advanced packaging realignment in 2025
• Intel flash move could put wafer-level packages on the map

The post CoWoS, wafer-scale and CoWoP: Why AI packaging bottleneck is moving appeared first on EDN.

Ones and zeroes: are clustered or spread out bits better? “It depends,” is the answer. Well, at least sorta.

In the Comments section of a recent Design Idea for a DAC (Reference 1), one reader expressed a full-throated preference for an alternative to the common type of PWM used therein. For this “common” PWM, the ones in a repetitive cycle are “clustered” together, as are the zeroes. The reader’s preferred alternative is a “spread” type, in which the ones and zeroes are evenly disbursed within each cycle.

The clustered PWM tends to concentrate energy toward the lower frequencies, versus toward the higher with the spread PWM. Noting the relative ease of filtering out the higher frequencies, the reader argued that a microcontroller implementing the spread PWM filtered by a first order low pass (single resistor, single capacitor) filter was superior to the clustered version followed by a more complex third order filter (three pairs of these components.) So, which is the better choice? Let’s take a look.

The job of a PWM filter

PWMs generally produce repetitive sequences of NO ones and NZ zeroes of length N = NO + NZ. A sequence’s filtered resolution is 1/N. Its duty cycle (DC) is its average value, NO / N. The filter will take some settling time TS to get to within some value VST of a new DC. And as long as DC is neither zero nor one, there will be an AC “ripple” signal of some level at the filter output.

Not only must the ripple signal’s contribution to TS be considered, but its post-setting time peaks and valleys must be closer than some error value VRip to DC. Typically, VRip is set to .5/N. The ideal filter meets this requirement while minimizing TS for a VST of 1/N. These requirements must hold for all DCs and transitions between them.

Verdict first, then the trial

With apologies for my paraphrase of a famous quote from Lewis Carroll’s Queen of Hearts, there’s enough math and batch file simulations required to adjudicate this PWM shoot-out that I thought it best to present the somewhat surprising (to me at least) conclusions without forcing you to first endure the derivations (perhaps this reported result will spur an interest in that math). Figure 1 provides the summary:

Figure 1 This graph shows the settling time TS for clustered and spread PWMs at various clock speeds. The spread filter employs a single resistor and capacitor; the clustered, 3 pairs of the same (see Table 1 for filter details.) Dividing the clock frequency by a factor multiplies the settling time by that same factor. The error VST at the settling time is 1/N. The post-settling time absolute maximum ripple error VRip is .5/N.

If implemented fully in hardware, such as with an FPGA, it would be possible to clock both PWM types at the same rate and compare their performances. For PWMs of more than 8 bits, the spread PWM (purple trace) with a first order analog filter does indeed settle faster than its clustered competitor (red trace) with a third order filter. The situation is reversed for PWMs of less than 8 bits. A simple explanation for this behavior is that below 8 bits, the clustered filter’s time constants turn out to be less than those of the spread, and the situation reverses above 8 bits. However, it’s worth noting that matched clocking is not possible in a microcontroller.

In a microcontroller, until a change in duty cycle is required, an initialized, clustered PWM can run indefinitely without further processor intervention. It can also benefit from the fastest clock available to the controller. Not so with the spread PWM; it requires code to be executed every PWM clock cycle period. I have assumed 6 machine cycles to execute this spread code within an infinite loop (blue trace). As such, only 16 bit and lengthier PWMs will favor the spread option.

Of course, if you need the processor to do more than just run a spread PWM, these additional functions will increase the effective spread clock period well beyond a mere 6 machine cycles. Obviously, this increases the settling time of the associated filter. And by the way, any non-PWM code had better take a constant number of clock cycles to execute, or the spread PWM output will jitter and its accuracy suffer. The less-than-pristine “cherry on top” is that processor interrupts while supporting a spread PWM are problematic.

PWM bits	Sequence length	Spread R·C/T: filter time constant / clock period	Spread settling time TS (ms), 1/6 MHz clock	Spread settling time TS (ms), 1 MHz clock	Clustered filter	Clustered settling time TS (ms), 1 MHz  clock
1	2	9.102E-01	6.00E-03	1.00E-03	See Reference 2 which points to a spreadsheet for filter design	7.92E-04
2	4	3.228E+00	3.00E-02	5.00E-03		3.32E-03
3	8	7.810E+00	1.08E-01	1.80E-02		1.01E-02
4	16	1.696E+01	3.12E-01	5.20E-02		2.93E-02
5	32	3.527E+01	8.04E-01	1.34E-01		8.32E-02
6	64	7.187E+01	1.97E+00	3.29E-01		2.34E-01
7	128	1.451E+02	4.67E+00	7.78E-01		6.53E-01
8	256	2.915E+02	1.08E+01	1.80E+00		1.81E+00
9	512	5.843E+02	2.24E+01	3.74E+00		4.98E+00
10	1024	1.170E+03	5.05E+01	8.42E+00		1.36E+01
11	2048	2.341E+03	1.12E+02	1.87E+01		3.71E+01
12	4096	4.684E+03	2.48E+02	4.13E+01		1.00E+02
13	8192	9.369E+03	5.42E+02	9.03E+01		2.71E+02
14	16384	1.874E+04	1.11E+03	1.85E+02		7.28E+02
15	32768	3.748E+04	2.40E+03	4.00E+02		1.95E+03
16	65536	7.496E+04	5.17E+03	8.61E+02		5.21E+03
17	131072	1.499E+05	1.11E+04	1.84E+03		1.39E+04
18	262144	2.999E+05	2.36E+04	3.94E+03		3.68E+04
19	524288	5.997E+05	4.81E+04	8.01E+03		9.75E+04
20	1048576	1.199E+06	1.02E+05	1.70E+04		2.58E+05
21	2097152	2.399E+06	2.16E+05	3.59E+04		6.80E+05
22	4194304	4.798E+06	4.55E+05	7.58E+04		1.79E+06
23	8388608	9.596E+06	9.57E+05	1.59E+05		4.71E+06
24	16777216	1.919E+07	1.94E+06	3.23E+05		1.24E+07

Table 1 This table details spread and clustered settling times and filter characteristics. Multiply the R·C / T term by the desired spread PWM clock period T to obtain the product of the resistance and capacitance of the first order analog filter (see Figure 4).

To avoid large settling times, recall the option of operating a most significant and a least significant 8-bit PWM simultaneously and adding their outputs as seen in Reference 2. A filter with a 16-bit settling time can be swapped for one with a much shorter 8-bit settling time. Should you want even more resolution, use this concept to add a third PWM.

All this being said, read on for some important sequence characteristics and how best to implement k-bit spread PWMs where k = 1, 2, 3… 24.

Clustered-bit PWM sequences

Clustered-bit PWMs’ NO ones and NZ zeroes each appear in contiguous streams. An example of a waveform for such can be seen in Figure 2. Most microcontrollers can implement these with no software overhead. Just “set ‘em and forget ‘em”: specifically, program the count (NO – 1) after which a one-to-zero output transition is to be produced, and the count (N – 1) after which the counter returns to 0 and the output to a one. The PWM goes on its merry way with no further intervention necessary from executable code unless a change in the value of the duty cycle DC is required.

8 and 16-bit counters are typically available, and so DC values of A / B can be had for any integers such that 0 ≤ A ≤ B ≤ either 28 or 216, respectively. Typically, these counters can be clocked from the same high frequency clock source used to execute the microprocessor instruction set. This is useful because in general, the higher the frequency, the shorter the settling time of the filter needed to suppress the ripple.

Figure 2 This plot is of a clustered-bit PWM where NO = 16, N = 256, and T = 1uS.

Spread-bit PWM sequences

Another type of PWM produces the same number of ones and zeroes in a cycle, but spreads these binary values as evenly as possible. An example can be seen in Figure 3.

Figure 3 With this spread-bit PWM, NO = 16, N = 256, and T = 1uS.

Notice that lowest frequency of the spread PWM is far higher (16 times) than that of the clustered one. Accordingly, a faster-settling filter can be used to suppress the ripple. So what rule governs the positions of the ones and zeroes in the spread sequence? A very simple one.

Consider a parameter X which can take on the values 0, 1, 2… or N – 1. Y is periodically updated to the value of (Y + X) modulo N. If an update reduces Y, the PWM output is one; otherwise, it’s zero. The DC is X / N. This process has at least two important properties:

1. The period of the PWM sequence is N. This can be shown by considering a parameter W upon which the process W = W + X is repeatedly performed (no modulus is involved in the W update.) If the initial values of Y and W were both C, then Y = (Y + X) modulo N and (W + X) modulo N would be equal after each process step. N steps later, W would be C + N X. For any X, (C + N · X) modulo N is C. Since the moduli of W and Y are always equal, C is also the value of Y after N process steps. And so for any X, the PWM sequence is periodic in N.
2. To gain insight as to how spreading works, consider when X is 0. Y would never be reduced, and so there would never be a PWM output of one. If X were 1, the PWM would produce a one only once every N steps. If X were increased, there would be ones approximately (if not exactly) every N/X steps. As X approached N/2, the proportion of ones in the output would increase, but as long as X ≤ N/2, ones would never appear in succession. For X ≥ N/2, there would never be any zeroes in succession. And as X approached N, a reversed version of the aforementioned progression of ones would apply to the zeroes.

How might this process be executed on a basic 8-bit microcontroller? The simplest implementation would be to set N to 28 and periodically hijack a portion of the processor’s executable bandwidth to run the process. The following code implements a spread 8-bit PWM of duty cycle X / 28, where the value of X is in register r17 and that of Y is in register r16:

ADD r16, r17 ; r17 holds the value of NO which can be anywhere from 0 to 28-1. ; r16 is a simple accumulator which overflows periodically. ROL r20 ; The carry bit ( 0 or 1) from the prior addition goes to bit 0 of r20. OUT PORTB, r20 ; Bit 0 of the PORTB GPIO register takes on the carry bit value.

Of course, you can include a few more instructions so that the other PORTB bits are unaffected. It’s important to note that this code must be executed regularly. Aperiodic, “jittery” execution will impact the accuracy of the filtered value of the output stream. This means that all non-PWM code must always take the same amount of time to execute, making interrupts on the processor problematic.

Want a PWM with more resolution? Place the following instruction after the existing ADD:

ADC r18, r19 ; r19 is the MSbyte of the input X and r17, the LSbyte.

This additional instruction enables a 16-bit duty cycle of X / 216. It’s obvious how to further increase resolution by additional factors of 28 to obtain 224, etc.

The inputs of spread PWMs can range from X = 0, 1, 2… to N-1. But if N is limited to integral powers of 28, there’s a very big jump (a factor of 28) of sequence lengths between these options. That means a proportional jump in filter cutoff frequencies and, more importantly, in settling times. Fortunately, a finer range of selections is readily available. Simply limit the allowable values of X to those for which X / 2k is an integer, where k = 1, 2… log2(N)-1. The result is a (log2(N) – k) bit DAC.

The settling times of filters meeting the ripple suppression requirement are now available in increments of a factor of 2. Of course, a spread-bit DAC can have any integer value for N. But values other than 2k require additional code which must explicitly compare Y to N to generate a carry, and then conditionally update Y by subtracting N from it. Also, the spacing between successive values of X could vary unless all N possible input values were used. Perhaps a better approach would be to operate multiple PWMs simultaneously, whose outputs are weighted differently by a factor of 28. The relatively quick settling time of an 8-bit filter would be a benefit.

Analog filters

For PWM filter designs, it’s necessary to determine the input-dependent output sequence whose ripple which is the most challenging for a filter to adequately suppress. As discussed in Reference 3, the worst case for a clustered PWM is a 50% DC. To achieve reasonable settling times (TS) to within an error VTS of 1/N while meeting the Vrip requirements of .5/N, a third order lowpass filter is employed. The structure of such a filter is seen in Figure 4. The referenced Design Idea offers a downloadable spreadsheet which designs filters to users’ specifications of PWM cycle frequency and of peak-peak ripple as a fraction of full-scale output.  It was used to populate the settling time entries in Table 1 for the clustered PWM.

For the spread PWM, the worst case was determined by running simulations of all 256 output sequences of an 8-bit spread PWM applied to a first order filter (see Figure 4 again.) But what first order filter? To answer this question, I started by assuming (perhaps counterintuitively) that the worst case for ripple suppression occurs for 1 one, that is, when PWM input X = 1. (Since zeroes and ones are fully symmetric, this is equivalent to the case of 1 zero, or X = 255.) What will the ripple troughs and peaks look like for each input value at the output of a filter with a time constant selected to provide the necessary ripple suppression for X =1 only?

Figure 4 With these first and third order low-pass analog filter structures, the filters are buffered with op amps because their inputs employ resistors of high values. This is done to limit the errors imposed by the unequal resistances of the logic high and low outputs of ICs such as the 74AC04 which drive the filter inputs (Reference 4).

First we have to find that time constant. We start by writing equations for ripple starting at time t = 0. Here, R and C are the first-order filter components, and NO + NZ = N as before. The filter output is:

1. V0 (immediately before a zero-to-one transition)
2. V1 = V0·e-NO·T/(R·C) + (1 – e-NO·T/(R·C)) (immediately before the next one-to-zero transition)
3. V2 = V1·e-NZ·T/(R·C) (immediately before the next zero-to-one transition)

in the steady state, after the filter settles from a change in duty cycle, V2 = V0. Solving:

4. V₁ss = (1 − e-NO·T/(R·C)) / (1 − e-N·T/(R·C)) + 1/N (ripple peak)
5. V₀ss = 1/N – (e-NZ·T/(R·C) − e-N·T/(R·C)) / (1 − e-N·T/(R·C)) (ripple trough)
6. Vrip = V1ss – V0ss = (1 – e-NO·T/(R·C)) · (1 – e-NZ·T/(R·C) ) / (1 – e-N·T/(R·C) ) (peak – trough)

Setting V₁ss in #4 above to .5/N for N = 28 and solving numerically, a value of 291.5 is obtained for the unit-less term R·C / T. Setting V0SS in #5 to .5/N with R·C / T = 291.5 yields a smaller error than .5/N for the trough; the peak error is the larger of the two (tabulations of this term for a range of N values were calculated from #4 and appear in Table 1). In a simulation, T was set to 1uS, R to 1MegΩ and C to 291.5pF. Output sequences resulting from inputs from 1, 2… 255 were applied to an 8-bit spread PWM.

Figure 5 shows a graph verses the input X values of the maximum ripple deviations from DC and of half the peak-to-trough differences. It’s clear that the biggest error is associated with inputs both of 1 one and of 255 ones (1 zero). This filter time constant 291.5uS does indeed limit the deviation from the duty cycle of 1/N (1/256) to .5/N times the PWM’s full-scale output, one half of the PWM resolution, and an input of X = 1 does yield the worst-case ripple. For any clock period T, simply multiply the Table 1 unit-less parameter R·C / T by T to obtain the filter’s R-C time constant.

Figure 5 This graph shows the filter output deviations from DC in the steady state vs. input values of 1, 2… 255 for an 8-bit spread PWM. A 100mS wait was employed before measurements to ensure settling, more than 300 times the 291.5uS filter time constant.

It might be surprising that the worst ripple peaks are associated with a single one or zero in the output sequence. But a little thought reveals that a single pulse is the case where the lowest frequency f1 = 1/(N·T) Hz that the PWM can produce has the largest amplitude. Note that input values which are powers of 2 have the lowest maximum errors. This is in part because they have no energy at f1 Hz. I have spot-checked sequences of N-4096 and those for N < 256 and found an input of X = 1 to consistently produce the maximally deviant ripple.

Settling times of the spread PWM filter

Tired of the math by now? You ain’t seen nothin’ yet!

Because an analog filter is being driven by a digital sequence, difference equations can be used to calculate the filter output. The worst case for setting time is when the filter output at time t = 0 is DC = 1 (NO = 256) and the input transitions to NO = 1. Then:

7. y[k]      =          a*y[k-1] + (1-a)*x[k],              y[0] = 1,           a = e-T/(R·C),       k = 0, 1, 2…

where x[k] = 1 when k modulo N = 0, and 0 otherwise.

Ripple peaks occur when x[k] = 1 and troughs when k modulo N = N – 1 =255 (immediately before a peak.) We have:

8. Yp[k·N]             =          ak·N + (1 – a)*(1 – a(k+1)·N) / (1 – aN),                   ripple peaks
9. Yt[k·N – 1]        =          ak·N -1 + (1 – a)*(aN-1 – a(k+1)·N-1) / (1 – aN),          ripple troughs
10. yp_SS                 =          (1 – a) / (1 – aN)                                                steady state ripple peak
11. ypp                             =          (1 − a)(1 − aN−1) / (1 − aN)                                steady state p-p ripple
12. k1st_peak = N * Ceiling [ Log { ( (2/N) · (1 – b) + a – 1) / (1 + (a – 2)·b) } / Log(b) ],       b = aN

where k1st_peak is the smallest value of k for which all ripple peaks are less than 2/N.

It’s worth taking a look at what is going on for the worst-case ripple when N = 256. See Figure 6.

Figure 6 This graph represents data for a spread PWM with N = 256 and filter outputs starting at one (1 volt.) At time t = 0, the red trace reflects a change of input to X = 1 and the blue, an input change to X = 0. X = 1 takes longer to settle because it spends 1/N of its time with an input of one, whereas X = 0 spends all of its time with an input of zero.

From #12, k1st_peak is the smallest value of k for which ripple peaks y[k·N] are less than or equal to 2/N. In this case, that corresponds to k = 8·N at 2.048mS ( y[7·N] is slightly larger than 2/N.) Finally, #7 is used to iterate all integer values of k from 7·N to 8·N find the smallest value of k = kS (that is, the first time) for which y[k] and all subsequent values of y[k] are less than 2/N. The settling time is then T·kS. This procedure is used to populate in Table 1 the spread PWM settling times at various cycle lengths N for a 1MHz clock.

In conclusion…

PWMs can be implemented by microcontrollers. For a clustered-bit PWM, no further intervention is required by the controller beyond the cycle length of a programmable counter and the latest value of DC. Typically, the counter can be advanced by the highest speed clock available to the controller. But for a spread-bit PWM, a supportive block of code consisting of multiple instructions must be executed periodically This must be done at consistently timed intervals if accuracy is to be maintained.

To allow the processor to perform other functions, these intervals, the effective period of the spread clock, can be quite long in comparison to those of the clustered-bit PWM. Longer clock periods lengthen the settling time of the filter needed to suppress a PWM’s ripple. Granted, the spread sequence has generally much less lower frequency energy than a comparably clocked clustered sequence and therefore can employ a faster settling time filter for ripple suppression. But in practice, microcontrollers cannot clock code-driven spread PWMs at the rates of clustered ones, which have inherent hardware support. Comparable resolution spread PWM filters generally take longer to settle than those of their clustered cousins when microcontrollers implement these PWMs.

It’s intriguing to consider that the spread PWM discussed herein can be considered to be a first order delta-sigma modulator (Reference 5). The overflow of the registers can be thought of as an accumulator which, when instead of overflowing, adds a value of -N to its input X. Modulators of order higher than the first can shift even more low frequency energy to higher frequencies, relaxing ripple-suppression requirements even more and reducing settling time. Most commercial implementations of such techniques replace analog filters with digital versions thereof which then drive conventional multi-bit DACs, all implemented on a single IC.

If our PWM types were to be implemented in hardware such as an FPGA, their clock rates could be identical. As per Table 1, at identical clock rates, some sequence lengths N would favor the spread PWM with a simple single R-C pair (first order) filter, and others which would favor the clustered PWM with its three-pair (third order) R-C filter. However, the spread PWM would also benefit by replacing its first order filter with a third order one, something I plan to discuss in a forthcoming Design Idea.

PWMs: the gift that keeps on giving!

References:

1. Custom design PWM filters easily
2. Ibid, Figure 3.
3. Ibid
4. Ibid, see the SN74AC04-induced errors section.
5. https://www.ti.com/lit/an/slyt423a/slyt423a.pdf

Christopher Paul has worked in various engineering positions in the communications industry for over 40 years.

Related Content

• A nice, simple, and reasonably accurate PWM-driven 16-bit DAC
• Parsing PWM (DAC) performance: Part 1—Mitigating errors
• Parsing PWM (DAC) performance: Part 2—Rail-to-rail outputs
• Parsing PWM (DAC) performance: Part 3—PWM analog filters
• Parsing PWM (DAC) performance: Part 4 – Groups of inhomogeneous duty cycles

The post Implementing a DAC: The battle of the PWMs appeared first on EDN.

Nuvoton Technology Corporation announces the launch of the NSC128L42, a new 32-bit Arm Cortex-M23 microcontroller for high-precision measurement. This highly integrated solution combines a 24-bit Sigma-Delta ADC, an LCD driver, and high-quality voice synthesis in a single package. With an operating speed of up to 49.152 MHz and support for a wide voltage range (2.0V to 5.5V), it is perfectly suited for a variety of portable and industrial applications.

Superior Computing Performance and Development Flexibility

The microcontroller features 320 KB of embedded Flash memory, along with an additional 6 KB that can be configured as a bootloader for In-System Programming (ISP). With 18 KB of SRAM, it provides ample memory for real-time data processing and embedded control tasks. The In-Circuit Programming (ICP) capabilities allow developers to update voice content efficiently, even after the device has been deployed in the field.

Powerful Analog Integration: Designed for Precision Measurement

A standout feature of NSC128L42 is its comprehensive analog capability, making it ideal for high-precision sensing applications. The device integrates a 24-bit Sigma-Delta ADC for ultra-high-resolution signal acquisition, complemented by a 12-bit SAR ADC for faster general-purpose conversions. Additional analog components, including a low-noise amplifier and an operational amplifier, enhance signal integrity and reduce the need for external circuitry. These features make NSC128L42 particularly suitable for applications such as blood pressure monitors, precision scales, and various measurement devices.

Rich Peripheral Connectivity and Smart Audio Support

In addition to its analog strengths, NSC128L42 provides a rich set of digital peripherals, including multiple UART interfaces, SPI and SPIM communication modules, and a six-channel Peripheral Direct Memory Access (PDMA) controller for efficient data handling. It also incorporates three 16-bit timers and PWM outputs to support a wide range of control applications. An integrated LCD driver supports various COM/SEG configurations, enabling direct connection to segment displays and reducing overall system cost.

For applications requiring audio functionality, the device includes a Class-D speaker driver capable of delivering up to 0.35W output at 3.6V, allowing for voice manual, audio alerts or voice assistance to increase the user’s experience.

Low Power Design and Industrial-Grade Reliability

Power efficiency remains a key focus in the NSC128L42 design. The microcontroller supports multiple low-power modes, including a Deep Power Down mode that consumes less than 1 µA. An internal low-speed RC oscillator enables periodic wake-up, allowing the system to monitor events while maintaining ultra-low energy consumption. Reliability is further enhanced through features such as a built-in Brown-Out Detector and an operating temperature range of -40°C to 85°C. With its combination of precision analog integration, flexible connectivity, and low-power operation, NSC128L42 provides an ideal platform for developers targeting smart measurement, medical, and industrial applications.

The post Nuvoton Unveils New Cortex-M23 Microcontroller SOC, NSC128L42, for High-Precision Measurement Applications appeared first on ELE Times.

Infineon Technologies AG of Munich, Germany has introduced the EiceDRIVER 2EDL90xG3, a 120V common footprint gate driver designed to enable silicon (Si) and gallium nitride (GaN) power designs on the same PCB...

At the 30th International Semiconductor Laser Conference (ISLC 2026) in Tampere, Finland (14-17 June), photonic simulation CAD software developer Photon Design Ltd of Oxford, UK showcased its industry-first, simulation tools for quantum dot lasers and photonic crystal surface-emitting lasers (PCSELs)...

Based on preliminary, unaudited accounting data as of end-May, NUBURU Inc of Centennial, CO, USA (a dual-use defense & security integrated platform company focused on non-kinetic effects and directed-energy technologies, electronic warfare and defense mobility programs, software-orchestrated defense systems and advanced manufacturing) expects its stockholders' equity to materially exceed the $4m requirement applicable under the NYSE American continued-listing rules for companies with a history of losses...

Енергія інновацій Дениса Дерев'янка Інформація КП вт, 06/30/2026 - 12:00

Floating-point computations dominate the landscape of all AI/ML compute but also in automotive, avionics and healthcare. While performance and compute errors dominated the landscape of floating-point design and verification, power optimizations forced designers to use non-standard precisions such as FP4, FP8, BF16, and so on. So, mixed precision computation has become prominent in modern-day design.

Figure 1 Here isa a sneak peek at floating point compute in AI designs. Source: Axiomise

However, a new paradigm of transprecision compute is also emerging. Tagliavini et.al captured this beautifully in their paper coining the term transprecision floating-point computing. According to the paper, transprecision computing is an area where “rather than tolerating errors implied by imprecise HW or SW computations, systems are explicitly designed to deliver just the required precision for intermediate computations”.

Mixed precision vs transprecision

Mixed precision and transprecision are closely related, but they are not the same thing. Mixed precision is mainly an algorithmic/use pattern; transprecision is a broader system and architecture paradigm. Mixed precision means using two or more fixed numeric formats within one algorithm or kernel. Transprecision goes further: it’s about designing the hardware, software, and algorithms so that the precision itself is a tunable resource.

In short, mixed precision is combining a few existing formats in one computation for performance/energy, with accuracy recovered by algorithmic tricks. And transprecision is an end-to-end paradigm where precision is a first-class, tunable knob, and the system supports many possible precisions (not just, for example, 16-bit/32-bit) to meet accuracy/energy goals.

The benefits are clear. Exploit lower precision where it’s safe, allowing better balance of performance and throughput, and lower energy consumption, thereby cooler chips, but maintain full-precision (higher) accuracy where needed. Specifically, formats such as FP16 and BF16 allow hardware to execute more FLOPs per cycle, often giving 1.5-3X speedups in deep learning workloads. Transprecision architectures can achieve multi‑x speedups by vectorizing and simplifying datapaths for small formats (for instance, 8-bit or 16‑bit “minifloats”).

Verification challenges

Mixed-precision and transprecision computing introduce substantial verification challenges because correctness is no longer tied to a single, well-understood format, but to a tapestry of interacting precisions, formats, and rounding behaviors across the pipeline. Mixed-precision and transprecision computing create a significantly harder verification problem than conventional floating-point design because correctness must be established not only within each individual format, but also across the boundaries between them.

In these systems, values may be computed, accumulated, converted, rounded, and stored at different precisions, so verification must account for interactions between multiple exponent ranges, mantissa widths, rounding modes, exception rules, and format-conversion paths rather than checking a single uniform arithmetic model. This increases the risk of subtle failures such as incorrect narrowing or widening behavior, loss of precision at format boundaries, inconsistent NaN and infinity propagation, mismatched exception flags, non-equivalent fused and non-fused results, and corner-case errors involving subnormals, saturation, or directed rounding.

The challenge is amplified further in configurable or transprecision FPUs, where the same hardware datapath may serve several formats and custom numerical types, making it easy for implementation shortcuts or shared logic to satisfy one format while violating the architectural intent of another.

As a result, effective verification of mixed-precision and transprecision designs requires more than numerical result checking: it demands format-aware reference models, carefully targeted boundary-case stimulus, cross-format property checking, and systematic validation of rounding and exception behavior under every supported precision configuration. The challenges of microarchitectural implementation are too many to capture here so we will defer to these for a separate blog, but pipelined implementations offer an interesting cross-dimensional challenge for verification.

Traditional verification methods

Simulation-based verification, whether directed or constrained-random, is inherently inadequate for mixed-precision and transprecision floating-point designs because it can exercise only a vanishingly small fraction of the enormous input and state space. Moreover, it’s biased toward scenarios that verification engineers think to test.

Even with sophisticated UVM environments and large regression farms, most tests focus on typical operating ranges and a limited set of corner cases, leaving huge gaps around precisely those conditions where multiple formats interact: operands that sit exactly on format boundaries, rare combinations of subnormals with different exponents, intricate sequences of narrowing and widening conversions, or subtle interactions between fused operations, rounding modes, and exception flags.

Many of the most damaging floating-point bugs historically have come from such corner cases that were numerically benign for most inputs but catastrophically wrong for particular patterns that simulation never hit. In a design that supports several precisions and custom formats, the number of distinct cross-format behaviors quickly explodes, making it practically impossible to gain real confidence from coverage metrics alone. That’s because hitting each branch or bin does not guarantee that all critical numerical combinations and flag behaviors have been validated.

Formal methods-based solutions

Formal verification, in contrast, can reason symbolically about entire classes of inputs and states at once, proving that key arithmetic, rounding, and exception properties hold for all operand values and all supported format combinations within a given block, and thus is uniquely positioned to close the coverage gap that simulation-based methods cannot realistically bridge. However, while C-to-RTL equivalence checking has been in use for many years to establish formal equivalence through proofs, deploying formal methods on direct pipelined implementations of RTL is not easy with C-to-RTL based tools.

What we need is a homogeneous architecture whereby we can reason about correctness of RTL micro-architectural implementation directly using a golden reference implementation in SVA, exploiting the abstraction-based techniques in property checking. This is why we built floatrix.

It’s an app offered as part of the axiomiser platform that can be automatically configured at runtime through a GUI to verify a range of FP precision formats through proofs obtained by exercising custom SVA properties on actual designs implemented in Verilog or VHDL requiring minimal human interaction; and most importantly requiring zero model minimization that is the norm in any C-to-RTL based formal equivalence checking solutions.

SVA models used in floatrix have been goldenized against the Berkeley Hardfloat models for IEEE-754 compliance. For non-standard precisions, we follow the reference guides of the implementation to adapt the models.

We have deployed floatrix on several designs since its launch in September 2025. We continue to find interesting bugs. Recently, we identified a tinniness issue on the FPU used by the OPENHW group. The Github ticket has more details.

In this article, we describe an interesting bug we caught in floating-point dividers found in the fpnew design (again part of the OPENHW group), using our floatrix app. In the next section we describe the bug itself and then we elaborate on its significance, and whether bugs like these are likely to happen in other designs. Our analysis covers the broader scope of what happens with designs in mixed-precision format, and gaps in verification causing these bugs to be missed in the first place.

Details of the bug

Before we describe the bug, let us capture some of the basic definitions.

Inexact flag: Raised when the rounded floating-point result is not equal to the mathematically exact result, meaning some precision was lost in rounding (this can accompany normal, overflowed, or underflowed results).

Underflow flag: Raised when a non-zero mathematical result is so small in magnitude that, after rounding to the target format, it becomes tiny (typically subnormal or zero); under IEEE‑754’s default rules, this is signalled only when that tiny result is also inexact.

Scenario

The inexact and underflow flags should be set if the unbound exact result (out of format) is 1×2-140 and the bounded result should be 16’h0000. Moreover, in the case of rounding up, the expected result should be 16’h0001. However, in FPnew, the result is always 16’h0000 with no exception flags raised.

Root cause

Root cause might be from performing the operations using single-precision arithmetic and then converting back to BF16.

Detection methods

The bug was caught using the floatrix underflow flag checks.

Figure 2 Waveform shows the special underflow case in division. Source: Axiomise

Why this class of bug is realistic?

Bugs like this can happen in real designs, especially in floating-point units that mix internal higher-precision arithmetic with lower-precision output formats such as BF16.

A bug like this reflects a common implementation pattern where the datapath computes in a wider internal format, such as FP32, and then converts or packs the result into a narrower format. If exception logic is tied only to the internal format and not to the final target format, the design can silently produce a numerically plausible output while missing required flags.

This is especially plausible in trans-precision designs. BF16 has the exponent range of FP32 but much less precision, which makes conversion-stage edge cases more common. A value can be representable or exact internally yet still underflow or become inexact when rounded to BF16. If the final conversion step is treated as a formatting step instead of a full IEEE-aware operation, underflow and inexact can be lost.

Reuse of a FP32 datapath for BF16

Modern fpu designs may implement a single “main” datapath (often FP32) and derive lower-precision results (BF16) by:

1. Computing in FP32
2. Rounding/packing down to the architectural format

For this bug, it means:

1. The internal FP32 computation is perfectly normal and may produce a small, exact, subnormal value.
2. Because that internal value is exact, the FP32 underflow and inexact logic quite reasonably decides “no underflow, no inexact”.
3. If the design then blindly packs to BF16, the BF16 representation of that exact value can be 0x0000 or 0x0001, which is architecturally tiny and inexact from the BF16 point of view, but no new flags are generated.

So, the specific condition “exact subnormal in FP32, non-representable in BF16” is not rare; it’s exactly what you get whenever BF16 sees the far tail of the FP32 subnormal range.

Flag logic attached to the wrong format

In a typical implementation:

• The main datapath correctly implements all rounding modes in FP32.
• The BF16 path is implemented as a simple truncation, or as a hard-coded “round-to-nearest-even” micro-operation, ignoring the global rounding-mode control.

For this bug, that architectural decision has a precise consequence:

• Underflow and inexact are defined with respect to the architectural result format and rounding (here BF16, with “tininess after rounding” for RISC‑V BF16).
• If flags are tied to the internal FP32 representation, any case where FP32 is fine but BF16 underflows will be mis‑flagged.

The bug is therefore a very plausible pattern and can occur in other kinds of FP implementations because it reduces duplication of flag logic but is architecturally wrong for BF16 arithmetic.

RISC‑V BF16 underflow definition vs implementation shortcut

RISC‑V BF16 explicitly says:

• Tininess is detected after rounding.
• Underflow is signalled only when the result is both tiny and inexact.
• The tininess detection itself conceptually uses rounding as if the exponent were unbounded in the target format.

A shortcut implementation for BF16 in a FP32-based unit often does:

“Let the FP32 unit compute and round; then chop its bits down to BF16.”

For this bug, perhaps that shortcut misses exactly this:

• “Tiny and inexact” must be interpreted in BF16, not in FP32.
• A result can be “non-tiny and exact” in FP32, yet “tiny and inexact” in BF16.

So, the focused risk factor is not generic underflow subtlety; it is the temptation to reuse the FP32 tininess logic instead of implementing BF16-aware tininess-after-rounding. That shortcut directly creates the buggy behavior.

Directed rounding applied only at the FP32 level

This case also involves a mode where “round to max” (or analogous directed rounding) should drive the BF16 result from 0x0000 to 0x0001. We suspect, this leads to:

• FP32 sees the tiny result as exact, so the rounding mode does nothing interesting at that level.
• BF16 should use the rounding mode to decide between 0x0000 and 0x0001, but the conversion block ignores it.
• Consequently, the result is always 0x0000, and the flags never see the inexact/tiny condition.

So, the specific vulnerability of rounding-mode control is not propagated into the BF16 block, yet the ISA treats the BF16 operation as architecturally rounded in that mode.

Verification gaps specific to this pattern

For bugs like these to escape into silicon, we imagine that two very concrete verification gaps typically exist:

• Format-mismatch in checkers: The reference model or scoreboard checks only the numeric value in FP32, or it narrows in the same way as the RTL (for example, using a float32‑>BF16 helper that also ignores flags), so it cannot see that BF16 flags differ from the spec.
• Lack of subnormal+narrowing directed tests: Random and ISA-level tests hit plenty of BF16 arithmetic, but almost nothing in the region where:

1. The true value is representable as a tiny FP32 subnormal.
2. That value is below the BF16 subnormal range.
3. The rounding mode is a directed one that should change 0x0000 to 0x0001.

These are not generic underflow issues; they are exactly the missing cases needed to expose flags generated in a wider format, and then silently narrowed.

Other similar bug patterns

This bug fits into a broader family of real floating-point design bugs:

1. Flag-silent narrowing conversions: FP32 to BF16 or FP32 to FP16 loses information, but the design fails to raise inexact or underflow.
2. Wrong rounding-mode application: The internal result is correct, but the final conversion stage ignores directed rounding such as round-toward-positive or round-to-max.
3. Fused/non-fused mismatch: FMADD produces different flags than a mathematically equivalent MUL followed by ADD because the implementation handles flags at the wrong stage.
4. Flush-to-zero leakage: A supposedly IEEE-compliant path accidentally behaves like flush-to-zero in one stage, especially for subnormal intermediates.
5. Tininess detection mismatch: The design effectively uses one tininess rule internally and another assumption in verification or architectural expectations.

These are all realistic in designs that support multiple formats, configurability, or internal reuse of a higher precision datapath.

Practical impact

The practical impact of these kinds of bugs can be profound, even if the affected values are tiny. In many applications, the numerical difference may seem small, but the bug still matters because:

1. Exception flags may drive diagnostics, fallback logic, or compliance tests.
2. Image, DSP, and ML pipelines can be sensitive to repeated bias near zero.
3. Safety or standards-driven environments care about architectural correctness, not just approximate numeric usefulness.

Why formal models for floating-point designs

Mixed-precision and transprecision floating-point designs offer compelling benefits in performance, power, and area, but they also amplify the risk of subtle correctness issues that are extremely hard to detect with traditional simulation-based verification alone.

The bug analyzed in this article illustrates how easy it is for architectural intent to be violated when arithmetic is performed in a wider internal format, flags are generated with respect to that format, and the final narrowing step is treated as a “mere” formatting operation rather than a first-class floating-point transformation with its own rounding and exception semantics.

This pattern is not unique to a single core or vendor; it’s a natural by-product of reusing FP32 datapaths to implement BF16, separating execution, rounding, conversion, and flag generation, and relying on checkers that mirror the same implementation shortcuts. More generally, the same structural causes can lead to a family of related failures: flag-silent narrowing conversions, incorrect application of directed rounding modes, inconsistencies between fused and non-fused operations, flush-to-zero leakage in ostensibly IEEE-compliant paths, and mismatched tininess rules between specification, design, and verification.

Addressing these challenges requires a shift from “best-effort” simulation to exhaustive, property-driven reasoning. By using format-aware formal models, such as those provided by floatrix, it becomes possible to prove that rounding, underflow, overflow, and flag behaviour are correct for all operands and all supported precisions, and to expose bugs that would otherwise hide indefinitely in rarely exercised corners of the state space.

Nicky Khodadad is senior solutions engineer at Axiomise.

Nguyen Vu is formal verification engineer at Axiomise.

Ashish Darbari is Founder and CEO of Axiomise.

Related Content

• Hardware-based floating-point design flow
• Implementing floating-point DSP on FPGAs
• Floating-Point Data in Embedded Software
• How to create fixed- and floating-point IIR filters for FPGAs
• Understanding Peak Floating-Point Performance Calculations

The post Hidden underflow in BF16 divider in mixed-precision FP designs appeared first on EDN.

Graphene-based electronic device design, development and manufacturing company Paragraf of Somersham, Cambridgeshire, UK is forming a new Advisory Committee that will include Oreste Donzella, Jean-Michel Richard and Thomas Piliszczuk. Donzella and Richard will also join Paragraf’s board as non-executive directors...

Ascent Solar Technologies Inc of Thornton, CO, USA – which designs and makes lightweight, flexible copper indium gallium diselenide (CIGS) thin-film photovoltaic (PV) panels that can be integrated into consumer products, off-grid applications and aerospace applications – has announced the results of its preliminary atomic oxygen (AO) exposure testing for its space-grade thin-film PV products. Testing has shown significant resilience to atomic oxygen in low Earth orbit (LEO)...

Конференція до 100-річчя професора В.М. Чермалиха "Сучасні технології автоматизації в електротехніці та електромеханіці" Інформація КП пн, 06/29/2026 - 17:30

Need just one more network port than you’ve currently got available (often: none)? A splitter can do the trick; just spend a few extra bucks to make sure you’ve made the right pick.

I’ll begin this teardown with an analogy. Imagine you’re grilling weekend hamburgers for the family. After the patties are cooked (medium-rare, of course), you slot them in buns and load them up with per-recipient preferred extras—lettuce, pickles, tomatoes, onions, mustard, and the like. The one condiment everyone wants is catsup (of course, again). But then you belatedly realize that there’s not enough of the tomato-derived sauce left in the bottle for everyone; specifically, one of the kids is about to be catsup-deprived.

Obviously, this just won’t do. But if you run to the store for more, the food will be cold by the time you get back. Plus, everyone’s already starving. And none of the neighbors, specifically those that you know well enough to even think of knocking on their doors and asking to borrow some of their catsup, are home. But then you remember the spare catsup packets from a recent take-out meal, jammed in the back of the refrigerator. An imminent condiment crisis is averted!

Or take this one. Your four-cylinder car is already paid off, in solid cosmetic condition and (mostly) equally great functional shape. But it just doesn’t have the “get up and go” that you’re now looking for. You could finance a more powerful replacement. But assuming you could even find someone to sell your existing vehicle to, or a dealer willing to take it in trade, you won’t get what you think it’s worth. And did I already mention that the one you already have is debt-free?

But then you realize you’ve only been putting regular (vs premium-octane) gas in it all this time. And/or that it’s been a while since you’ve taken it to the shop for a spark plug swap and broader tune-up. And/or maybe just that its tires are underinflated, or your trunk is overfilled. Rectifying these shortcomings transforms your existing vehicle, making it sufficiently spunky such that you can shelve the alternative of a replacement, keeping money in your pocket in the process.

An RJ45 in every port

What’s this all got to do with technology, specifically with Ethernet splitters? Well, multi-port Ethernet switches commonly come in the following configurations:

• 5-port
• 8-port
• 16-port
• 24-port
• 48-port

(10- and 12- port models, and other variants, also exist but are less common and therefore tend to be much more expensive on a per-port basis).

What happens if, as I’ve repeatedly experienced over the years, I have an eight-port switch  already in service and fully populated, but then add another wired Ethernet device to my LAN (for example, another NAS)? This leaves me needing one more port, but I don’t have any available spares. I could:

• Replace the 8-port switch with a 16-port successor: an expensive transition proposition that also leaves me with a perfectly good but now-unused 8-port switch predecessor, or
• Add a separate 5-port switch to the mix, connected to the original 8-port switch using a short span of Ethernet cable. While this is more economical than the prior approach, it “wastes” a port on both switches, dedicated solely to the interconnect between them, plus it takes up more space on the networking equipment shelf (along with another power strip spot).

Passive deficiencies

But there’s a third option, which I’ll be analyzing today. It’s a splitter, most commonly found in 1:2 ratio variants such as today’s dissection victim, although larger configurations are also available at least in active, versus passive, splitter form. What’s the difference? Passive splitters, as their name suggests, are unpowered (I’m also assuming here that they’re not self-powered, specifically via PoE). They’re also quite inexpensive, as this $8.99-total pair of them exemplifies:

Alas, they’re not a perfect panacea. Not even close. In this particular implementation case, notice the “(Can’t Run Both at The Same TIME)” qualifier right in the product title, conceptually replicated in another stock image, although the embedded verbiage muddies the waters as least as I’m interpreting it:

What’s basically going on with this particular implementation of the concept (with thanks to a knowledgeable Amazon reviewer, whose graphics I’m “borrowing”) is that the eight Ethernet wires flowing into one end of the splitter are duplicated at both connectors on the other end:

The upside? From a performance standpoint, both split-end (see what I did there?) connectors use all eight original-end wires (hold that thought). The downside? If you plug active devices into both “split” connectors at the same time, neither of them will go online. Not to mention all the short-circuiting going on between all three devices mated to the splitter, which should instead be called a duplicator (or maybe an overly complicated and potentially tragic coupler).

In the other implementation of the concept, which as my Amazon reviewer friend points out, often looks identical from the outside, four of the eight original-end connector wires go to one split-end connector, with the other four going to the other.

There are upsides to this variant approach, potentially. No short circuits, for one thing. And depending on how the wiring is handled at the other end of the cable plugged into the splitter’s original-end connector, gear plugged into both split-end connectors may be able to coexist. But since each of them is only using four wires of the total eight-wire strand, they’re each restricted to 100 Mbps peak bandwidth, since GbE connectivity requires the use of all four two-wire sets.

Active rationalization

Powered (active) splitters are the real deal. Essentially, they’re mini-switches, with a subset of the total number of connectors found in a “true” five-port (or larger) switch. Take today’s Goalake 2:1 patient, for example, which set me back only $6.49 post-35%-off-promotion when I bought it from Amazon in December 2024.

Along with its 3:1 sibling, which I’d purchased at the same time for only $9.09.

No inter-device packet collision issues, plus full GbE bandwidth to both “split end” devices, albeit subdivided between them if they’re concurrently transmitting or receiving.

With the stock image out of the way, let’s now look at the “real thing”, starting with box shots accompanied by a 0.75″ (19.1 mm) diameter U.S. penny for size comparison purposes, as usual.

Packaging contents

Open ‘er up, and inside you’ll find a slip of paper up top:

with the rest of the goodies below:

Extras first, also including a USB-A to USB-C cable, whose purpose you’ll see shortly:

And now for our patient, initially translucent-swathed:

And now “unclothed”:

This side you’ve already seen in the “stock” image:

These two are, like the bottom, bland:

And this one explains why the aforementioned included USB cable exists:

It’s for the USB-C incoming power connection:

To my earlier “takes up more space on the networking equipment shelf (along with another power strip spot)” crack, this device in contrast is pretty tiny (58.1 mm x 23.4 mm x 62.8 mm). And although you could plug the USB-A end into a dedicated “wall wart”, the power requirements (5V@1A) are low enough that you could instead leverage an already-available and otherwise-unused USB connector coming out the back of a nearby NAS or UPS, for example.

Unsurprising (and highly integrated) innards

Time to get inside. You probably already noticed the four screws, two on each end. And you probably already guessed what comes next:

Turns out, I didn’t necessarily need to remove both ends’ plates; I could slide the PCB out either:

Oh well…nothing wrong with being thorough:

Note the lingering glue on the inside-chassis slot, to hold the PCB in place as originally installed:

Speaking of which, not much of note on this PCB side, save for more glue remnants and the fact that the manufacturer went with multiple smaller LAN transformers per-connector versus one unified per-connector alternative, as I’ve seen in other wired Ethernet-inclusive products.

The other side’s more interesting, albeit only a bit, reflective of the minimized bill-of-materials cost for this low-priced device.

That thermal pad presses up against the lower half of the (aluminum, I presume) chassis when the PCB is in place. Let’s see what’s underneath:

Surprise, surprise (not)…an Econet (later merged with Airoha Technology, both subsidiaries of MediaTek) EN8850DHE five-port switch with embedded 10/100/1000Base-T PHY!

That’s all I’ve got for you today. Reader thoughts are as-always welcome in the comments!

—Brian Dipert is the associate editor, as well as a contributing editor, at EDN.

Related Content

• Teardown: Powerline networking plus PoE
• Malfunctioning Ethernet cable comes up short
• Cutting into a conventional USB-C charger
• Modern UPSs: Their creative control schemes and power sources

The post Dissecting an active Ethernet splitter appeared first on EDN.

A breakthrough could lead to huge breakthroughs in battery performance, as per scientists. The findings, from researchers at Dundee and Warwick universities, could lead to the development of batteries for electronics and vehicles that charge faster, last longer, and are safer to use. The researchers say that for the first time they have identified the key role oxygen plays in storing and releasing a battery’s energy.

Previously thought that during the charging process, much of the activity happens in metal elements inside the battery, such as nickel, cobalt, or iron, and that oxygen in the battery was “passive”. However, the team said advanced computer modelling and laboratory experiments have shown that oxygen plays a much more active role in the charging and discharging process.

Dr Hrishit Banerjee, a theoretical physicist at Dundee’s faculty of science, engineering and business, said: “Global populations have become increasingly reliant on renewable energy technologies and advanced energy storage systems, from everything from the mobile phones in our pockets to the cars we drive. “By improving our knowledge of what is occurring at a tiny, atomic level within batteries, we can make big leaps in improving their performance in the real world.

This has made understanding the technology underpinning electronic processes inside battery materials increasingly important. This research is crucial and showcases a new understanding of how batteries function at a fundamental level. The study compared two of the main lithium-ion battery cathodes in daily use, phosphates and layered oxides.

Together, these forms of batteries are used for a host of applications, including electric vehicles and portable electronics such as mobile phones and laptops. The study found that while phosphates showed little oxygen participation, the layered oxides showed “significant” electron extraction from oxygen. Current technologies are limited by the understanding of the underlying physics of how and why batteries fail over time. This general framework will help design batteries with much longer lifetimes.

The post New Battery Breakthrough Leads to ‘Big Leaps’ in Electronic Performance appeared first on ELE Times.

КПІ — серед лідерів сталого розвитку за версією THE Sustainability Impact Ratings 2026 kpi пн, 06/29/2026 - 14:25

The global tech supply chain is undergoing a massive structural realignment, and India is positioning itself to be more than just a destination for product assembly. In a significant move to bolster the nation’s hardware and clean-tech ecosystems, Uttar Pradesh Chief Minister Yogi Adityanath officially laid the foundation stone for major manufacturing facilities, led by Amber, Ascent, and SAEL Industries Limited. Their goal is to develop a manufacturing capacity of 6 gigawatts for solar cells and 5 gigawatts for solar modules from this plant. This development marks a critical transition from local product assembly to deep-tier component manufacturing, and the production of green technology is a fundamental requirement for true technological self-reliance.

Speaking at the inauguration ceremony, Chief Minister Yogi Adityanath said that the vision is to transform India into a global hub for electronic components manufacturing. ‘The goal is to transform India into a hub for electronic components, and this very vision has brought us to where we stand today, a moment that brings joy to us all.’

Expanding the Grid: Mass-Scale Solar and Component Infrastructure

While the state is aggressively pushing toward general electronics production, a massive anchor of this new manufacturing hub is dedicated to renewable energy hardware. The newly initiated plants are targeting staggering production capacities to fuel both domestic infrastructure and global markets:

• Solar Cell Production: The facility is designed to scale up to a manufacturing capacity of 6 Gigawatts (GW) for solar cells.
• Solar Module Assembly: Alongside the cells, the plant will house a 5 Gigawatt (GW) capacity line for fully fabricated solar modules.
• Upstream Electronics: By focusing on core electronic components and advanced fabrication alongside partners like Amber and Ascent, the hub addresses critical raw hardware gaps in India’s tech supply chain.

The launch also coincided with the inauguration of the “Pandit Deendayal Upadhyaya Training Mega-Campaign,” a structured initiative designed to upskill local workers and prepare engineers to operate these highly automated facilities. As these production lines spin up, the project provides a vital sandbox for localized engineering talent, ensuring that the youth of Uttar Pradesh are positioned to lead the region’s emerging green economy.

The post India is Engineering a Domestic Tech and Clean-Energy Supply Chain appeared first on ELE Times.

Сергій Струтинський: від фундаментальної науки до практичних інновацій Інформація КП пн, 06/29/2026 - 12:06

Infineon Technologies AG of Munich, Germany has introduced a 24kW battery backup unit (BBU) DC–DC reference design for high-voltage (HV) DC bus architectures in artificial intelligence (AI) data centers. The design is said to be the first of its kind to operate directly from a battery stack to an 800V DC bus, using 650V and 1200V silicon carbide (SiC) technology. It achieves a power density of 450W/in3 and efficiency exceeding 99% within the same physical form factor as existing low-voltage (LV) BBU implementations, addressing a key infrastructure bottleneck as data centers transition to higher-voltage DC distribution...

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In the world of retail, security is not always about cameras or guards; it’s often about technology you barely notice. Electronic article surveillance (EAS) tags are a prime example: small, lightweight devices that quietly safeguard billions of dollars’ worth of merchandise every year. Their strength lies in simplicity; an elegant mix of materials science and signal engineering that creates a reliable deterrent against theft.

For engineers and technologists, EAS tags are more than just retail accessories; they are a case study in how discreet design and robust physics converge to solve a persistent, real-world problem.

Principle of operation: Resonance and detuning

EAS tags are built on the physics of resonance. In RF systems, tag’s circuit is tuned to the frequency of the detection gates, producing a clear signal when energized. Acousto-magnetic (AM) systems rely on magnetostrictive strips that vibrate under alternating magnetic fields, creating a distinct response. In both cases, the tag’s resonance or detuning is what makes it detectable—a simple but elegant exploitation of electromagnetic behavior.

Detection gates: Antennas at the exit

The tall panels at store exits are more than just barriers; they are antennas transmitting and receiving fields. As a tag passes through, it interacts with these fields, altering the electromagnetic environment in a way the system recognizes. That interaction—a resonant “signature”—is what triggers the alarm. Without it, the gates remain silent, underscoring how precise the tag–antenna relationship must be.

The shielding challenge: Countering the Faraday cage

While EAS systems are robust, they face a persistent challenge from tag shielding, a technique where shoplifters use “booster bags” lined with conductive materials like aluminum foil. This creates a Faraday cage—a metal barrier that blocks the electromagnetic or magnetic fields from reaching the tag, preventing it from resonating or “talking” to the detection gates.

Because the tag’s signal cannot penetrate the shield, the system remains silent even as the item passes through the antennas. To counter this, modern engineering has introduced metal detection sensors within the antennas that trigger an alert when a large volume of metal is detected, ensuring the system isn’t bypassed by simple physical interference.

Ink security tags: Benefit-denial strategy

Developed in 1984, ink security tags feature an ampoule of indelible dye that ruptures and seeps into a product when tampered with, rendering the stolen item useless. This benefit-denial strategy has since evolved to work alongside EAS, combining electronic monitoring with a visible deterrent that discourages thieves from attempting removal.

Modern designs integrate ink ampoules directly into EAS housings, available in both AM and RF frequencies to suit all common systems, while ink dye pins can also be added to existing tags as an extra layer of protection.

Types of EAS tags

Retailers deploy different tag formats depending on the product and security need. Hard tags are the familiar plastic housings with locking pins, designed to be durable and reusable. They’re common on apparel and electronics, where reusability offsets cost. Soft labels are adhesive-backed and disposable, often hidden in stickers or packaging. These are ideal for books, cosmetics, and boxed goods, where speed and convenience matter.

Finally, specialty tags are engineered for unique shapes or high-value items—think liquor bottles, eyewear, or luxury accessories. Their design ensures protection without interfering with the customer’s ability to handle or try the product.

Figure 1 Composite image captures a black RF security hard tag pinned to jeans, a second detached tag with its metal pin exposed, and a white rectangular AM soft label marked with a barcode pattern. Source: Author (composite); individual images belong to their respective producers

Deactivation vs. removal: Two paths to clearance

Checkout counters handle tags in two distinct ways. Soft labels, often hidden in stickers, are electronically deactivated by disrupting their resonant circuit. Once deactivated, they no longer respond to the exit gates.

Hard tags, however, are mechanical devices locked onto the product. These require a physical detacher to release them, ensuring they can be reused. The dual approach reflects retail priorities: speed for disposable labels, security and sustainability for reusable tags.

Engineering behind the scenes

The effectiveness of EAS systems rests on careful engineering choices. Materials science plays a central role: ferrite cores and resonant circuits are tuned for reliable response, while adhesives ensure soft labels stay in place without damaging products. Signal processing is equally critical, with systems designed to operate within specific frequency ranges, reduce false alarms, and manage interference from other electronics.

Finally, engineers face constant design trade-offs: balancing cost, durability, and detection reliability. A tag must be inexpensive enough for mass deployment, rugged enough to survive handling, and precise enough to trigger only when it should. This interplay of physics, electronics, and economics is what makes EAS technology both ubiquitous and invisible in everyday retail.

EAS tag frequencies: RF vs. AM

The performance of EAS systems hinges on their operating frequencies. RF tags typically resonate at 8.2 MHz, making them cost-effective and widely used for general merchandise. Acousto-magnetic (AM) tags, by contrast, operate at 58 kHz, using magnetostrictive strips that vibrate under alternating magnetic fields to deliver stronger detection in environments with metal shelving or foil packaging.

These frequency choices are deliberate: RF systems provide scalable protection for everyday goods, while AM systems excel in challenging conditions, reducing false alarms and ensuring consistent reliability. Frequency engineering, in short, is what makes EAS technology both practical and precise in modern retail.

Figure 2 8.2-MHz RF tags display the internal resonant coil structure and the standard barcode-printed adhesive backing. Source: Author (composite); individual images belong to their respective producers

Dual-frequency and RFID integration

Dual-frequency EAS tags combine AM (58 kHz) and RF (8.2 MHz) technologies into a single housing to ensure universal compatibility across different retail security systems, regardless of which hardware a specific store uses. This makes them the gold standard for source tagging, where manufacturers apply the security tags during production rather than at the store; because the tag is “universal,” the manufacturer can ship the same protected product to any retailer worldwide without worrying about system compatibility.

By further integrating RFID into this setup, the tag evolves into an all-in-one solution that not only triggers exit alarms to prevent theft but also provides item-level data for real-time inventory tracking and supply chain visibility from the factory floor to the point of sale.

Figure 3 This dual-technology label integrates a UHF RFID inlay and an EAS tag to provide item-level tracking and secondary loss prevention for retail apparel. Source: Avery Dennison

Just to clear the mist…

At the core of the above dual EAS technology lies the NXP UCODE 9 chip, a high sensitivity “brain” engineered to deliver superior read ranges and maintain stable signals even under physical interference or shifting environmental conditions. Operating within the global ultra-high frequency (UHF) band of 860–960 MHz, it ensures seamless tracking across international regulatory standards, enabling long-range detection far beyond the proximity limits of standard “tap-to-pay” systems.

Data management is anchored by a 96-bit Electronic Product Code (EPC) memory, a rewritable digital barcode for precise item identification, complemented by a 96-bit Tag Identifier (TID). This TID serves as a permanent digital fingerprint, factory-locked with a 48-bit unique serial number that provides hardware-level authentication and protection against counterfeiting—an identity that cannot be duplicated or altered.

Smarter EAS for modern retail

The evolution of EAS technology is not just about new features; it’s about reshaping retail practice. As mentioned before, source tagging embeds protection at the point of manufacture, streamlining store operations and ensuring every item arrives shelf-ready. Likewise, integration with RFID merges theft prevention with inventory intelligence, giving retailers real-time visibility into stock while safeguarding assets.

Smarter systems, powered by AI-driven analytics, further reduce false alarms by distinguishing genuine threats from background noise. The practical results are clear: shrink reduction delivers measurable savings, customer experience improves through unobtrusive security, and operational efficiency rises with reusable tags and scalable systems. Together, these innovations transform EAS from a silent guard at the exit into a strategic enabler of modern retail.

The harmonic handshake: Integrating EM physics and DSP intelligence

Modern electronic article surveillance systems achieve reliability through the sophisticated interplay of electromagnetic (EM) physics and digital signal processing (DSP).

EM tags, built around high-permeability amorphous metal, generate a distinctive non-linear magnetic response when exposed to a low-frequency interrogation field (typically between 10 Hz and 1 kHz). Thin, durable, and capable of indefinite activation or deactivation, these tags remain the gold standard for high-security applications such as libraries and pharmaceuticals. Yet the low-frequency spectrum they inhabit is increasingly crowded with electronic noise.

Figure 4 These adhesive electromagnetic strips integrate seamlessly into book gutters for discreet security. Source: The Library Store

Here the DSP becomes the system’s discerning ear, applying advanced algorithms to isolate the harmonic signatures produced by the EM strip. By analyzing the timing and ratios of these harmonics—especially the unique “spikes” created as the tag’s magnetic material reaches saturation—the DSP can instantly distinguish a genuine tag from background interference like power lines or moving metal doors.

This synergy preserves the physical strengths of EM technology, including detection through foil and ease of concealment, while adding digital intelligence that virtually eliminates the false alarms once common in legacy analog systems.

From security tags to ambient intelligence

The humble EAS tag is no longer just a one-bit alarm. It’s evolving into the foundation of ambient IoT—a world where everyday objects speak digitally without batteries or costly processors. By merging chip-free EAS principles with conductive inks and AI-driven signal processing, we’re entering the age of computational matter. Imagine a cereal box that not only sets off a gate alarm but also tells a recycling sorter what it’s made of and quietly alerts your smart kitchen when it’s nearing expiration.

And this isn’t just theory—it’s a call to action. For makers, the playground now includes conductive filaments and paints, where a 3D-printed resonator might shift frequency when bent or a touch sensor could be embedded directly into a wooden desk. For engineers, the challenge lies not only in faster chips but in mastering signal-to-noise ratio using machine learning to extract meaning from the messy electromagnetic echoes of chipless tags and designing packaging tech that’s as recyclable as the cardboard it’s printed on.

The future of IoT isn’t merely connected—it’s ambient, invisible, and accessible. Whether you’re hacking RF readers or sketching with graphene ink, remember that sophistication isn’t measured in transistor counts, but in achieving the most with the least. Keep tinkering, keep questioning, and let’s weave an internet into the very fabric of our world.

T. K. Hareendran is a self-taught electronics enthusiast with a strong passion for innovative circuit design and hands-on technology. He develops both experimental and practical electronic projects, documenting and sharing his work to support fellow tinkerers and learners. Beyond the workbench, he dedicates time to technical writing and hardware evaluations to contribute meaningfully to the maker community.

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