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Melexis has introduced a 5-V variant of its MLX90381 Triaxis pico-resolver for compact motor systems that rely on a 5-V supply. As motors become smaller and mechanical space more constrained, integrating accurate rotor position sensing becomes more challenging, particularly when end-of-shaft sensing is not possible. The MLX90381’s resolver-based position sensing provides greater flexibility in sensor positioning than TMR-based solutions, making it suitable for automotive, alternative mobility, and robotics motor applications.

Housed in a compact DFN-6 package measuring 2.0×2.5×1.0 mm, the MLX90381 combines Triaxis Hall technology with high-speed sine and cosine analog outputs. Its ability to sense magnetic flux density in three dimensions and use selectable X/Y, X/Z, or Z/Y magnetic axis pairs allows flexible sensor placement relative to the rotating magnet. In side-of-shaft and through-shaft motor designs, the sensor can be placed below or close to the magnetic track, reducing mechanical constraints and simplifying PCB placement and tolerance management in compact assemblies.

The MLX90381 5-V provides a 2-µs output refresh rate and measures rotational speeds above 50,000 rpm for precise rotor position detection in DC, BLDC and PMSM motors. Programmable sensitivity and filter bandwidth enable performance optimization, while I²C supports device configuration and production calibration.

Samples of the MLX90381 5-V are available now. Target use cases include e-valves, robotic actuators, cadence sensing, and motor applications for braking, steering, and seating.

MLX90381 product page

Melexis

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NVIDIA’s Jetson Orin Nano 2 system-on-module delivers nearly twice the inference performance of its predecessor, the Jetson Orin Nano Super. The performance boost comes from improved Tensor Cores and higher memory bandwidth. Nano 2 also maintains the same compact form factor as the Nano Super while consuming 40% less power in 15-W mode.

The robotics computer enables developers to build robots, delivery and inspection drones, and vision AI systems with advanced generative AI capabilities. NVIDIA says the Nano 2 combines up to 78 TOPS of AI performance, 8 GB of memory, and an 8-core Arm CPU in a cost-effective, power-efficient design.

Built on NVIDIA’s open software stack and supported by Jetson agent skills and a rich AI ecosystem, Jetson Orin Nano 2 allows developers to run the latest large language models (LLMs) and vision language models optimized for memory-efficient edge inference. These include open models such as NVIDIA Cosmos, NVIDIA Nemotron, Gemma 4, and Qwen 3.

The NVIDIA Jetson Orin Nano 2 module and developer kit are expected to be available in the first half of 2027.

NVIDIA

The post Robotics computer doubles edge AI performance appeared first on EDN.

SECO announced early access to hardware samples of its SOM-SMARC-Dragonwing-IQ8 module for industrial edge AI applications. Developed with Arduino and Qualcomm, the SMARC 2.1.1 module enables the transition from Arduino Ventuno Q prototyping to production-oriented architectures for AI-enabled robotics, smart machines, industrial vision, HMI, and machine control.

The system-on-module leverages the Qualcomm Dragonwing IQ-8275 processor, with AI acceleration options of up to 40 TOPS to meet various performance and price points. It provides up to 32 GB of LPDDR5/LPDDR5X memory and up to 1 TB of UFS 3.1 flash storage. Connectivity interfaces include Gigabit and 2.5-Gigabit Ethernet, PCIe Gen4, MIPI-CSI, and CAN-FD.

Developers can build and validate designs on the Ventuno Q and use the Arduino App Lab to port them to the SOM-SMARC-Dragonwing-IQ8. The module runs Clea OS, based on Yocto Linux, providing a consistent software baseline for secure lifecycle management, OTA updates, and connected device scalability.

A limited number of SOM-SMARC-Dragonwing-IQ8 samples are expected to be made available to select customers and partners for evaluation. Register here to receive updates on priority access.

SOM-SMARC-Dragonwing-IQ8 product page 

SECO

The post SMARC module bridges Arduino prototyping to production appeared first on EDN.

The nPZ2100 sensor-management and power-saving IC (PSIC) from Nanopower provides autonomous control for battery-constrained sensor systems. Based on the nPZero power-reduction architecture, the device manages sensors and peripherals while keeping the host MCU powered down until needed. This approach enables a simple operating principle: sense, decide, wake, and process.

With typical idle current consumption of just 200 nA at 3.0 V and polling current of 1 µA, the nPZ2100 can autonomously manage up to six independent peripherals through I²C or SPI interfaces. It integrates four 1-mA peripheral power switches and a dedicated 10-mA host power switch. The device also includes 256 bytes of SRAM for data logging, a three-channel ADC with battery monitoring, a 32-bit timer with alarm and watchdog, and a 32-bit counter, as well as power-aware operation for energy harvesting.

In addition to the MCU, the nPZ2100 can also power down peripherals when they are not required, helping eliminate their idle power consumption. Nanopower says that by taking over sensor communication and system monitoring while the host MCU is powered down, the nPZ2100 can significantly reduce the host’s active time and overall system energy consumption.

Development kits and engineering samples are planned to be available in September 2026, with full product release and volume manufacturing slated for Q2 2027.

nPZ2100 product page 

Nanopower Semiconductor

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Achronix now offers a JESD204C IP core for connecting high-speed ADCs and DACs to programmable logic in Speedster7t FPGAs. Each core supports data rates of up to 32 Gbps per lane and up to eight lanes per link, delivering an aggregate serial line rate of up to 256 Gbps. Combining up to four cores enables aggregate performance of up to 1 Tbps.

Designed for high-bandwidth, multichannel data-converter systems, the standards-based JESD204C core maintains backward compatibility with JESD204B to ease legacy system migration. It supports both 64b/66b and 8b/10b encoding, along with Forward Error Correction (FEC), CRC-12, and CRC-3 modes. Subclass-1 operation provides deterministic, phase-coherent latency for single- and multichannel systems. Flexible framing, integrated alignment and recovery features, and an AXI-Lite interface simplify system integration and control.

Speedster7t FPGAs integrate 112-Gbps SerDes to achieve the signal integrity needed for 32-Gbps JESD204C links. A 2D network-on-chip (NoC) provides high-bandwidth data transport across the device while reducing programmable-routing congestion and power consumption.

The Achronix JESD204C IP core for Speedster7t FPGAs is available now. The IP package includes a graphical interface in the Achronix ACE design environment, synthesizable VHDL/Verilog design files, templates, and example designs.

Achronix Semiconductor 

The post IP core provides scalable JESD204C connectivity appeared first on EDN.

Atlantic Alumina Company LLC (ATALCO, the only operating alumina refinery in the USA) has expanded its partnership with the US Department of War’s (DoW) Office of the Under Secretary of War for Acquisition & Sustainment, the Economic Defense Unit, and natural resource company Concord Resources Holdings Ltd (ATALCO’s majority owner), in conjunction with Concord’s majority shareholder (a fund managed by New York-based commodities investment firm Pinnacle Asset Management L.P). The new funding, in the form of $350m in preferred equity, brings total capital raised for the ATALCO facility in Gramercy, Louisiana and its critical mineral production to $800m since the start of the year, split evenly between $400m from the DoW and $400m from private investors through Pinnacle’s fund...

Build a simple soil moisture threshold detector with a PCB fork sensor, an LM393 comparator, and a relay output for visual and local control.

Vector Photonics Ltd of the West of Scotland Science Park — which was spun off from the University of Glasgow in 2020, and is pioneering the use of photonic crystal surface-emitting lasers (PCSEL) in secure communications — is exhibiting on stand 1468 at the European Conference on Optical Communication (ECOC 2026) in Malaga, Spain (20–24 September). The firm will discuss how its proven PCSEL technology can eliminate communications bottlenecks in AI data centers that are threatening to restrict performance...

Simple circuit saves hard-working fingers from unnecessary wear and tear.

Digital potentiometers (DPOTs) with manual up/down increment/decrement interfaces can have real utility as versatile substitutes for traditional electromechanical pots. But they start life with a big handicap.

No knob.

Wow the engineering world with your unique design: Design Ideas Submission Guide

The basic (and obvious) way to interface people with DPOTs is illustrated in Figure 1, using  push buttons to increment or decrement the setting, one pulse per push. It works. But it’s work!

Figure 1 In this reference circuit, Schmidt trigger U1 senses and de-bounces UP/DOWN momentary contact pushbuttons to (tediously) move the U2 setting by one position per push.

DPOTs need large numbers of setting positions (e.g. 64, 128, or 256) to provide enough resolution to make them useful. Large changes in setting using Figure 1 therefore require comparably large numbers of button pushes. This can entail considerable time consumed, and finger fatigue endured. You could get a blister! And that’s in addition to the potentially unpleasant (and dangerous?) effects of annoying your fellow lab-mates with the associated dripping-faucet sound effects!!

Figure 2 suggests a simple labor-saving remedy comprising just four added passive parts.

Figure 2 When a button is pushed down and held, the R5C2 time constant begins running. About a half second later, if the hold is still being held, the U1b multivibrator starts up, generating auto-repeating pulses at roughly 4 Hz for as long as the hold-down continues.

If we add the illustrated components to U1b, its basic function of contact bounce filter will be unaffected. That’s unless a button-down condition lasts longer than about a half second. If that happens, then C2 will discharge to below the pin 5 low-going Schmidt trigger threshold of V+/3, driving pin 6 high.

Now C2 will be quickly recharged through D1 and R4 (this takes ~3ms), generating another clock pulse to the pot that will duplicate the initial actuation. And so on and so forth, at 4Hz or so, until the button is released. Note that C2’s timeout between auto-repeats is shorter than the initial delay before they start. That’s because auto-repeat recharge ends at the Schmidt high-going threshold of only ~(2/3)V+ instead of running all the way up to V+ like it does between button pushes.

So what’s U1d for?  Well, when the pot arrives at the desired setting and the button is released, the R3C1 debounce time constant prevents the news from instantly arriving at U1b. Therefore, depending on how close C2 was to completing an autorepeat cycle, it’s possible that it will timeout before C1  does. If so, a bogus clock pulse and unintended pot increment could then theoretically occur.

To prevent this, U1d does a fast end-run around the auto-repeat oscillator to disable U2’s CS input. So even if the spurious pulse happens, the pot won’t see it. Not a big thing, but the gate was going to go to waste, anyway.

With a little practice, auto-repeat can be used to quickly get the pot very near a desired new setting. Then you can finished it off with a (mercifully) individual button push (or few) to arrive at the precisely needed final position.

Theoretically.

And a final remark. In an earlier Design Idea, I discussed the relative advantages of  buttons that actuate on push versus those that act on release. Whatever personal taste might otherwise dictate, it’s hard to imagine how the latter scheme could be made to work with the idea shown here.

Stephen Woodward‘s relationship with EDN’s DI column goes back quite a long way. Over 200 submissions have been accepted since his first contribution back in 1974.  They have included best Design Idea of the year in 1974 and 2001.

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The post Finger-friendly DPOT pushbuttons do ups, downs, and dittos appeared first on EDN.

Learn how to use the STEMMA QT/Qwiic connector on the Arduino UNO R4 WiFi to connect I²C sensors and displays, with a custom adapter board and example code.

AI-assisted chip design is not new. What is new is seeing an advanced ASIC reach tape-out in roughly nine months. The significance is not that AI can optimize individual design tasks; the industry already knows that. Synopsys and others have demonstrated AI-assisted implementation, verification, PPA optimization, and design-space exploration across many tape-outs.

What makes the nine-month result important is the possibility that architecture, RTL, verification, memory, network-on-chip (NoC), high-speed I/O (HSIO), design for testability (DFT), physical design, timing, and power were compressed together into a much tighter development cycle without losing overall convergence.

OpenAI and Broadcom’s Jalapeño program therefore raises a more important engineering question: How do you make many strongly dependent design activities move faster at the same time without allowing the chip to diverge?

The answer is unlikely to be one AI tool. Parallelism creates speed while intelligence-aware control keeps the design converging.

Speed begins with task parallelism

A semiconductor development flow is often shown as a sequence:

Architecture → RTL → Verification → Synthesis → Floorplan → Place & Route → Timing → Signoff

Experienced engineers know that real programs are never completely sequential. Architecture, RTL, verification, physical design, software, package definition, and other activities already overlap. But there are still expensive handoffs and feedback loops.

• Architecture decisions affect RTL.
• RTL changes affect verification.
• Synthesis exposes PPA problems.
• Physical design exposes congestion and timing problems.

These problems may propagate back into RTL, microarchitecture, memory organization, interfaces, or even the original partitioning. Every long loop consumes schedule, and AI and modern automation make it possible to push much more of this activity into continuous parallel execution.

However, architecture exploration can continue while RTL develops. Verification can run continuously against evolving blocks. Early synthesis and floorplanning can feed physical information upstream before RTL is frozen. Therefore, NoC, memory, HSIO, DFT, timing, power, and implementation teams can work simultaneously rather than waiting for a single completed design state.

In other words, AI can accelerate individual activities inside each of those workstreams. That creates speed, but it also creates a new problem.

A complex ASIC isn’t a collection of independent tasks

Consider something as simple as moving an HSIO PHY. Locally, the change might solve a placement or congestion problem. But that decision may propagate into:

Floorplan → Bump assignment → Package escape → Routing → Timing → Clocking → Power delivery → Signal integrity → DFT access → Local thermal behavior

The same problem exists throughout the chip. Change the NoC topology and bandwidth may improve, while latency, power, routing congestion, area, and verification requirements change. Change SRAM organization and compute utilization may improve while floorplan pressure and timing deteriorate.

Change pipeline depth and frequency and throughput may improve while latency, verification assumptions, clocking, and workload scheduling move in another direction. Change HBM or HSIO placement and the effect may extend beyond the silicon floorplan into package interfaces and power delivery.

This creates a fundamental problem: A locally optimized design decision can produce a globally worse chip. That’s why simply adding more AI tools cannot be the complete answer.

Imagine architecture AI, RTL AI, verification AI, DFT AI, physical-design AI, and timing optimization all running aggressively in parallel. Each one could produce a technically better answer within its own objective function. Yet together they could cause the overall design to diverge. Parallel execution therefore creates speed only if something maintains continuity between the parallel activities.

Parallel AI needs intelligence-aware control

Parallel execution therefore needs a second layer: intelligence-aware control. Call it an intelligence-aware control environment. Its purpose is not necessarily to design every transistor, block, or interface. Its purpose is to understand the relationships between design decisions and control how changes propagate through the development program.

For every significant modification, the environment should be capable of asking:

• What changed?
• What depends on it?
• Which assumptions may now be invalid?
• Which analyses must run again?
• Did this local improvement create a penalty somewhere else?
• Can the new result propagate automatically, or does it require engineering review?

That is more than launching EDA jobs. It requires awareness of the relationships among major design objects:

• Compute/NPU
• NoC
• SRAM and memory hierarchy
• HBM/DDR
• HSIO/PHY
• Clock and reset
• Power domains
• DFT
• Physical implementation
• Package interfaces

And each of these operates within engineering constraints: area, power, timing, bandwidth, latency, physical location, interface behavior, verification requirements, SI/PI limits, and thermal conditions. Change one object and some portion of these constraints may need to be reevaluated. The development environment therefore needs something resembling a live dependency map of the ASIC.

The real schedule savings may be in the feedback loops

Consider a conventional development loop. An RTL block changes, and verification runs. Later, synthesis exposes a problem and physical implementation discovers congestion. Next, STA identifies a timing issue and the problem returns upstream.

RTL or microarchitecture changes again. Downstream work repeats. So, while each individual tool may be fast, the engineering loop is slow. Now imagine a connected environment in which a change to an HSIO region immediately identifies the analyses affected by that change.

Perhaps it triggers update:

• Floorplan checks
• Timing checks
• Congestion checks
• Power checks
• Package-interface checks
• Signal-integrity checks

An NoC modification would activate a different dependency path. A compute-block modification might primarily require RTL verification, synthesis, PPA, timing, and physical evaluation. But the objective is not to rerun the entire chip every time something moves.

It is to understand what must be reevaluated because this particular design object changed. That distinction matters enormously. If feedback that previously took days arrives in hours—or minutes—many design loops can operate simultaneously without waiting for large downstream milestones. That is where months can begin disappearing from the schedule.

AI becomes more useful when boundaries are controlled

Within that environment, AI can operate aggressively on bounded engineering problems. It may help engineers explore architectural alternatives, generate or modify RTL, analyze verification failures, optimize arithmetic structures, evaluate physical alternatives, interpret timing results, propose ECOs, or search PPA space.

Synopsys’ existing products already demonstrate that AI can autonomously search enormous implementation and verification spaces and accelerate convergence within individual domains. The harder step is connecting those capabilities so that one accelerated decision does not silently invalidate another.

Instead of asking an AI system “Improve this block,” the environment can effectively ask “Improve this block while maintaining these timing, power, physical, interface, and verification constraints—and identify what downstream assumptions the change affects.” Now AI supplies speed and search capability while the control environment protects global convergence. That is a far more powerful combination.

Intelligence doesn’t eliminate engineering judgment

Suppose an optimization reduces area by 6%. Is that automatically better? No. That’s because congestion may increase, timing margin may fall, or current density may increase or redistribute. Moreover, DFT access may become more difficult and power density may create a local thermal problem. A high-speed interface may also move into a more difficult package region.

No single PPA number determines whether that design state is actually better. This is why Broadcom’s role in the OpenAI program is important. OpenAI explicitly credits Broadcom’s silicon implementation expertise as part of the nine-month result.

Years of ASIC experience create something that is difficult to reproduce quickly: an understanding of which dependencies matter, which trade-offs are acceptable, which interfaces are high risk, and which apparently small changes can create major downstream consequences. So, while AI may dramatically increase how many alternatives engineers can evaluate, experienced semiconductor teams still determine which alternatives are worth accepting.

Workload knowledge may also shorten architecture convergence

There is another advantage apparent in the OpenAI example. Jalapeño was not designed as a generic accelerator and then handed to an unknown software workload. OpenAI says the chip was built around knowledge of its models, kernels, serving systems, memory behavior, networking, scheduling, and product requirements.

That matters because many ASIC programs spend significant time determining what the chip should optimize. On the other hand, OpenAI began with extremely detailed knowledge of the workloads the silicon is expected to execute. That allows tighter co-development between:

Workload → Architecture → Memory → Networking → Scheduling → Silicon

OpenAI is now also reporting measured first-silicon results from Jalapeño, which makes the nine-month tape-out more significant than a purely simulated design exercise. But even here, the important lesson may not simply be “software-hardware co-design.” It’s that more design information becomes available earlier, reducing uncertainty that would otherwise propagate through later stages.

A nine-month tape-out is not yet a nine-month methodology

This distinction is important because a fast program could benefit from exceptional engineering talent, proven IP, mature implementation flows, large compute resources, rapid management decisions, deep Broadcom experience, OpenAI workload knowledge, extensive automation, and extraordinarily tight focus. These ingredients can produce an exceptional result.

However, an exceptional result is not automatically a repeatable process. The real proof comes with the next generations. Can ASIC #2 and ASIC #3 converge in approximately the same timeframe? Can the process deliver predictable verification closure, controlled ECO activity, consistent PPA, manageable engineering effort, and successful first silicon?

OpenAI and Broadcom describe Jalapeño as the beginning of a multi-generation platform. If the nine-month schedule becomes repeatable, then something more important has happened than simply using AI in chip design. For instance, how development methodology has changed.

The larger opportunity

The future of AI-assisted semiconductor design may therefore not be one giant AI system autonomously designing an entire system-on-chip (SoC). It may look more like many specialized engineering activities operating simultaneously:

• Architecture
• RTL
• Verification
• Memory/NoC
• DFT
• Physical implementation
• Timing/Power

With AI accelerating work within each of these domains, a higher-level control environment continuously maintains dependency, connectivity, change impact, feedback, and convergence across the complete development program. That gives us a much simpler way to understand the nine-month question: Parallelism creates speed; intelligence-aware control keeps the design converging; and AI can make each piece move faster.

The harder engineering challenge is making sure all of those faster-moving pieces continue advancing toward the same tape-out. If that can be accomplished repeatedly, the real achievement will not be one fast ASIC. It will be a new level of repeatable semiconductor development capability.

Dr. Moh Kolbehdari is senior director of IC/packaging at Socionext US.

Related Content

• 5 ways manufacturers benefit from AI in chip design
• The AI design world in 2026: What you need to know
• Four tie-ups uncover the emerging AI chip design models
• How AI is reshaping IC signoff: Trust, speed, and intelligent workflows
• First Benchmarks Revealed for Jalapeño, OpenAI’s Clean-Sheet General Purpose AI Accelerator ASIC

The post Why a nine-month AI chip tape-out matters appeared first on EDN.

Infineon Technologies AG of Munich, Germany and Skeleton Technologies, which provides high-power energy storage systems for AI data centers, have signed a memorandum of understanding (MoU) to collaborate on high-efficiency, resilient power solutions for modern data centers...

Rohde & Schwarz in collaboration with Qualcomm Technologies, Inc. has completed an early verification step for 3GPP Rel. 17 Search Space Set Group Switching (SSSG). This 5G NR feature, designed to reduce device power consumption, has now been formally submitted for RAN5 verification. This milestone supports the path from standardization to conformance testing and commercial use, while also feeding practical findings back into the standardization process.

Rohde & Schwarz has successfully verified for the first time a 3GPP NR conformance test case for Search Space Set Group Switching (SSSG). Introduced in 3GPP Release 17, SSSG is a power-saving mechanism for user equipment that improves how a device monitors control channel activity while maintaining reliable reception of scheduling information.

By completing verification of the 3GPP RAN5 NR conformance test case TS 38.523-1 TC 7.1.1.12.5 for SSSG at an early stage, the two companies supported early readiness of this feature across the 5G conformance ecosystem. The verification was carried out using a mobile test platform using Qualcomm X105 5G Modem-RF and the R&S TS-PCT protocol conformance test platform from Rohde & Schwarz, which is based on the CMX500 5G one-box signaling tester. SSSG optimizes the PDCCH monitoring behavior in 5G NR devices. This reduces unnecessary monitoring activity and helps improve power efficiency.

Rohde & Schwarz and Qualcomm Technologies are the first to complete all relevant test aspects for this conformance test case. During the verification work, the companies also identified areas where the underlying conformance specification could be improved and supported the submission of a change request to 3GPP RAN5, the group responsible for conformance test specifications. This links practical verification work with ongoing standardization development.

This combination of test execution and standards input shows how verification work can also improve the quality of future test specifications. For device manufacturers, the wireless chipset ecosystem and certification organizations, it marks a step toward reliable testing of advanced 5G power-saving functions.

The post Rohde & Schwarz has Achieved Initial Verification of 3GPP Rel. 17 Power-Saving Feature SSSG for 5G NR appeared first on ELE Times.

🎥 Майбутні інженери опановуватимуть реверс-інжиніринг у новій лабораторії на ФРП KPI4U-2 ср, 09/02/2026 - 12:58

US-based aerospace & defense technology company Northrop Grumman Corp has won a $7m contract to create diamond-cooled chips that deliver higher power, faster speeds and enhanced performance for military radar and communications...

To accelerate technical innovation and expand domestic manufacturing capabilities for solar panels in space applications, the US Department of Energy’s (DOE) Office of Critical Minerals and Energy Innovation has announced a $12m funding opportunity to help to ensure that the next generation of space photovoltaics (PV) is developed in the USA...

🍁 Три дні Японії в самому серці Києва — у КПІ ім. Ігоря Сікорського kpi ср, 09/02/2026 - 10:43

Vishay Intertechnology, today introduced two new low profile common mode chokes for high current automotive, energy, and industrial applications. Available in both surface-mount and through-hole packages, the Vishay Dale commercial ICMS2321 10 and Automotive Grade ICMS2321-1A combine a heat rating current to 30 A with a 1500 VDC dielectric withstand voltage between coils.

With their low profile, the devices released today offer a reduced size and volume, making them more resistant to shock and vibration, while their enhanced core design increases performance and saturation current at high temperatures up to +150 °C. Offering a self-shielded, rugged construction, the common mode chokes are ideal for DC/DC converters, high voltage inverters, EMI filters, and high current filters for noise suppression in motor control and other circuitry. The AEC-Q200 qualified ICMS2321-1A is well suited for use in automotive on-board chargers.

In addition to their surface-mount and through-hole mounting options, the ICMS2321-10 and ICMS2321-1A offer customizable inductance, impedance, DCR, and current ratings. Devices with surface-mount terminations are available in tape and reel packaging and are compatible with automated pick and place assembly for increased flexibility in board layouts. The common mode chokes are RoHS-compliant, halogen-free, and Vishay Green.

Device Specification Table:

Part number		ICMS2321-10	ICMS2321-1A
Inductance		70 µH to 480 µH
DCR typ.		1.2 mΩ to 13.4 mΩ
DCR max.		1.3 mΩ to 15.0 mΩ
Common mode impedance	@ 1 MHz	540 Ω to 3790 Ω
	@ 10 MHz	345 Ω to 1920 Ω
	@ 100 MHz	220 Ω to 410 Ω
Heat rating current typ.(1)		7 A to 20 A
Heat rating current typ.(2)		10 A to 30 A
Leakage max.		1.7 µH to 11.5 µH
AEC-Q200		No	Yes

 

(1) DC current (A) that will cause an approximate ΔT of 40 °C

(2) DC current (A) that will cause an approximate ΔT of 100 °C

The post Vishay Intertechnology Commercial and Automotive Grade Low Profile Common Mode Chokes Offer High Shock and Vibration Resistance appeared first on ELE Times.

The IOX-77 is an ESP32-C3-based development board that packs 75 GPIO pins into a compact 71 × 42 mm PCB, using five RISC-V CH32V003 microcontrollers on an I²C bus for parallel execution and expandability.

In electronics manufacturing, material and quality testing using X-ray inspection is considered the gold standard for reliability and the highest standards. For years, GÖPEL electronic has been a leader in the field of inspection and non-destructive, comprehensive assembly testing at all levels. With a completely newly developed system platform, the manufacturer now presents next-generation X-ray inspection: The Multi Line AXI combines outstanding technological innovations with highly versatile application options and multifunctionality, while offering simple operation and rapid adaptability to inspection tasks. The result is an innovative AXI system that sets new standards in X-ray inspection—offering a secure investment and high performance.

Technically, the Multi Line AXI stands out as a state-of-the-art planar 3D-CT X-ray system, offering the highest possible resolution and razor-sharp cross-sectional images. Based on the company’s proprietary aspeCT technology, the system achieves new levels of precision and image quality in X-ray inspection. Using a high-resolution, high-speed flat-panel detector, the detailed images are transformed into intelligent 3D reconstructions and volumetric 3D images and models of the highest quality. An innovative 7-axis system with synchronized control ensures high-speed, on-the-fly CT imaging in the shortest possible time: In less than 2 seconds, and with 8 µm voxel resolution, the Multi Line AXI offers flexible 2D, 2.5D, and 3D X-ray imaging as needed, using microfocus X-ray tubes and in sub-micrometer increments. This makes the system a highly secure investment and versatile in its application, manufactured entirely in Jena.

In addition to its outstanding technology, the Multi Line AXI has been consistently designed for broad applicability, reliability, and low-maintenance operation. With an 810×535 mm inspection area, a maximum PCBA clearance of 105 mm, and a transport capacity of up to 25 kg in its flexible transport system, both the smallest PCBAs and large power electronics can be inspected quickly and with consistently high quality. Thanks to the use of parts from exclusively European suppliers and German-brand mechanical components, the system is extremely durable and reliable. The Multi Line AXI’s platform concept makes upgrades, expansions, and repairs quick and easy. Furthermore, the system can be integrated into any manufacturing or inspection environment—whether inline, at-line, or stand-alone. It interfaces seamlessly with the manufacturer’s MES and can be integrated into traceability systems. High repeatability, variable X-ray performance as needed, and adaptability to high mix, low-volume production are hallmarks of the Multi Line AXI.

However, a system’s performance and quality are only the foundation—in everyday use, an AXI system must be quickly adaptable to specific inspection tasks and easy to operate. The Multi Line AXI guarantees this through its seamless integration into the PILOT software platform’s user interface, which has also proven itself in GÖPEL AOI systems. Inspection programs are automatically generated using “Magic Click” based on Gerber and assembly data or other CAD formats (ODB++, Process, etc.). For reliable verification, the PASS/FAIL evaluation is supported by intelligent AI assistants. This transforms detailed X-ray images into actionable inspection results—ensuring the quality and security of the PCBA. Short programming times and comprehensive evaluation of results—including precise void calculation and THT fill rate measurement in percent—combined with GÖPEL electronic’s software and inspection intelligence make the Multi Line AXI practical and suitable for everyday use, intuitive to operate, and customizable.

In developing the new X-ray inspection system, GÖPEL electronic also addressed questions about the future: How do we want to manage our resources? As a result, the Multi Line AXI is designed as a “Lean & Green Machine” focused on resource conservation, energy efficiency, and sustainability. The manufacturer has deliberately omitted pneumatic components and compressed air, which not only simplifies installation and operation but also reduces maintenance and operating costs. With its lightweight design—weighing just 2.7 metric tons and featuring a compact footprint of 1600×1660—this X-ray system requires no special structural preparations and can be installed quickly and easily in virtually any environment. Based on GÖPEL electronic’s many years of experience, the system is designed from the outset to be durable, upgradeable, and reusable, with easy access for service and maintenance.

The post GÖPEL electronic Introduces the New Multi Line AXI 3D-CT X-Ray Inspection System appeared first on ELE Times.