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Gallium nitride (GaN) and silicon carbide (SiC) power semiconductor firm Navitas Semiconductor Corp of Torrance, CA, USA has been awarded the ALATTIS (Accelerated, Large-Area, 10kV SiC IGBT) program to develop next-generation 10kV silicon carbide (SiC) power semiconductor technology...

Firehat is an open-source HAT that brings native IEEE 1394 FireWire to boards such as the Raspberry Pi 5 and the Radxa ROCK 2F. It adds an i.LINK/DV port to modern SBCs, eliminating the need for older computers. The board uses the VIA VT6315N controller and connects through the 40-pin GPIO header and the PCIe FFC connector. In this way, Firehat becomes a bridge between the DV world and digital storage.

The project solves a real problem: MiniDV and HDV camcorders use FireWire, but modern computers no longer have that port. Firehat fills the gap with a compact, open-source solution. The board measures 56 x 70 x 12 mm and weighs just 25 grams. It costs $79, a reasonable price for anyone who needs to digitize precious tapes.

How Firehat works

Firehat uses two separate connections on the SBC. The 40-pin GPIO header provides power and handles the OLED, buttons, LEDs, and buzzer. The PCIe FFC connection, on the other hand, carries FireWire data between the VIA VT6315N controller and the board. On Linux, Firehat appears as a standard PCIe FireWire controller, using the kernel’s FireWire stack.

DV capture is handled with open-source tools such as dvgrab and dvcont, or with the Equip-1 software stack for a standalone recorder interface. FireWire device control allows you to play, stop, rewind, and trigger captures via software. In addition, libavc1394 support enables reliable communication with camcorders.

For those who want to build the project themselves, you need an SBC with a PCIe FFC connector. The board with the Raspberry Pi 5 is the most common choice, but the Radxa ROCK 2F also works well. Firehat also includes a 1.3-inch OLED display and SK6812 RGB LEDs for status. Everything mounts in a compact case with accessible connectors.

Why digitize with FireWire

MiniDV, Digital8, DVCAM, DVCPRO, and HDV camcorders record to tape. Without FireWire, recovering those videos is a nightmare. Firehat lets you capture the digital DV stream directly to local storage without any quality loss. The DV stream is already digital, so no analog conversion is needed.

The project is designed for makers and archivists. Thanks to Linux support, captures can be automated with scripts. For example, you can rewind the tape, start recording, and stop at the end, all from the command line. Additionally, a 128×64 OLED display shows capture status in real time.

Firehat is not just an adapter; it is a true FireWire controller. The VIA VT6315N chip handles the IEEE 1394 protocol at the hardware level, while the software takes care of the rest. The 30 cm PCIe FFC connection ensures flexibility in mounting. The result is a stable and fast board, suitable even for long capture sessions.

What you need to get started

To use Firehat you need only a few items. Here is the essential list:

• An SBC with a PCIe FFC connector, such as the Raspberry Pi 5 or Radxa ROCK 2F
• Firehat with VIA VT6315N controller and OLED display
• A FireWire camcorder with DV or HDV tape
• Linux with FireWire stack and dvgrab, dvcont, or Equip-1 tools

Assembly is simple: connect Firehat to the GPIO and the PCIe FFC, then boot the SBC. On Linux, the controller is recognized automatically. Finally, run dvgrab to start capturing. No hardware modification to the camcorder is required.

Firehat is available for $79 and the design is open-source, so you can also study the project. An SPI 256×64 OLED display can be added for richer interfaces, but the included 1.3-inch one is enough for most uses. The board is robust and well documented.

In conclusion, Firehat is the modern solution for those with legacy camcorders who want to save their footage. It combines open-source hardware, Linux software, and an accessible price. For anyone working with video archives, it is an indispensable tool.

Source: https://github.com/computerequipmentgroup/firehat

The post Firehat: Bringing FireWire to the Raspberry Pi 5 appeared first on Open Electronics.

As automotive, AI/data centre, networking and industrial systems rapidly transition to 48V power architectures to improve efficiency and support higher power demands, designers require more than visibility into instantaneous voltage and current conditions. They also need systems that can track energy consumption over time and respond to changing power conditions. To address these requirements, Microchip Technology has introduced the PAC1761 and PAC1861 families of 65V energy-aware digital power monitors. The devices combine accumulated energy-measurement capabilities with 65V measurement headroom and transient spike protection to support efficient and resilient 48V power architectures.

The move to 48V power architectures requires digital power monitors to provide additional operating margin, including up to 65V measurement capability and 75V spike protection to ensure transient survivability. The PAC1761 and PAC1861 devices add intelligence to these capabilities, enabling real-time responses to energy-usage dynamics based on accumulated power measurement data.

“The industry conversation is shifting from measuring power at a single point in time to understanding and responding to energy behavior across an entire system and its lifecycle,” said Keith Pazul, vice president of Microchip’s mixed-signal linear business unit. “The PAC1761 and PAC1861 families are designed to help customers build better performing and more reliable 48V systems that can measure instantaneous conditions and understand energy consumption and availability over time. These scalable, low-power solutions reduce monitoring overhead and include pin-compatible package options that improve source flexibility while reducing design risk.”

Microchip’s digital power monitoring devices feature programmable alerts for voltage, current and power excursions, step-limit detection to identify sudden load changes, and configurable accumulated-energy thresholds that enable proactive system management based on both instantaneous and long-term power behavior.

Target applications include automotive, AI/data center, networking, industrial, server, telecom/Power over Ethernet (PoE) and 48V power distribution systems. The 12-bit PAC1761 and 16-bit PAC1861 options are available in VDFN-8 (similar to SOT23-8), VDFN-10 and MSOP-10 packages including automotive-orderable variants. Pin-compatible options can reduce redesign risk, shorten qualification cycles and give customers flexibility to move between devices as requirements, availability, cost or performance change.

Development Tools

Development support includes evaluation board EV12R33A, a Python Command Line Interface (CLI) with library, Linux driver and generic C library with multiple MCU code examples.

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Modern RTL verification flows generate more evidence than engineers can always review with equal priority. Simulation, assertions, coverage, and formal analysis each expose different classes of behavior, but a large design can produce hundreds or thousands of properties.

This article describes an AI-assisted workflow that uses machine learning to prioritize those properties while leaving proof and counterexample generation to the formal engine. The approach is intended to complement, not replace, established SystemVerilog, Universal Verification Methodology (UVM), simulation, and formal verification practices.

The problem: too many properties, too little verification time

Verification teams face a practical allocation problem. A complex subsystem may include control-state logic, FIFO interfaces, arbitration, multiple clock domains, configuration registers, error handling, and protocol checks. Each area can generate assertions, and each assertion can have a different verification cost and value. Some properties prove quickly. Others expose difficult corner cases or consume substantial solver resources.

Simulation remains essential because it exercises realistic scenarios, software interactions, coverage goals, and system-level behavior. Formal verification offers a different capability: it can prove or disprove a specified property over the modeled state space under explicit assumptions. Formal methods therefore complement simulation rather than simply compete with it.

The remaining question is operational: when a verification environment contains a large property set, which properties should receive attention first? Engineers normally answer this using design knowledge, coverage, previous failures, proof history, and experience. As designs grow, an automated way to organize that evidence becomes attractive.

AI as a prioritization layer

Machine learning has become an active research area in electronic design automation, including hardware design and verification. For formal verification, the most useful role may be narrower than asking AI to determine whether a design is correct. AI can instead act as a prioritization layer in front of the formal engine.

The model can assign a priority to each property using features such as RTL hierarchy, number of referenced signals, control and data dependencies, state-machine complexity, clock relationships, previous proof duration, coverage gaps, prior failures, and related assertions. The output is a recommendation about verification order, not a proof result.

A five-stage workflow

The workflow can be organized in five stages: RTL and property analysis, feature extraction, AI-based property ranking, formal execution, and feedback.

Figure 1 Here is a broad view of the five-stage AI-assisted formal verification workflow. Source: Author

1. RTL and property analysis: Collect the RTL, assertions, hierarchy, interfaces, assumptions, and available verification metadata.
2. Feature extraction: Convert verification information into features that describe structural complexity, dependencies, coverage, history, and proof behavior.
3. AI-based ranking: Use one or more machine-learning models to estimate which properties may provide useful verification information earlier.
4. Formal execution: Run selected properties in the formal engine, which produces the authoritative proof result or counterexample.
5. Feedback: Feed proof results, counterexamples, and verification history back into the prioritization process.

Why use more than one model?

A single machine-learning model may not capture every relationship in a verification dataset. A hybrid system can compare recommendations from multiple models and look for agreement. If several models independently place a property near the top of the queue, the system can treat that agreement as a scheduling signal.

This does not make the prediction a formal result. The distinction is important. Machine learning estimates where verification effort may be useful; formal verification establishes whether the selected property holds under the specified assumptions.

Figure 2 In this illustrative AI-assisted property prioritization, scores are conceptual and are not measured results from a specific project. Source: Author

Counterexamples can become verification feedback

A formal counterexample contains more information than a pass/fail label. It can expose a state transition, control path, boundary condition, protocol sequence, or assumption associated with failure. A verification workflow can use those observations to identify related properties that deserve attention.

For example, consider a hypothetical subsystem with a FIFO, arbitration logic, and two clock domains. Suppose a clock-domain property receives high priority because it involves multiple clocks, has limited simulation coverage, and is related to previous failures. If formal analysis produces a counterexample, the system can increase the priority of other properties that share the affected control or clock-domain path.

This is a feedback mechanism, not autonomous verification. The engineer still determines whether the property is correctly formulated, whether assumptions are valid, and whether the resulting evidence is sufficient.

Working with UVM and simulation

The AI layer does not require a new verification environment. Existing SystemVerilog and UVM infrastructure already produces useful information, including test results, functional coverage, assertion status, regression history, and debug information.

Figure 3 UVM and simulation data have been integrated with AI analysis, formal verification, and engineer review. Source: Author

Simulation can provide scenario coverage and failure information. UVM can provide structured testbench and regression data. The AI layer can organize these signals and recommend formal priorities. The formal engine can then produce proofs or counterexamples. This division lets each part of the flow retain its established role.

• Review low-confidence or strongly disagreeing model recommendations manually.
• Keep AI priority, formal status, and signoff status as separate fields.
• Record the features and model version that produced each recommendation.
• Make sure that critical properties are protected by explicit rules.

In a continuous-integration environment, the loop can run after an RTL change: identify affected properties, update their features, generate priorities, execute selected formal jobs, collect results, and store the new evidence. The next run can then use that history. The result is a practical feedback loop that fits around existing verification infrastructure instead of requiring a separate verification methodology.

The scheduler should also enforce engineering rules outside the model. A property marked as mandatory for signoff should remain in the verification plan even if the model assigns it a low priority. Likewise, the system can reserve resources for regression baselines while using AI to order the remaining work. This makes the AI layer a scheduling aid rather than an uncontrolled gatekeeper.

For example, a property record might contain the number of referenced signals, hierarchy depth, number of state elements involved, clock-domain count, previous proof time, previous failure frequency, coverage status, and whether the property belongs to a critical interface or reset sequence. These features are useful because engineers can inspect them and relate them to the underlying design rather than relying on an opaque score.

The approach can be introduced without replacing the existing verification tool chain. A lightweight orchestration script can collect RTL and assertion metadata, regression results, coverage summaries, formal proof history, and counterexample information. The collected information can be normalized into one record per property. Each record can then be passed to a trained model or a small ensemble of models that returns a priority recommendation.

Turning the concept into an engineering workflow

Below is an illustrative property prioritization example.

Table 1 In this illustrative prioritization example, the entries demonstrate the method and are not experimental measurements. Source: Author

The main benefit is not that AI makes formal verification mathematically stronger. The benefit is that it can help organize verification work. A team can use prioritization to focus compute time on properties associated with complex control, weak coverage, previous failures, or other signals that indicate potential value.

The same idea can help with regression management. If a new RTL revision changes a particular control path, the system can identify related properties and move them upward in the queue. If a property repeatedly consumes large amounts of solver time without producing useful evidence, engineers can inspect its formulation and decide whether to refine it, decompose it, or change its assumptions.

What AI should not decide

AI-based prioritization introduces a new failure mode if engineers treat a low score as permission to ignore a critical property. The system should therefore preserve explicit criticality rules. Safety-critical, security-sensitive, interface, reset, and other signoff properties may require execution regardless of their predicted rank.

The workflow should also remain explainable. Engineers should be able to see which features influenced a ranking and distinguish between a property that was not selected, a property that timed out, and a property that was formally proven. These states carry very different meanings.

From verification execution to verification management

As IC designs become larger, verification teams need more than additional tests. They need ways to organize the evidence produced by tests, assertions, coverage, formal analysis, and debug. AI can provide one layer of that organization.

The practical model is therefore a division of responsibility. Simulation explores scenarios. UVM structures the verification environment. AI analyzes evidence and recommends priorities. Formal verification supplies rigorous proofs and counterexamples. Engineers interpret the results and make signoff decisions.

AI-assisted formal verification is most useful when it remains an assistant to established verification methods. Using machine learning to prioritize properties can help teams direct limited compute and engineering resources toward potentially informative checks, while formal verification remains the authority for proof and counterexample generation.

The approach does not require replacing SystemVerilog, UVM, simulation, or existing formal tools. It adds a layer that connects the evidence those systems already produce. With appropriate safeguards, that layer can turn verification history and counterexamples into feedback for the next analysis cycle.

Praveen Kumar Vagala is a semiconductor design verification professional and independent researcher with extensive experience in the semiconductor industry.

Related Content

• Introduction to Formal Verification
• Is Formal Verification Artificial Intelligence?
• Formal verification: where to use it and why
• Specifications: The hidden bargain for formal verification
• Formal Verification Moves Firmly into the Design Environment

The post Rethinking RTL flows with AI-driven hybrid formal verification appeared first on EDN.

Battery-swapping technology allows electric heavy trucks to replace a drained battery placed between the frame rails with a fully charged one at a charging station in just 5 to 10 minutes. Unlike conventional plug-in EV trucks, battery-swapping vehicles are designed with modular and removable battery packs along with the mechanical, electrical and communication interfaces required for rapid battery exchange.

Automated swapping equipment can then remove the depleted pack and install a charged one. Current heavy-duty EV examples in India demonstrate the growing adoption of this approach, with some systems completing a battery swap in less than five to seven minutes.

This battery-swapping technology is gaining attention in India’s EV transportation sector as manufacturers look for a better option to reduce electric vehicle charging downtime. It also provides an advantage of lower upfront costs because the battery is owned by a battery-swapping operator, allowing the customer to pay for battery use through a subscription.

This technology is now moving beyond the deployment phase towards a wider infrastructure network. In July 2026, Energy In Motion (EIM) and Hindustan Petroleum Corporation Limited (HPCL) announced plans to develop fast-charging and battery swapping stations for heavy EV trucks at specific HPCL petrol pumps or service stations. The partnership company (EIM) will establish swap-and-charge hubs along freight corridors including Mumbai-Pune, Delhi-Jaipur and Chennai-Bengaluru over the next 18 to 24 months.

The implementation of battery-swapping at a wider scale demonstrates that India is adopting modern technologies to provide faster and efficient charging solutions to the EV industry. The adoption of this technology at a very large scale will depend on several factors such as battery standardisation, station availability, interoperability, fleet economics, and the development of reliable freight-corridor infrastructure.

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​The demand for electric vehicles is continuously rising in India. Government and charging companies are making continuous efforts to make charging easy for consumers by expanding charging infrastructure and improving charging efficiency. But increasing the number of chargers alone is not sufficient to provide a reliable charging experience.

A new report from the Institute for Energy Economics and Financial Analysis (IEEFA) found that charger reliability, interoperability, charging cost, home-charging challenges and delays in grid connection are rising problems affecting EV charging in India. The report was published on September 16, 2026.

In the early stages of EV adoption, vehicle range was a major focus for manufacturers and consumers. As EV sales and charging infrastructure continue to expand, attention is increasingly turning​to the reliability and accessibility of charging infrastructure. A charging station is useful only when it is operational and available when an EV user needs it.

Network interoperability is another growing concern, as different charging networks may require separate apps, accounts or payment systems, making it less convenient for users to access and pay for charging across different locations. IEEFA has identified charger reliability and interoperability among charging networks as key factors that need to be addressed to improve India’s EV charging experience.

As India’s charging network continues to grow, the next stage of development will therefore depend not only on deploying more chargers but also on improving their reliability, interoperability, affordability and integration with the electricity grid.

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As manufactures and battery material companies are searching for increasing energy density and improve charging performance in electric vehicles, silicon-based anode technology that replace traditional graphite parts with silicon-based materials is gaining momentum in the electric vehicle (EV) battery industry. The advantage of adopting these technologies is that it holds significantly more lithium ions (up to 10 times more lithium per gram than standard graphite) to boost energy storage of an anode without increasing its size.

Although, this technology suffers from big challenges such as silicon undergo tremendous expansion once it absorbs lithium during charging. This expansion can destroy the anode and cause capacity loss over repeated charging cycles. Researchers have come up with the solution of using silicon-carbon composites to overcome this problem. By combining silicon with carbon based materials can accommodate the expansion to preserve the anode stability.

The technology has new completed its testing phase and is new ready to be implement toward large-scale manufacturing. Group14 Technologies, an American battery technology company, in March 2026 announced that its South Korea battery- material plant for silicon batteries has started production of its SCC55 material at the scale needed for EV batteries. The plant can produce up to 2,000 tonnes of silicon battery material per year, which should amount to about 10 GWh of energy-storage capacity annually once production reaches its planned level.

Australia is another major supporting commercialisation of this silicon-adopting material for energy storage. The Australian Renewable Energy Agency (ARENA) announced an award of $45 million to silicon battery technologies to build a commercial scale facility for advanced silicon-carbon battery material.

These developments put silicon-carbon anodes closer to commercialisation. If the manufacturers can overcome the issues of cost, cycle life, expansion and manufacturing scale, then the technology could contribute to higher battery energy density in future EV batteries, while allowing for faster charging.

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With the rise in the implementation of software technologies in Electric vehicles, the transition towards Software-Defined Vehicles (SDVs) is changing how electric vehicles are designed. Technologies in software-defined vehicles such as advanced automotive semiconductors, edge artificial intelligence (AI) and centralised computing are becoming key concepts in designing future transportation vehicles.

During electronica India 2026 held at Bangalore International Exhibition Centre (BIEC), Renesas Electronics showcased technologies related to SDVs, edge AI, EV charging and intelligent mobility. These technologies highlight the growing role of semiconductor-based computing in designing next-generation vehicles. At the event, Renesas demonstrated its newly designed 3nm multi-domain automotive SoC, the R-Car Gen 5 platform, highlighting features such as advanced driver assistance systems (ADAS), digital cockpit technologies and connected-vehicle solutions providing personalised functions and voice interfaces.

The platform combines high-performance automotive computing with AI capabilities and supports software-defined vehicle architectures. Edge Intelligence was another area of interest, where AI processing is being executed with the help of the vehicle’s sensors and systems instead of depending on cloud interface. Renesas demonstrated applications that support AI vision, autonomous and assisted driving for the driver, and embedded intelligence.

Edge AI can result in faster local responses compared to cloud connectivity and reduce the amount of sensor data that needs to be transmitted to external system. As EV architectures shift towards software-defined systems, the use of advanced automotive system-on-chip (SoC) platforms, edge AI, power semiconductors, and software platform will increasingly play an important role in vehicle computing, charging, connectivity, and smart mobility.

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SEMICON India 2026, the fifth edition of India’s flagship semiconductor conference, concluded on September 19 at Yashobhoomi, New Delhi, highlighting the country’s growing capabilities across the global semiconductor value chain. Held from September 17 to 19 under the theme “Silicon to Systems: Building the Ecosystem,” the three-day event brought together semiconductor companies, policymakers, investors, academia and start-ups.

The event featured more than 600 exhibitors, including around 300 international participants, with representatives from 52 countries and more than 150 speakers. Six country pavilions representing Japan, South Korea, Malaysia, the Netherlands, Singapore and Sweden, along with 12 state pavilions, showcased capabilities across different areas of the semiconductor ecosystem. The event recorded 51,656 registrations and around 40,000 cumulative footfall.

Prime Minister Narendra Modi inaugurated SEMICON India 2026 highlighting India’s progression from policy discussions and project planning to commercial semiconductor production. During the inauguration, the Prime Minister virtually inaugurated commercial production lines at CDIL Semiconductor in Mohali for discrete semiconductor devices and Suchi Semicon in Surat for semiconductor packaging. The two facilities added to India’s operational commercial semiconductor units under the Semicon 1.0 programme.

As a major outcome of SEMICON India 2026, a total of 56 MoUs, announcements and strategic initiatives were announced across areas including semiconductor design, fabrication, advanced packaging, equipment, materials, power electronics, AI, R&D, startups and talent development.

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Due to massive pool of specialised VLSI (Very Large Scale Integration) engineers, large number of Global Capability Centre (GCCs) presence and ongoing government support, India currently accounts for nearly 20% of the world’s semiconductor design workforce. This number highlights the India’s increasing role in global chip design and research. The statement of accounting 20% global workforce in semiconductor design was made by S. Krishnan, the MeitY Secretary on the side-lines of SEMICON India 2026 in New Delhi.

The government is prioritising the development of semiconductor design talent, said S. Krishnan. He said an ongoing programme is focused on training around 85,000 semiconductor design engineers, while skill-development efforts are also being expanded across the semiconductor value chain, with a strong focus on supporting semiconductor manufacturing in India.

The semiconductor design workforce will play an important in strengthening India’s position in the global semiconductor ecosystem. According to government data, India holds 7% of the world’s semiconductor-related Global Capability Centres (GCSs) along with Indian engineers continue to contributing to chip design, fabrication, verification and testing activities.

The government is taking action to move beyond design and improve semiconductor ecosystem by covering fabrication, advanced packaging, assembly and testing, semiconductor equipment and materials, research and development (R&D), and talent development. The recent organised event Semicon 2.0 has an outlay of ₹1,27,500 crore and is structured around six pillars which include design, machine, materials, advanced packaging, additional fabs, research, and talent.

There are different schemes supported by the government body encouraging semiconductor design which include Design Linked Incentive (DLI) Scheme and the Chips to Startup (C2S) Programme. The focus of these programmes is to train around 85,000 semiconductor design engineers. The initiatives are also aimed at strengthening India’s domestic chip-design capabilities and building a stronger semiconductor design ecosystem.

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India continues to focus on raising domestic value addition and further deepening domestic manufacturing in electronics industry. Moving beyond large-scale assembly towards deeper manufacturing and stronger local supply chains, S. Krishnan, the Secretary of the Ministry of Electronics and Information Technology (MeitY) made the statement that India is targeting 35-40% domestic value addition in mobile-phone manufacturing, up from the current level of about 22-23%. To achieve this number, different government schemes are giving support such as India Semiconductor Mission (ISM), mobile manufacturing, the Production Linked Incentive (PLI) for electronics hardware and the Electronics Component Manufacturing Scheme (ECMS).

The Electronics Component and Manufacturing Scheme (ECMS) is expected to play a major role by focusing on deep component-level manufacturing rather than basic assembly. Key areas include printed circuit boards, passive components, electrochemical components, subassemblies, camera module, optical transceivers, and critical equipment.

The government aims to wider the development of India’s semiconductor ecosystem by expanding capabilities across components, semiconductor manufacturing and other parts of electronics value chain. ECMS is designed to integrate Indian manufactures with global value chains and ISM supports semiconductor design, fabrication, advanced packaging, equipment and materials.

The 40% target in domestic manufacturing does not means that forty percent of the electronic devices to be made in India. It means if a device is selling in India, then its forty percent value must be manufactured within the country. This target reflect India’s deepen participation in global value chains by moving beyond final assembly, creating a deeper supplier ecosystem, reduce dependence on imported components, and moving towards complete manufacturing location. This will allow Indian factories to source more inputs locally while maintaining competitive cost, quality and scale.

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On 22 September 2026, North Korea said it had tested a new weapon system that it claimed utilised modern defence technology. State media images seem to indicate that North Korea tested an improved Hwasongpho-11Ma short-range ballistic missile capable of carrying a manoeuvrable hypersonic glide vehicle. South Korea’s military identified two missiles fired from the Wonsan area on 20 September, which it said travelled 450 kilometres and 600 kilometres before crashing into the sea.

North Korean reporting gave other performance numbers that could not be checked. A hypersonic glide vehicle is a rocket disseminated missile released from a booster that then glides course toward its target at very high speeds and altitude. Its capability to change course after launch presents a challenge to tracking and destroying it because of the ballistic predictability for defenders.

Latest test indicates progress by Pyongyang in enhancing the lethality and penetrability of its short-range missile arsenal. Such weapons, if employed, are likely meant to saturate regional missile-defence systems through rapid, highly manoeuvrable and possibly erratic flight trajectories. Still, outside analysts are sceptical of North Korea’s claims: briefly achieving hypersonic speed is one thing; sustained hypersonic manoeuvring-especially under realistic operational conditions- is another.

Additional launches will be necessary to determine the missile’s precision, guidance accuracy and ability to defeat existing missile defences. The missile test, however, inevitably heightens South Korea’s, Japan’s and the United States’ urgency to enhance regional tracking and interception capabilities.

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Lockheed Martin won a US Army contract worth up to US$1.2 billion for production of the Increment 2 configuration of the PrSM, or Precision Strike Missile. The contract announced on 21 September 2026 supports the Army’s effort to succeed the legacy Army Tactical Missile System. PrSM is a surface-to-surface precision missile launched from the M142 High Mobility Artillery Rocket System and the tracked M270 Multiple Launch Rocket System.

Its more compact size will enable the two launch pods to carry two PrSM rounds per pod as opposed to one ATACMS missile, which could expand the number of precision weapons available to a firing battery. The missile family is being fielded in subsets (increments) to allow the Army to incrementally add improved systems without replacing the entire missile.

Increment 2 targets increasing the PrSM’s targeting ability, which is necessary to address the US military’s need to engage mobile maritime and land-based threats. This is obviously related to the countries’ operations in the Indo-Pacific, where ground forces are expected to engage enemy ships, air-defence facilities, and command and control facilities at extended distances. Some technical details remain classified.

The award further indicates that the US Army aims to move from limited early production toward establishing a larger manufacturing base. Increased production capacity has become a top priority as recent conflicts have highlighted how rapidly precision-missile stockpiles can be depleted in prolonged campaigns.

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Photonic integrated circuits (PICs) use manufacturing processes developed for the semiconductor industry to miniaturize complex optical functionality onto a chip. PICs offer significant advantages over electronic ICs. Since light travels about 3x faster than electricity, PICs can transmit data with much higher throughput. Propagation losses are also typically much smaller compared to resistance losses in electronic ICs...

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Wolfspeed Inc of Durham, NC, USA — which makes silicon carbide (SiC) materials and power semiconductor devices — has announced the commercial availability of its new Premium 200mm n-type silicon carbide substrate, expanding its 200mm SiC materials portfolio with a higher-quality starting material designed to improve yield through reduced defects and greater wafer-shape stability...

Fraunhofer Institute for Applied Solid State Physics IAF of Freiburg, Germany has developed a broadband distributed amplifier monolithic microwave integrated circuit (MMIC) chip suitable for use in data centers, measurement systems and sensors. Modern data centers, high-precision measurement systems and high-resolution radar sensors rely on extremely broadband amplifier chips that feature both low noise and high output power...