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​With the rising demands of electric vehicles, researchers are continuously working in this domain to make future mobility more practical for electric vehicle (EV) users. To make future mobility more convenient, researchers have introduced an advanced all-solid-state lithium-sulfur battery. This charging solution addresses two major challenges in modern EV infrastructure: long charging periods and limited cycle life.

Many government agencies and companies across the globe are working to commercialize solid-state lithium-sulphur battery designs because they provide high energy density, better safety, reduced dependence on rare-earth metals, and long shelf-life by eliminating the shuttle effect.

Redox Mediator Improves Battery Reaction Kinetics

All-solid-state lithium-sulfur batteries are being explored as an alternative to lithium-ion batteries, offering higher specific energy and lower material cost. However, the solid-state reaction hinders the development of all-solid-state lithium-sulfur batteries due to slow reaction kinetics, which can reduce charging speed and cycling stability.

To overcome this problem, the research team designed a positive electrode with a unique nano-eutectic material of sulfur and iodine arranged in an amorphous network. The iodine serves as a redox mediator, which allows electrons to transfer easily and enhances the sulfur reactions. The electrode’s electrochemical activity is further improved by growing the material within mesoporous carbon.

In lab tests, the battery delivered 851.9 mAh (milliamp-hours per gram) of sulfur and iodine when charged at a rate of 10C, and 474.7 mAh/g at 24C. According to the researchers’ report, electrode showed 9,000 cycles over nine months at 2C and 2,800 cycles at 0.5C over 17 months. These results demonstrate promising cycling stability under the tested conditions.

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DRDO has successfully carried out a flight trial of the indigenous High-Altitude Platforms (HAPS). HAPS is a long endurance unmanned aircraft designed as an aerial platform to be used as a surveillance system in the stratosphere. The platform has been developed by ADRDE, Agra, which is an agency of the DRDO.

In the course of the experimental flight, the platform attained an altitude of about 21 kilometres above mean sea level and was maintained at a level of 20 kilometres for more than 30 minutes before being ordered to descend. The vehicle was recovered and analysed, and its flight-performance data were obtained. Instrumental and control systems onboard included an inertial measurement unit, GPS receiver, onboard cameras, and an altitude-control system. Video and other vehicle data were sent back to a ground control station during the trial.

HAPS vehicles are meant to fly at substantially higher altitudes than aircraft that are currently flying today. They may be capable of watching a large area for an extended period of time. They could eventually be used in a variety of surveillance, comms, and monitoring roles. The trial was also conducted in collaboration with the Indian Air Force, CEMILAC, the Directorate General of Civil Aviation, the Airport Authority of India, and other agencies. The flight achieved a significant milestone in the development, though tests are still needed to confirm endurance, payload capacity, and operational viability.

The post DRDO Tests Indigenous High-Altitude Platform for Long-Endurance Surveillance appeared first on ELE Times.

Lockheed Martin has announced a new and improved missile for the missile defence force known as PAC-3 Edge for the US Army Future Interceptor programme. It is aimed at enhancing military capability to protect against increasingly sophisticated missile threats such as hypersonic missiles. The PAC-3 Edge is based on technology developed for the combat-proven PAC-3 Missile Segment Enhancement (MSE), including a new seeker, enhanced flight control technology, and a Northrop Grumman-designed multi-pulse solid rocket motor.

Lockheed Martin has announced a new and improved missile for the missile defence force known as PAC-3 Edge for the US Army Future Interceptor programme. It is aimed at enhancing military capability to protect against increasingly sophisticated missile threats such as hypersonic missiles. The PAC-3 Edge is based on technology developed for the combat-proven PAC-3 Missile Segment Enhancement (MSE), including a new seeker, enhanced flight control technology, and a Northrop Grumman-designed multi-pulse solid rocket motor. defence as forces encounter a more complex array of threats. But PAC-3 Edge is still a development program rather than an operational system in the field.

Lockheed Martin said development and testing would start in 2027, and the missile would enter service in 2031. PAC-3 Edge is a prime example of how manufacturers are already moving legacy interceptor technology forward in the areas of sensors, propulsion, and flight control. Its future utility will be contingent on test results, integration, and procurement.

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US-based defence technology firm Anduril Industrial has announced its new family of missiles, Steelfin, a high-speed, configurable surface-to-air missile developed to counter a variety of aerial threats, such as hypersonic vehicles, cruise missiles, and ballistic missiles. The system employs a common two-stage design. Its first-stage booster can be tailored to vary range, performance, and launch parameters. Its second-stage interceptor consists of a common baseline airframe, avionics, software, and flight-control architecture for each variant.

The modular design aims to lessen the incidence of having to redesign the whole missile in the event of a change of operational requirement. Identical parts and production methods could be used to help bring about efficiencies in the manufacturing process and help to achieve economies of scale. Anduril says Steelfin is capable of being integrated with existing land- and sea-based launch infrastructure, such as the Mk 41 Vertical Launch System, and interoperates with current battle-management systems. Ballistic testing with surrogate air vehicles has been conducted, and flight tests will start in 2027.

The move also comes as the armed forces search for cheaper counter-drone tactics to deal with swarms of enemy aircraft that don’t max out the available expensive interceptors. Layered air defence, defensive and offensive protection of the armed forces and the military facilities, ships from the attack of various missile-type ballistics. Steelfin embodies the trend towards modular missile architectures and scalable defence manufacturing. Its actual ability, cost, and effectiveness will have to be proved through additional trials.

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India’s Defence Research and Development Organisation (DRDO) has demonstrated the capacity of a Quantum Key Distribution (QKD) platform on the live network of Proof and Experimental Establishment at Chandipur, Odisha. The trial is aimed at developing cutting-edge technology to safeguard high-value information from growing cyber threats.

Quantum Key Distribution (QKD) uses properties of quantum physics to generate encryption keys. QKD can involve the use of physical objects, such as photons, which have the ability to detect some form of tampering when quantum signals are used to distribute those keys. It has the potential to be part of a high-security communications network.

In the trial, the platform was launched on a live network in a defence test-range environment. The trial was important because a real operational network faced a number of practical issues such as equipment integration, transmission conditions and communication reliability. QKD does not itself encrypt all transmitted information. It enables the creation of secure keys with which to encrypt data, provided that suitable encryption systems are used. In addition, secure end points, management, authentication, and measures to prevent attacks on the system are needed.

Use Cases: Strategic military command network and communications, strategic military research establishments, and other facilities of strategic importance.

The successful demonstration has created more interest in quantum-secured communications in India. Additional testing and integration of the systems will be necessary to ascertain the role this technology will play in defence networks.

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India’s Ministry of Defence has signed agreements worth nearly Rs 4,106 crore to procure a ‘Made-in-India’ communication satellite for the Indian Air Force (IAF) and heavyweight torpedoes, named Varunastra, for the Indian Navy. The deals bolster India’s defence strength in space and underwater combat.

The GSAT-7C contract of Rs 2,563 crore was signed with New Space India Limited (NSIL). This satellite shall be designed, developed, and manufactured in India and would enable the IAF to have a secure, resilient, and seamless communication network. Reliable Satellite Communications are critical for coordination of aircraft, ground stations, and operational assets over scattered areas.

The second contract, valued at Rs 1,543 crore, was granted to Bharat Dynamics Limited (BDL) for Varunastra heavyweight torpedoes. The Varunastra is a domestically produced ship-launched anti-submarine missile with high manoeuvring characteristics, built by the Naval Science and Technological Laboratory (NSTL), to attack opposing submarines at great range.

They align with India’s Atmanirbhar Bharat programme to bolster the country’s defence industry and cut reliance on imports of vital military equipment. The deal points to India’s simultaneous procurement of state-of-the-art underwater wars as well as modern secure military communications. How effective they are commercially will depend on the execution, integration, and delivery dates.

The post India Signs Rs 4,106 Crore Defence Contracts for GSAT-7C Satellite and Varunastra Torpedoes appeared first on ELE Times.

Keysight Technologies, today announced two new 1.6T Ethernet test platforms, Switch and Edge Router Tester (SERT) 1600GE and AresONE Plus 1600GE, designed to help customers validate next-generation AI data center and hyperscale networking infrastructure. AresONE Plus 1600GE sets a new benchmark by delivering eight 1.6T Ethernet ports in a single 2U appliance while providing stateful, realistic AI workload generation with mix-of-experts emulation.

SERT 1600GE targets data center switch fabric and edge router validation, while AresONE Plus 1600GE adds AI workload emulation and high-density switch fabric testing. The combined platforms provide a consistent test foundation for device qualification, routing, and AI fabric validation. They also enable performance, interoperability, and control-plane evaluation as networks scale.

Key capabilities include:

• AresONE Plus 1600GE for testing high-density switching: Packs eight OSFP1600 ports into a single 2U chassis, delivering 12.8T of line-rate traffic at 64 bytes. It supports 1600GE PAM4 signaling over 224G SerDes with backward compatibility to 112G, plus flexible port breakout of 1x1600GE, 2x800GE, 4x400GE, or 8x200GE.
• SERT 1600GE for switch and edge router validation: Available in eight-port 2U configuration for switch fabric scale testing. In common with the AresONE Plus 1600GE platform, it is capable of being time synchronized using Precision Time Protocol (PTP), for larger topologies, offering flexibility to scale test environments as network configurations grow.
• Protocol and control-plane validation: Both platforms support Border Gateway Protocol (BGP), Equal-Cost Multipath (ECMP), Virtual Extensible LAN (VXLAN), and SONiC validation across routing, bridging, and access use cases. AresONE Plus 1600GE also provides core routing scale for control-plane testing.
• AI workload emulation: AresONE Plus 1600GE integrates with Keysight AI Data Centre Builder software for mix-of experts emulation, RoCEv2, Priority Flow Control (PFC), Explicit Congestion Notification (ECN), and Ultra Ethernet Consortium (UEC) support. These capabilities let customers exercise both network protocols and AI traffic behavior in the same validation environment to identify performance and congestion issues before deployment.
• Optics and test flexibility: Both platforms support DAC, ACC, AEC, AOC, and coherent optics in both IHS and RHS form factors. AresONE Plus 1600GE can dynamically switch between an eight-port mode for data centre switch qualification and a four-port mode for AI benchmarking on the same chassis, helping teams use one appliance across multiple test scenarios and gain more value from their test infrastructure.

NVIDIA Spectrum-6 Ethernet Switch is setting the foundation for next-generation AI Ethernet fabrics with unprecedented bandwidth, scale, and AI-optimized networking. Through collaboration with NVIDIA, Keysight AresONE Plus 1600GE provides the high-performance validation platform needed to stress these capabilities with 1.6T/800GE traffic throughput, 224G SerDes, routing-scale validation, and realistic AI workload emulation, enabling rigorous performance and congestion testing before deployment.

Gilad Shainer, Senior Vice President of Networking, NVIDIA said: “AI factories require an Ethernet fabric designed for accelerated computing, and NVIDIA Spectrum-X provides the performance, predictability and control needed to keep large-scale AI workloads running efficiently. Keysight’s validation capabilities help engineering teams emulate realistic AI traffic and test Spectrum-X-based fabrics before deployment, reducing time to market.”

Ram Periakaruppan, Vice President and General Manager, Network Test & Security Solutions, Keysight, said: “The AI era breaks the rules for hyperscale infrastructure. We have moved beyond fault-tolerant commodity scaling to highly synchronized, specialized AI clusters where every packet, link, node, and nanosecond counts. As engineering teams and operators race to upgrade AI infrastructure to 1.6T Ethernet, they need to emulate the broader AI system throughout the development process—from early design and device qualification to system-level validation and AI rack deployment. These new platforms give our customers the flexibility to test at scale while using the same test foundation across the entire design-to-deployment continuum.”

The post Keysight Expands 1.6T Ethernet Validation Across Edge Routing, High-Density Switching, and AI Workload Emulation appeared first on ELE Times.

Infineon Technologies AG announced today that it is expanding its PSOCTM Control family with the launch of the PSOC Control C3 Main Line PSC3M/P6 microcontrollers (MCUs). The new, versatile, and cost-optimized MCUs combine real time motor and power control performance, with advanced security features. The features efficiently drive up to four brushless DC motors in censored or sensor less configuration with a single MCU, power topologies and security needs for a variety of applications including industrial drives, drones, smart home, home appliances, renewables, robotics, telecommunication servers, data centres, and digital healthcare applications.

The MCUs are compliant with post-quantum cryptography (PQC) requirements for firmware protection outlined in the Commercial National Security Algorithm (CNSA) Suite 2.0, and they support PSA (Platform Security Architecture) Level 3 enablement. By supporting both standards, Infineon’s PSOC Control Main Line PSC3M/P6 MCUs meet security needs for a wide range of industrial applications and ease their transition to increased security in the PQC era while allowing compliance with Cyber Resilience Act (CRA).

“These next-generation MCUs are designed for multi-motor control and power conversion systems that require high performance, efficiency and advanced security features,” says Steve Tateosian, SVP and General Manager, IoT, Consumer and Industrial MCUs, Infineon Technologies. “As industrial applications increasingly demand faster control loops for tighter control and improved efficiency, the PSC3M/P6 MCUs give customers another option to help meet their motor, power and general-purpose design needs without increasing their footprint.”

Key features and benefits

• Arm Cortex -M33-based MCU with up to 180 MHz.
• Enables high-performance systems to respond to real-time events with quad-motor control, PFC and very high RPM motor control systems.
• Wide-bandgap-ready with fast, precise analog processing and digital control to improve control loop accuracy and system efficiency.
• Provides a high level of functional integration for power supply units with advanced security to enable compliance with the latest standards.
• Scalable and compatible portfolio in features, packages, pinouts, memory, software and performance.
• Up to PSA L3 / EPC3 security and “DICE ready” including PQC support.
• Additional analog and digital features such as on-chip OpAmps, along with USB and I3C interfaces, expand the suitability of this MCU in markets beyond motor and power systems.
• Quicker time-to-market with ModusToolboxTM Power Suite and Motor Suite GUI as unified and comprehensive software and ecosystem platform for developers with dedicated tools and advanced libraries including ModusToolbox AI Assistant for seamless migration from other solutions to PSOC Control products.

The post Infineon Expands PSOCTM Control C3 family With PSC3M/P6 Featuring Advanced Security for Multi-Motor Control and Power Conversion Systems appeared first on ELE Times.

A maker designed a custom chip, had it manufactured, and the chip works. Zachary Tong described a processor based on TTA (transport triggered architecture), took it to a foundry through wafer.space and demonstrated the result on a breadboard with a Raspberry Pi Pico and a row of LEDs. Until recently an experiment like this was not economically within reach of an individual: today wafer.space’s 1 x 1 slot measures 3.93 x 5.12 mm and costs 8,000 dollars, while each die produced costs 7 dollars.

The starting point is describing the circuits with Spade, a hardware description language with modern features. From there you move on to physical design, a step comparable to the jump from a schematic to a PCB layout. At this stage packaging and the physics of electron flow matter a great deal, because the real behaviour of silicon does not match what you write in code.

From the GDS file to the die: how production works

The result of physical design is a GDS (graphic design system) file, which is used for the actual production. wafer.space collects the order together with those of other projects and sends it to the foundry: the dies come back after a few months. The process used is GF180MCU at 180 nm, so a mature, well-established technology, not an advanced node.

There is, however, a detail that anyone wanting to repeat the experience has to take into account. wafer.space does not verify the functionality of the project: whether the design works is a matter of luck. On top of that, the service can mount the dies in usable COB (chip-on-board) packages, so the chip can really be connected to something. In Tong’s case luck helped, because the custom chip worked on the first attempt.

The LEDs on the breadboard show the processor’s registers

The final demonstration sits on a breadboard, with a Raspberry Pi Pico alongside and a row of LEDs as the interface. The LEDs indicate the values in the processor’s registers and show their patterns: it is the most direct way to see that the die does what it was supposed to do. Instead of a screen or a serial port, Tong chose the light of the diodes, which makes the chip’s behaviour immediately visible.

• Spade, the hardware description language used to describe the circuits
• The GDS file, that is, the result of physical design ready for the foundry
• wafer.space, which collects the orders and sends them into production
• The GF180MCU process at 180 nm
• The COB package, with which wafer.space can mount the dies
• The Raspberry Pi Pico and the LEDs for the breadboard demonstration

Anyone who wants to follow the same path must be prepared for a long journey. First you learn to describe the hardware, then you tackle physical design, and finally you wait for the dies to come back from the foundry. Zachary Tong’s video tells this experience from start to finish, including the less visible steps such as packaging and the physics of electron flow. For anyone who wants to understand what it really takes to bring a project from code to silicon, Zachary Tong’s video is the right starting point.

For those who would rather start from something ready-made, the catalogue offers a few useful boards. The ESP12-based development board with USB, Wi-Fi and mikroBus and Grove slots is programmable with the Arduino IDE, Micropython or Javascript, so it lends itself to supporting a prototyping project. Anyone looking instead for a more powerful platform to drive the test logic can look at the fifth generation of the Raspberry Foundation board with a quad-core Broadcom BCM2712 processor at 2.4 GHz, which in Tong’s case is replaced by the Pico but remains a valid base for similar experiments.

Source: https://youtu.be/q6ytRHaTEXI?si=YCg0uiZVsvDys965

Related products

• GANIMEDE.E12 ESP12 Board with USB, Wi-Fi, mikroBus and Grove Sockets
• Raspberry Pi 5 – 2 GB memory version

The post A Custom Chip on a Breadboard: Zachary Tong’s TTA Processor appeared first on Open Electronics.

Visium of West Palm Beach, FL, USA has joined the Florida Semiconductor Institute (FSI) at the University of Florida as an Industry Affiliate, connecting the company with Florida’s growing network of semiconductor innovators, researchers, and industry leaders...

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Voicebox FX is a gadget that records and plays back sounds, with a set of effects selected through physical inputs. It is not a toy: it is a reference project for I2S audio in CircuitPython, aimed at anyone who wants to understand how digital audio moves across a microcontroller. The board driving it is an RP2350, the Raspberry Pi chip that debuted with the Pico 2.

The flow is simple: an I2S microphone captures the sound, the RP2350 records and processes it, and an I2S amplifier plays it back. The effects, such as reverb or pitch shifts, are triggered from the physical controls on the case. Everything is enclosed in a 3D-printed box, so the project can be replicated with a printer and a soldering iron.

The circuit: microphone, amplifier and RP2350

The audio section relies on two I2S modules: a microphone for the input and an amplifier for the output. The I2S bus is the standard protocol for digital audio between chips, and here it handles both directions. The RP2350 acts as the brain: it reads the data from the microphone, stores it in memory, applies the effects and sends it to the amplifier.

Choosing CircuitPython simplifies the work: no compilers or complicated toolchains, just Python scripts to load onto the board. What is more, the CircuitPython audio library exposes the I2S functions in a straightforward way. Anyone who has already used MicroPython or CircuitPython on other boards will find the code familiar.

The CircuitPython firmware and the physical inputs

The firmware handles recording, playback and the sound effects. The physical inputs, probably buttons or potentiometers, change the parameters in real time. For example, one button can start recording, another can apply an effect, and a third can play back the result. The response is immediate, because the main CircuitPython loop reads the inputs on every cycle.

For anyone who wants to rebuild the project, the page on Hackaday.io collects the code and the assembly details. The fact sheet indicates that it is a well-documented reference, so developers working on similar projects can start from here instead of starting from scratch. The files for the 3D-printed case are included, and the component list is short: an I2S microphone, an I2S amplifier and a board with an RP2350.

For the audio input side, an I2S MEMS microphone INMP441 breakout is the same type of module used in the project to capture the sound sent to the RP2350. For now Voicebox FX works standalone, with no network.

The project shows that I2S audio in CircuitPython is mature and accessible. With a few components and a bit of code you get a working gadget, which can serve as a base for vocal effects, experimental instruments or simple recorders. The 3D-printed case also makes it an object worth keeping on your desk.

Source: https://hackaday.io/contests

Related products

• I2S MEMS Microphone Breakout – INMP441

The post Voicebox FX: I2S Audio with RP2350 and CircuitPython appeared first on Open Electronics.

TrendForce’s latest report ‘2027 Infrared Sensing and Optical Communication Market Trend’ shows that rapidly growing demand for data transmission in expanding data-center networks is increasing interest in vertical-cavity surface-emitting laser (VCSEL)-based near-packaged optics (NPO). This technology is favored for its low power usage, easier maintenance, and a mature supply chain. Major companies like Lumentum, Furukawa Electric, Coherent, Broadcom, ams OSRAM, and HiSilicon are investing heavily in R&D...

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Ветеранам клубу регбі "Політехнік" присвячено Інформація КП пн, 10/19/2026 - 10:00

Spin a heavy wheel or vibrate a piece of silicon, and you get a traditional gyroscope. Spin two beams of light inside a coil of fiber, however, and you get a masterclass in relativistic physics turning into precision navigation.

Figure 1 The VG2103S series rugged single-axis fiber optic gyroscope provides accurate motion sensing under severe shock and vibration. Source: MostaTech

From the whirring bearings of mechanical gyros to the silicon pivots of MEMS, navigation has long relied on moving parts. But in the fiber optic gyroscope (FOG), it’s light itself that spins—racing through coils of glass to sense the Earth’s rotation.

The fiber optic gyroscope remains a marvel of solid‑state engineering, bridging Einstein’s relativity with modern tactical guidance. By harnessing the Sagnac effect in a coil of optical fiber, it delivers precision without moving parts, an elegant fusion of physics and practicality that continues to define high‑end navigation systems.

Core physics: Re‑introducing the Sagnac effect

Counter‑propagating beams

At the heart of the fiber optic gyroscope lies a deceptively simple idea: send two light beams in opposite directions through a long coil of fiber. If the coil is stationary, the beams return in perfect synchrony. But when the coil rotates, one beam travels a slightly longer path while the other travels a shorter one, creating a measurable difference.

Rotation and phase shift

That difference is tied directly to the rotation rate, Ω. The result is a phase shift, ΔΦs, between the counter‑propagating beams. In essence, the gyroscope translates angular velocity into an optical interference pattern—a bridge between motion and light.

Engineering reality check

On paper, the equations look straightforward. In practice, the challenge is immense: engineers must detect phase shifts on the order of microradians. That’s where the true marvel begins—not in the physics itself, but in the precision engineering that makes such delicate measurements reliable in real‑world navigation systems.

Anatomy of a FOG: The key components

The light source

At the front end sits the superluminescent diode (SLED). Unlike a narrow‑line laser, the SLED provides broad spectral output that suppresses coherence noise. This choice minimizes Rayleigh scattering and back‑reflection artifacts, ensuring the gyroscope’s signal remains clean enough to resolve microradian phase shifts.

Figure 2 Superluminescent diodes provide the low coherence and high brightness required for high-performance fiber optic gyroscopes (FOGs). Source: AeroDiode

The fiber coil

The coil is the heart of the sensor. Engineers rely on polarization‑maintaining (PM) fiber to keep the light’s polarization stable as it races through kilometers of glass. Without PM fiber, environmental stress—temperature gradients, vibration, or bending—would scramble the polarization state and corrupt the phase data. The coil’s stability is what makes the Sagnac effect measurable in practice.

The phase modulator

To translate tiny phase differences into usable signals, the system employs integrated modulators, often lithium niobate (LiNbO3) devices driven by precision op‑amps. By biasing the interference pattern, the modulator shifts the signal into a measurable regime, allowing the electronics to lock onto rotation‑induced phase shifts with high fidelity.

From open‑loop to closed‑loop: The engineering polish

The limitation

An open‑loop fiber optic gyroscope is conceptually straightforward: measure the interference pattern directly and infer rotation from the phase shift. But this simplicity comes at a cost. Scale‑factor drift creeps in over time, and the dynamic range is limited; as a result, large rotations push the system out of its linear regime, degrading accuracy.

The solution

Closed‑loop architecture solves these shortcomings with elegance. Instead of letting the Sagnac phase accumulate unchecked, the system applies a digital phase ramp that continually cancels the shift. By driving the interferometer back to its null point, the feedback loop keeps the output linear, stable, and immune to drift. The measured rotation rate is then encoded in the feedback signal itself—a clever inversion that transforms fragility into robustness.

Yet even feedback isn’t the whole story; thermal and mechanical realities still test the limits of precision.

Thermal and mechanical dynamics: Shupe effect vs. mechanical dither

Beyond optical stability, real-world gyroscopes must withstand environmental and physical constraints that threaten measurement accuracy. In fiber optic gyroscopes, asymmetric temperature gradients across the coil cause localized thermal expansion and refractive index shifts—an error known as the Shupe Effect that generates false rotation signals.

To eliminate this without moving parts, engineers utilize quadrupolar winding patterns, placing symmetrical sections of fiber side-by-side, so counter-propagating light beams experience identical thermal fluctuations.

By contrast, ring laser gyroscopes (RLGs), another class of optical gyros, face a mechanical challenge called lock-in, where backscattering from internal mirrors causes counter-propagating laser beams to synchronize at low rotation rates, creating a dead zone.

To bypass lock-in, RLGs rely on piezo-driven motors to mechanically “dither” (vibrate) the gyro thousands of times per second. While effective, this mechanical movement introduces wear, acoustic noise, and complexity—highlighting the key advantage of the FOG’s purely solid-state design.

FOG vs. the world: MEMS and RLGs

Gyroscopes come in three dominant flavors, each tuned to a different mission profile. MEMS gyros are the cheapest and most compact, finding their way into smartphones, drones, and consumer gadgets. Their bias stability is modest, and while they’re perfect for short‑term orientation, they drift too quickly for long‑duration navigation.

Fiber optic gyros or FOGs occupy the middle ground. They cost more than MEMS but deliver far higher stability and an extraordinary lifespan, thanks to their solid‑state design with no moving parts or gas reservoirs to degrade. This makes them ideal for tactical missiles, subsea navigation, and autonomous vehicles where reliability and precision matter more than price.

At the high end sit ring laser gyros or RLGs. They achieve ultra‑high stability, rivaling the best FOGs, but at a steep cost. Their reliance on helium‑neon gas means eventual degradation, yet they remain the gold standard for submarines and commercial aircraft, where absolute precision justifies the expense.

Figure 3 Honeywell GG1320 ring laser gyro delivers precise rotation sensing, enabling navigation and stabilizing aerospace, marine, and defense platforms. Source: Honeywell Aerospace

Variants of the fiber optic gyroscope

From the classic interferometric FOG (IFOG) to newer digital FOGs (DFOGs) and integrated gyroscope systems (IGS), the architecture has steadily evolved while retaining the same Sagnac foundation.

The IFOG remains the workhorse, using long coils of polarization‑maintaining (PM) fiber to preserve phase integrity and deliver tactical‑grade accuracy. DFOGs build on this by embedding digital feedback and advanced signal processing, often with quadrupolar winding patterns of PM fiber to suppress thermal drift, extending dynamic range and robustness. Resonant and hybrid designs push sensitivity further, employing ultra‑low‑loss PM fiber loops or specialty coated fibers, though they demand complex stabilization.

Meanwhile, integrated gyroscope systems and chip‑scale photonic FOGs are beginning to replace kilometers of fiber with silicon photonic waveguides, aiming to replicate PM fiber performance in miniature. Across all these variants, the choice of fiber is decisive: single‑mode fiber may suffice for low‑cost experiments, but only polarization‑maintaining fiber—and its emerging photonic equivalents—ensures the stability needed for navigation‑grade gyroscopes.

Performance metrics and outputs

Fiber optic gyroscopes are defined by their precision metrics. Angular random walk (ARW) sets the short‑term noise floor, and FOGs achieve values far lower than MEMS, translating into smoother orientation data. Bias stability—the long‑term drift of the zero point—remains their hallmark, often holding steady for years without recalibration. Their solid‑state design makes them inherently shock‑ and vibration‑proof, with no moving parts to resonate or wear.

Input range spans from ultra‑low rotation rates to thousands of degrees per second, while bandwidth supports rapid maneuvers without lag. Magnetic response is negligible compared to MEMS, since light rather than moving charges carries the signal.

Start‑up time is typically short, with modern digital FOGs locking in within seconds. On the output side, legacy analog formats provide voltage‑scaled signals, while digital FOGs deliver direct digital outputs, ensuring seamless integration with navigation computers and minimizing conversion errors.

Output conventions

Beyond raw analog and digital rate formats, commercial FOGs often provide standardized outputs such as CLOCK OUT and DELTA OUT. CLOCK OUT serves as a timing reference, aligning the gyro’s data stream with system processors, while DELTA OUT delivers the incremental angle (Δθ) per sampling interval. These conventions simplify integration into inertial navigation systems, where synchronized timing and accumulated angle increments are essential for accurate position and attitude computation.

Commercial coil configurations

In commercial interferometric FOGs, the fiber coil is engineered with meticulous care, since its geometry directly governs thermal stability and bias drift. Wet coils embed the fiber in resin or epoxy, damping vibration and stabilizing temperature, while dry coils leave the fiber free‑wound with mechanical cushioning, allowing natural expansion but demanding tighter control of stress.

Winding patterns are equally decisive: the original quadrupole winding cancels first‑order thermal gradients by alternating coil segments, while the modified quadrupole refines this symmetry to suppress residual Shupe errors. More advanced schemes such as time‑delay fiber (TDF) winding distribute the optical path to average out environmental fluctuations, further reducing bias instability.

Octupolar and higher‑order windings extend these principles, trading complexity for incremental gains in stability. Together, the choice of wet vs. dry construction and the winding geometry transforms a simple fiber coil into a rugged, navigation‑grade sensor core.

Coil mounting styles

Beyond wet and dry construction, fiber coils are packaged in different mechanical styles. Flanged coils can be built wet or dry, clamped between rigid end plates for stability. Hubbed coils are wound around a central hub and are typically resin‑embedded (wet only) to lock the fiber in place.

Freestanding coils dispense with rigid supports, relying on resin encapsulation (wet only) to maintain geometry. These mounting choices balance mechanical ruggedness, thermal expansion control, and ease of integration into navigation‑grade assemblies.

Figure 4 Standard freestanding fiber gyro coils showcase the physical construction and reel structure used in closed-loop FOG systems. Source: Yoec

Axis configurations and INS integration

Commercial FOGs are offered in single‑axis modules for specialized sensing, or multi‑axis assemblies—typically three orthogonal coils—to deliver full 3D rotation data. These triads form the angular‑rate backbone of an inertial navigation system (INS), where FOGs are paired with accelerometers to compute position and altitude without GPS.

Single‑axis FOGs find use in stabilization platforms and precision pointing, while double‑ and triple‑axis units dominate navigation, guidance, and autonomous vehicle control. The modularity of coil design allows vendors to scale from compact one‑axis sensors to rugged INS‑grade packages, ensuring that the same interferometric principle can serve both niche instrumentation and mission‑critical navigation.

Non‑ITAR FOGs

Vendors often distinguish between ITAR‑restricted gyroscopes and non‑ITAR models. International Traffic in Arms Regulations (ITAR) governs military‑grade hardware and technical data, limiting export and use.

By contrast, non‑ITAR FOGs are commercial versions cleared for civilian applications—aviation, marine navigation, robotics, and autonomous vehicles—without the licensing hurdles. They still deliver navigation‑grade performance, but are designed for open markets where accessibility and integration matter more than classified specifications.

Deployment and future directions

Fiber optic gyroscopes have already proven themselves in submarines, tactical missiles, aircraft, and autonomous vehicles—anywhere long‑term stability and ruggedness matter more than cost. Their mean time between failures often exceeds decades, a testament to solid‑state reliability.

While FOGs occupy the mid‑tier between low‑cost MEMS and high‑end RLGs, research is pushing further: silicon photonics promises chip‑scale integration, and quantum gyroscopes based on cold atoms may one day bypass optical fibers altogether. Together, these paths suggest that navigation without GPS will only grow more precise and more accessible.

The elegance of the fiber optic gyroscope lies not only in the Sagnac physics but in the way engineers tame optical noise, stabilized polarization, and perfected feedback loops to build a sensor with zero moving parts. What results is a navigation instrument immune to wear, capable of microradian precision trusted in the harshest tactical environments.

Looking forward, the same principles are migrating into silicon photonics. Chip‑scale integrated optics promise to deliver FOG‑like precision in miniature packages, opening the door to navigation systems that are lighter, cheaper, and more ubiquitous. The journey from spinning bearings to spinning light may soon culminate in spinning photons on a chip—bringing Einstein’s relativity into everyday devices.

For makers, engineers, and serious tinkerers, the challenge is clear: don’t just admire the elegance—experiment with it. Build your own interferometer, wrestle with coherence noise, and see how far you can push solid‑state precision. The fiber optic gyroscope is more than a marvel; it’s an open invitation to innovate.

T. K. Hareendran is a self-taught electronics enthusiast with a strong passion for innovative circuit design and hands-on technology. He develops both experimental and practical electronic projects, documenting and sharing his work to support fellow tinkerers and learners. Beyond the workbench, he dedicates time to technical writing and hardware evaluations to contribute meaningfully to the maker community.

Related Content

• Modeling the MEMS gyroscope
• Gyroscope Accuracy Beats MEMS
• InvenSense spins first pitch-and-yaw MEMS gyro
• CEA-Leti’s NEMS-Based Gyroscope Operates at 50 kHz
• BAW gyroscope sensors transform inertial MEMS apps

The post Fiber optic gyroscopes: Elegant engineering of modern inertial navigation appeared first on EDN.

An ESP32 can do far more than handle sensors and Wi-Fi. This project by M Mohammed Shaheen K S turns it into a complete video player: it reads a Motion JPEG file from a microSD card and plays it back on a 2.4-inch TFT display. The result is a compact device that shows custom animations or dynamic UI elements, pushing the board’s performance to its limit.

The heart of the system is the MJPEG format, a sequence of individual JPEG images. The microSD card stores the video as an .mjpeg file. The ESP32 reads the raw file stream over the SPI bus, with no need for complex codecs or extra hardware.

Reading data and buffering in RAM

The file is read in 4 KB blocks into RAM. This choice avoids delays caused by continuous access to the card. The system looks for the JPEG frame start and end markers, so it can assemble the complete images in memory ready for decoding.

The frame buffer is 80 KB, a size that balances available memory against playback smoothness. The JPEGDEC library decompresses each JPEG image directly in memory, converting the data into 16-bit RGB565 pixels. This is the display’s native format, so no further processing is needed.

TFT display and frame rate

The 2.4-inch TFT display with 240×320 resolution uses the ILI9341 controller. Pixel data arrives over a high-speed SPI bus. The display’s SPI frequency is 27 MHz, while the maximum supported speed reaches 40 MHz. This difference ensures stable transmission without errors.

Playback targets 15 FPS. The interval between one frame and the next is 1000/15 milliseconds, about 66 ms. Small delays between updates keep the stream steady, avoiding tearing or freezes. Video quality is average, suitable for simple content and animated interfaces.

Rebuilding the project takes only a few components: an ESP32 Dev Module, a 2.4-inch SPI TFT display (model TJCTM24024-SPI) and a microSD card. The wiring uses the SPI bus for both the SD card and the display. The source code, available in the project repository, includes all the necessary libraries: SPI.h, SD.h, Adafruit_GFX.h, Adafruit_ILI9341.h and JPEGDEC.h.

Before loading the video onto the microSD card, it must be converted into the right format. The resolution must be 320×240 pixels and the file must be saved as .mjpeg. M Mohammed Shaheen K S’s repository contains the complete code and the instructions for the conversion, so you end up with a file that is ready to use.

The project shows how an ESP32 can handle lightweight video streams with few external components. Possible uses range from custom animations to information panels, and even small retro games.

Source: https://circuitdigest.com/articles/esp32-video-player-tutorial

The post MJPEG Video Player on ESP32 with a TFT Display appeared first on Open Electronics.

The 0.96-inch 128×64 OLED display is a compact module widely used in electronics projects. It uses the SSD1306 driver and communicates over I2C, so it connects to Arduino, ESP8266 and ESP32 with just a few wires. It shows text, sensor data, symbols and graphics. AdriRobot tested it with an Arduino UNO and with an ESP32-C3 SuperMini.

128×64 OLED display: technology and colours

OLED stands for Organic Light Emitting Diode. Each pixel emits its own light, so contrast is high and no backlight is needed. Power consumption is lower than that of a backlit LCD, and readability stays good both in the dark and in bright light. The module comes with white, blue or yellow pixels, or in a two-colour version with a yellow top strip and the rest in blue.

• 0.96-inch size, 128 × 64 pixel resolution, SSD1306 driver;
• supply from 3.3 to 5 V, 0.06 W consumption in normal display mode;
• viewing angle greater than 160°;
• operating temperature from -30 to +70 °C;
• glass screen, lifetime of at least 16,000 hours;
• module dimensions: 29.28 × 27.1 mm.

Pins, I2C address and power supply

The connector has four pins: VCC (3.3-5 V), GND, SCL and SDA. The reset circuit is on board, so no extra pin is needed. On the Arduino UNO the I2C pins are A5 for SCL and A4 for SDA, on the Mega they are 21 and 20.

Watch out for the two power pins, because on some modules their order is reversed. Displays marked JMDO.96C.1 let you choose: two pads on the PCB, shorted with 0 Ω SMD resistors or with a blob of solder, swap the two pins. Before connecting, it is therefore worth checking the silkscreen.

The I2C address is 0x3C, the same as other SSD1306 displays, and it cannot be changed. If other peripherals with that address are on the bus, another solution is needed.

Test with Arduino UNO

For the test, the display is mounted on a small breadboard and connected to an Arduino UNO. First you read the address with the i2c_scanner sketch (File, Examples, Wire): if nothing shows up, try swapping the SDA and SCL wires. Then install the Adafruit SSD1306 library from the Library Manager, accepting the Adafruit GFX dependency as well with Install all.

The test sketch then fills the screen, draws a pixel in each corner and writes a few lines of text. On the two-colour model, in fact, the first line comes out yellow because it sits in the top strip.

Test with ESP32-C3 SuperMini

With the ESP32-C3 SuperMini the display uses 3.3 V, GND, GPIO9 as SCL and GPIO8 as SDA. In the IDE you select ESP32C3 Dev Module and enable USB CDC On Boot and Erase All Flash Before Sketch Upload, as in the other tests. Finally the sketch initialises I2C on pins 8 and 9, starts the display at address 0x3C and writes a few lines of text.

AdriRobot also used it on a board with an ESP8266 12F, to show temperature and humidity from a DHT11, and on a shield with a DFPlayer Mini, to print messages. The white-pixel model is available as a 0.96-inch I2C OLED display.

Source: AdriRobot’s original article includes the circuit diagram, the downloadable sketches and the test video.

Related products

• Mini ESP32-C3 module
• OLED Display I2C 0.96” – VCC/GND/SCL/SDA

The post 0.96-inch 128×64 OLED Display: SSD1306 and I2C appeared first on Open Electronics.