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The Design, Automation & Test in Europe (DATE) Conference in Verona in April showed an EDA research community moving with real momentum into the AI era. The strongest signal from the conference was that AI is no longer a separate topic sitting beside chip design. It’s now shaping the workloads, architectures, design tools, verification flows, and security questions that will define the next phase of semiconductor development.

The conference was upbeat because the direction is clear and the opportunity is substantial. Heterogeneous compute, RISC-V, chiplets, AI accelerators, agentic EDA, structured specifications, and AI-assisted verification are all advancing at the same time. The challenge is significant: these systems must be designed, verified, secured, and trusted.

However, DATE 2026 showed that the research community is already developing the methods, tools, and flows needed to address that challenge. For Europe, the opportunity is not simply to catch up with existing EDA capability, but to help lead the next wave of AI-enabled, verification-aware, and trustworthy semiconductor design.

This also re-frames the European sovereignty discussion. There are three distinct parts: sovereignty in processor design, sovereignty in EDA tools, and sovereignty in next-generation AI+EDA capability. Processor design is being opened up by RISC-V, chiplets and design-enablement platforms.

EDA-tool sovereignty is more challenging, because advanced-node signoff depends on mature commercial tools, process design kits (PDKs), verification IP, and foundry-qualified flows. The strongest near-term opportunity is therefore AI+EDA capability: building the methods, benchmarks, structured specifications, secure deployment models, and verification-aware AI flows that will define the next generation of design automation.

Conference context and program messaging

DATE 2026 provided a useful view of where semiconductor research is moving as AI, EDA, advanced architectures, verification, and security begin to converge. DATE is not the Design and Verification Conference (DVCon), with its practitioner focus on verification methodology and commercial tool use. It is not the Design Automation Conference (DAC), where the exhibition floor is often as important as the technical program. DATE is research-led, with the papers, focus sessions, tutorials, keynotes, and European project sessions forming the center of gravity.

That research-led character matters. It makes DATE a good indicator of topics that are still forming before they become mature tool flows or standard industry practice. The commercial ecosystem was clearly present with Cadence, Synopsys, Qualcomm, Arm, Infineon, Micron, STMicroelectronics, Tenstorrent, Axelera AI, Real Intent, and others represented in the sponsor list. However, the tone was less product marketing and more ecosystem development.

A key takeaway was that AI is now present as a workload, a design objective, a design-assistance technology, a verification challenge, and a security risk. The individual sessions differed in emphasis, but the common thread was the same: the next phase of EDA will be shaped by the interaction between AI, heterogeneous architectures, verification, security, and trust.

DATE 2026 included 325 regular papers and 91 extended abstracts across the D, A, T, and E research tracks, giving 416 accepted research-track outputs. The program offered 41 main technical sessions, three Best Paper Award candidate sessions, two late-breaking-result sessions, five keynotes, 10 focus sessions, five workshops, four special-day sessions, and four embedded tutorials.

The geographical distribution was also significant. DATE is European in location and culture, but the research paper base reflects the global semiconductor research map. By country-affiliated appearances in technical paper-like entries, China, plus Hong Kong and Taiwan, accounted for 247 appearances, or 44.7%. Europe, plus the U.K., accounted for 133 appearances, or 24.1%. The U.S. accounted for 94 appearances, or 17.0%, with the rest of the world at 79 appearances, or 14.2%.

Using a broad classification, roughly 27% of the technical country-affiliated appearances had some AI connection. Most of this was hardware-for-AI: accelerators, compute-in-memory, large language model (LLM) inference, edge AI, photonic AI, and memory systems. AI applied directly to verification, test generation, fuzzing, coverage, and security validation was closer to 2.7% of the technical program. This shows that AI-for-verification is currently a specialist part of the larger AI-related research activity.

AI as workload, tool, and risk

The opening keynote from Luc Van de Hove of IMEC set out one of the central pressures: AI models are evolving faster than semiconductor hardware development, creating bottlenecks that require new compute architectures and semiconductor platforms. In this framing, AI is a key demand changing the hardware stack.

At DATE, AI appeared in at least four roles. First, AI is the workload driving accelerators, compute-in-memory structures, chiplets, photonics, and energy-efficient platforms. Focus session FS02, “Architecting Intelligence: Next-Gen Acceleration for Generative AI,” and TS36, “Next-Generation Memory Systems for AI Acceleration,” were good examples. Second, AI is becoming a design tool, with LLMs, agents, and machine-learning-driven optimization applied to routing, placement, high-level synthesis (HLS), analog sizing, and lithography simulation.

Third, AI is changing the research process itself, as raised in the keynote from Rolf Drechsler from the University of Bremen in Germany. Fourth, AI is becoming a security and trust problem, since AI-guided verification tools can introduce risks such as adversarial manipulation, biased test generation, or hallucinated security guidance.

The AI-for-EDA message was therefore not simply that AI will automate design. AI can accelerate parts of the design and verification flow, while also creating systems and flows that are harder to verify, explain, secure, and certify.

Future platforms are heterogeneous

A repeated architectural message was that general-purpose compute is no longer sufficient for many target workloads. The program included strong content on AI accelerators, chiplets, 3D integrated circuits (3DIC), RISC-V vector extensions, photonic accelerators, quantum and high-performance computing (HPC) coupling, FPGAs, high level synthesis (HLS), open chiplet ecosystems, and domain-specific processors.

RISC-V appeared prominently as an instruction set architecture (ISA), especially where openness, customization, and verification interact. It appeared in open-source cores such as Rocket, BOOM, XiangShan, and Snitch; in vector-extension verification; in processor fuzzing; in cryptographic accelerators; in SoC security; and in lightweight wearable systems. This is consistent with the broader RISC-V opportunity: the open ISA makes architectural experimentation easier but also increases the verification responsibility for each implementation and extension.

The Cornell University keynote by Zhiru Zhang on accelerator design and programming described a familiar problem. Performance and efficiency increasingly come from specialized accelerators, but there is a widening gap between how accelerators are designed and how they are programmed. That gap is an EDA problem because the design flow needs to connect architecture, programmability, verification, performance estimation, and software maintenance.

Quantum was also treated as a systems topic rather than as isolated physics. Nvidia’s Bettina Heim described NVQLink, coupling GPU real-time processing with quantum processors at sub-microsecond latency for error correction and control. A focus session covered MLIR, QIR, and intermediate representations for quantum-classical compilation. The point for EDA is that quantum-classical systems create problems in compilation, control, architecture, timing, and verification. These are recognizable EDA problems, even if the devices are different.

Verification and security become first-class constraints

The third major theme was the convergence of verification, security, and open ecosystems. DATE treated verification and security as part of the same scalability problem. As systems become heterogeneous, AI-driven, and assembled from chiplets and third-party IP, functional correctness, security validation, explainability, and certification overlap.

The verification panel (session FS06), “Who Is Best Suited to Do Verification?”, framed rising re-spin rates and verification cost as a central industry problem. The hardware security focus session argued that heterogeneous SoCs, CPUs, and accelerators create attack surfaces too large for manual analysis alone. The AI-for-verification thread included coverage-driven test generation, reinforcement-learning-guided concolic (concrete + symbolic) testing, processor fuzzing, SystemVerilog Assertion (SVA) generation, and agentic security assistants.

This work is still emerging. However, the direction is clear: verification needs more automation, and that automation needs to be tool-grounded, measurable, and traceable. A generated test, assertion, or security recommendation is useful only if it connects to coverage, formal results, simulation results, reviewable traces, or other engineering evidence.

AI for RTL and verification

A specialist but important cluster was AI applied to register-transfer level (RTL) design. This included LLM-generated Verilog, closed-loop RTL repair, multi-agent design flows, HLS-to-RTL pathways, and benchmark contamination. The volume was small, roughly 2-3% of the technical program, but the technical direction was important.

The field has moved beyond asking an LLM to write Verilog. The more credible flows put verification in the loop: generate RTL, run checks, estimate correctness, repair errors, and preserve equivalence. VeriBToT (session TS07.1) combined self-decoupling and self-verification for modular Verilog generation.

EstCoder (TS22.9) used a collaborative agent flow with a functional-estimation agent scoring generated RTL before accepting or correcting it, reporting up to 9% improvement in RTL correctness. LiveVerilogEval (TS29.1) addressed benchmark contamination and found that LLM performance degraded significantly on dynamically generated benchmarks, suggesting that static benchmarks may have overstated current capability.

The sponsor-hosted executive session on EDA agentic AI provided a useful industrial view. Agentic AI is moving from demonstrations toward production flows with RTL checking and fixing, specification-to-testbench construction, and synthesis-to-GDSII flows identified as near-term use cases. The hard constraints are determinism, traceability, IP protection, tool integration, and signoff confidence.

The AI-for-verification work showed the same pattern. The best examples were closed-loop and tool-grounded, not generic prompt-based test generation. ChatTest (TS22.7) used a multi-agent LLM framework with a structured Verification Description Language (VDL), retrieval-augmented generation, and a coverage-feedback loop. It reported 1.46 times higher toggle coverage, 2.28 times higher line coverage, and a 24.23% improvement in functional coverage across 20 complex RTL designs. CoverAssert (TS40.10) used functional coverage feedback to guide LLM generation of SVAs.

Processor fuzzing gave another important example. SimFuzz (TS40.6) applied similarity-guided block-level mutation to RISC-V processors Rocket, BOOM, and XiangShan, finding 17 bugs, including 14 previously unknown issues and seven CVE-assigned bugs affecting decode and memory units.

This connects to GhostWrite (CVE-2024-44067), a RISC-V vector-extension implementation bug in T-Head XuanTie processors that allowed unprivileged code to write arbitrary physical memory. GhostWrite was not a side channel. It was a direct architectural flaw, and the mitigation required disabling the vector extension. This is a strong argument for structure-aware, security-directed processor verification.

AI-generated SVAs also appeared in several forms. PALM (TS07.6) investigated LLM assistance for valid SVAs in security verification, while CoverAssert (TS40.10) and AutoAssert (TS02.5) extended coverage-driven, LLM-assisted assertion generation with formal verification feedback. This seems to be the right near-term role for AI in formal verification: assistant and accelerator, not replacement for formal reasoning.

Agentic AI and structured specifications

The most visible emerging pattern in AI+EDA was the movement from single-shot prompting to multi-agent, tool-grounded, feedback-driven workflows. The focus session (FS07) “From Concept to Silicon: End-to-End Agentic AI for Smarter Chip Design” made this explicit across HLS, physical design, testing, and security verification.

The Nexus paper presented by PrimisAI (session SD01.1) framed the engineering problem clearly. EDA workflows need reliability and traceability, and weak coordination and unstructured communication are bottlenecks for multi-agent deployment. Nexus reported 100% accuracy on RTL generation tasks in VerilogEval-Human and nearly 30% average power savings on Verilog-to-routing (VTR) timing-optimization benchmarks.

AgenticTCAD (TS41.6) applied a natural-language-driven multi-agent system to TCAD device optimization, achieving IRDS-2024 specifications for a 2-nm nanosheet FET within 4.2 hours, compared with 7.1 days for human experts.

The key point is that agentic AI wraps the LLM in an engineering process. The flow is to decompose the task, call EDA tools, inspect reports, measure quality, repair errors, and iterate. That is much more credible for EDA than single-shot generation.

Two structured-language examples were also notable. The first was the Universal Specification Format (USF), a formal specification format (in session TS24.3) with unambiguous syntax and semantics able to generate formal properties and behavioral simulation models.

The second was Verification Description Language (VDL), introduced in ChatTest (TS22.7), which captures I/O pins, timing, functional coverage targets, stimulus sequences, checkpoints, and boundary conditions in YAML format. These are early signs that AI-assisted EDA may require better intermediate representations, not only better models.

European sovereignty and the next EDA wave

European semiconductor sovereignty was an undercurrent throughout DATE 2026, but it needs to be framed carefully. Semiconductor sovereignty is not about becoming completely self-sufficient, it is about reducing dangerous dependencies on other geographic regions. There are several separate questions, for example: sovereignty in processor design, sovereignty in EDA tools, and sovereignty in next-generation AI+EDA capability.

For processor design, the RISC-V activity, open chiplet ecosystems, and European design-enablement platforms such as the cloud-based makeChip point in a useful direction. However, first-time-right silicon still depends heavily on commercial EDA tools, qualified PDKs, verified sign-off flows, and high-quality verification IP. A realistic sovereignty strategy means sovereign design competence and secure access to the best tools, not an assumption that open-source-only flows can replace the commercial stack.

For EDA-tool sovereignty, open-source EDA is strategically valuable for education, research, reproducibility, open PDKs, and lowering barriers for small and medium-sized enterprises (SMEs) and universities. However, advanced-node commercial EDA represents decades of investment in algorithms, foundry relationships, sign-off maturity, and customer regression infrastructure.

The keynote by Luca Benini of the University of Bologna in Italy on democratizing silicon made the positive case for broader access, but open-source EDA is a supplemental and educational platform, not a near-term substitute for advanced-node sign-off.

The more compelling opportunity is next-generation AI+EDA. DATE 2026 showed that this area is still being defined. Agentic workflows, AI-assisted verification, coverage-driven test generation, formal and SVA support, open benchmarks, trustworthy AI, structured specification languages, and secure on-premise model deployment are all areas where research depth and engineering discipline matter.

Europe has strong universities, safety-critical application domains, active RISC-V and open-source hardware communities, and the policy framework of the EU Chips Act. That combination is well suited to shaping the next EDA wave.

The strongest form of European sovereignty is not isolation. It is capability: the ability to design, verify, secure, and understand the systems Europe depends on. DATE 2026 showed that the future of EDA will require new compute architectures, better verification methods, more automation, structured specifications, stronger security methods, and a clear understanding of where AI helps and where it introduces new risks. These are exactly the problems that a research-led, ecosystem-focused community should be able to address.

DATE 2026 was therefore not just an EDA conference about AI in chip design. It was a useful indication that the next phase of EDA will be defined by the interaction between AI, heterogeneous architectures, verification, security, and trust. The next step is to turn these research directions into reliable engineering flows.

Simon Davidmann is an EDA industry pioneer and serial technology entrepreneur with over 40 years of experience in simulation and verification. His career has been instrumental in shaping the foundational languages and methodologies used in modern chip design, particularly those now critical for AI/ML hardware. Davidmann was the co-creator of Superlog that became SystemVerilog. After selling Imperas to Synopsys in 2023 and being Synopsys VP for Processor Modeling & Simulation, he left Synopsys and is now an AI + EDA researcher at Southampton University, UK.

Editor’s Note

DATE 2026 was held on 20-22 April 2026 in Verona, Italy. The conference program is available at https://www.date-conference.com/programme. Specific session labels are noted in parentheses in the article.

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The post The next EDA wave: Lessons from DATE 2026 appeared first on EDN.

Building on more than 30 years of collaboration, process equipment maker Applied Materials Inc of Santa Clara, CA, USA has announced a new innovation partnership with foundry Taiwan Semiconductor Manufacturing Company Ltd (TSMC) to accelerate the development and commercialization of semiconductor technologies required for the next era of AI. Working together at Applied’s EPIC Center in Silicon Valley, the companies will co-innovate to advance materials engineering, equipment innovation, and process integration technologies designed to deliver energy-efficient performance from the data center to the edge...

A subtle change to a standard circuit can enhance its usefulness—and even save a resistor.

If there were a prize for the most trivial Design Idea (DI) of the year, this one would likely be high on the shortlist (if not at the top). Most DIs involve adding components to circuits to improve them; this time we’re removing one. Circuits for line drivers, balanced or not, are ten a penny, but this variant has a surprising twist: surprising because it’s so simple and, when you look at it, obvious, though I can’t find it in any published schematic, even those from National Semiconductor’s golden days.

Wow the engineering world with your unique design: Design Ideas Submission Guide

Figure 1 presents it:

Figure 1 Resistors R1 and R2 help to set the gains of both the non-inverting and inverting stages, allowing for excellent matching of the anti-phased outputs with minimal components.

A1a is a non-inverting gain stage, utterly conventional except that its feedback network is referred to A1b’s virtual ground point. A1b is an inverting unity-gain stage, utterly conventional except that its input resistor is also A1a’s feedback network. A1a and A1b therefore work together to deliver perfectly matched anti-phase outputs (assuming perfectly matched components, of course). The gain can be set to anything above 1 (unity gain would revert the circuit to a simple buffer plus an inverting stage: nothing new).

At first glance, this circuit may look rather like part of a differential or instrumentation amplifier. But its function, as determined by the resistor ratios, is quite different. Those others have accurately-matched differential inputs; this is designed for balanced outputs.

Is that it?

Yup: ’fraid so, apart from some practical details. A CR network may be needed to remove DC from the input, and any remaining imbalance could be trimmed by bleeding some current into (or out of) the A1b in- input. Otherwise, the circuit is stable and well-behaved, and will happily drive a transformer directly, though series matching resistors should be added, perhaps with 300R in each output line if you want to be really picky about balance.

Trimming the frequency response is messy, and should be done before the signal gets this far. Any (HF-cutting) capacitor across R1 (call it C1) needs to be matched by (1 – 1 / Gain) × C1 across R3 if the responses in both output legs are to match.

The output drive differs from device to device. Using ±15 V rails and working into 600R, LM4562s delivered 26.3 V pk-pk and KA5532s gave 24.5 V, while TL072/082s disappointed at just 13.8 V. An MCP6022 (RRIO, unlike the others) with ±2.5 V supplies clipped at 4.7 V pk-pk into 600R.

And in the real world…

To paraphrase Bob Pease, “If a circuit’s never seen a soldering iron, it probably won’t work right” (although perhaps he’d make an exception for plug-in breadboards, at least at low frequencies). So, just to demonstrate that this doesn’t merely describe a simulation, Figure 2 shows it plugged in and “working right”:

Figure 2 This is how an LM4562 performs at 1 kHz with ±15 V rails and a 600R load. It is just clipping—cleanly and symmetrically—at a differential output level of 32.2 dBu.

As noted earlier, the circuit is well behaved as long as you avoid driving capacitive loads directly, as with all op-amp circuits (33–100R in series with an op-amp’s output pin is normally a good cure, limiting the peak current). Lacking any suitable audio transformers but wanting to check if such loading might cause problems, I hooked it up directly to the secondary winding of a small mains transformer, which seemed like a cruel enough (not to mention fun) test.

While the resulting >>300 V RMS output tolerated little loading, it could light a neon brightly (with its integral 220k series resistor) without affecting the distortion at the op-amps’ outputs. Although the HV output showed a nick in the waveform where the neon struck and went negative-resistance, this artifact wasn’t reflected back to the drive. Which is exactly what we’d expect, but should not take for granted.

For phase-splitting with gain (but no pain) and the ability to drive old-school 600Ω balanced lines, this circuit may be ideal. That said, there may be easier and cheaper ways of powering neons…

—Nick Cornford built his first crystal set at 10, and since then has designed professional audio equipment, many datacomm products, and technical security kit. He has at last retired. Mostly. Sort of.

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The post Well-balanced gain, driven without pain appeared first on EDN.

I'm slightly lazy; if I need to do repeated work I'd rather spend my time on building something that will do that job for me. (It's not always never faster but certainly more fun). In the last few months I went completely overboard and built something that connects to, well, pretty much everything in my workshop that communicates. I can now control my power supply, read data from a power meter, read temperatures etc, all in a single tool. It can even control my 6-axis robot arm and watch and analyse my security camera's. Using javascript, I can now run automated tests or whatever. And of course, since it is 2026, I added AI which is pretty awesome. Combined with voice recognition and text-to-speech, I can now say " Set the power supply to 15V, 100 mA, turn the output on" while holding two probes. And it actually works. (Though first attempt it mishard it as 100 mA as 100 million 💀 So I built in a confirmation step). But AI can also write scripts for you and help to write the drivers to your equipment. The camera and AI can also be used inside a script; imagine you have an old analog voltmeter and want to use the value to do something in your script: just point the camera at it and do something like let value=ai("return the value of the analog meter in Volts",camera.snapshot()); So I hope there are more fools like me who would love to play with something like this; if you want to give it a try, it's free! Though very much in Beta so I'm sure you'll find stuff I need to fix. Or stuff I need to explain better... It should be able to connect to any scpi device over serial/usb or tcp/ip. muxit.io has all the information and docs.muxit.io has even more. You'll need to run your own local llm (like ollama or lm studio) to get the AI to work for now. I used lm studio with Qwen3.5 9b, which worked perfectly for recognizing images. There will be versions in the future that have more advanced, integrated AI like claude and chatgpt but since that will cost me money I need to figure out how to get that implemented. The free version should be able to do all the cool stuff. Let me know if you have any questions! submitted by /u/lampmaker [link] [comments]

Power modules for data centers are incorporating AI inference for applications such as agentic AI, response generation with large language models (LLMs), and predictive analytics in finance and healthcare. The use of AI accelerators is mainly aimed at boosting energy efficiency in high-density boards.

Take the case of Infineon, which is incorporating d-Matrix’s Corsair inference accelerator in its OptiMOS TDM2254xx dual-phase power modules. According to Sid Sheth, founder and CEO of d-Matrix, Corsair was purpose-built for delivering the sub-2 ms token latency that interactive applications require.

The OptiMOS TDM2254xx dual-phase power module enables vertical power delivery while offering a density of 1.0 A/mm2. Source: Infineon

Infineon has been working closely with d-Matrix to optimize the Corsair inference accelerator for its power semiconductors. “Infineon has been collaborating with customers specializing in inference processors, such as d-Matrix, from the early days when the industry was mostly focused on training hardware,” said Raj Khattoi, VP and GM of consumer, computing and communication at Infineon.

Infineon, which offers a broad portfolio of power semiconductors, based on silicon (Si), silicon carbide (SiC), and gallium nitride (GaN), has also been working closely with AI companies in both the training and inference markets. And these liaisons have aimed to improve energy efficiency at higher power density in hardware at data centers and other AI installations.

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The post AI inference accelerator bolsters efficiency in power modules appeared first on EDN.

Подяка компанії VirginGrip за підтримку скеледрому КПІ kpi вт, 05/12/2026 - 09:55

I thought this recent project of mine could inspire people on how to reuse the spindle motor on obsolete or crashed hard drives. After all, it's a shame how these state-of-the-art motors often end up in the bin despite being in full working condition. I built a so-called "ringing table" for microscopy by creating a drop-in replacement for the original disk controller on a twenty year old WD drive. My board has a PIC processor, a three-phase spindle motor driver and a simple button-and-led user interface right where the SATA and Power connectors used to be. It actually worked pretty well. There must be other things one can build from this basic concept! More technical details about the project are laid out on my personal blog. https://espenandersen.no/ringing-table-from-a-dead-hard-drive/ submitted by /u/Party-Butterfly-4857 [link] [comments]

Ініціатива для професійної адаптації ветеранів і людей з інвалідністю KPI4U-1 пн, 05/11/2026 - 22:52

🎥 У КПІ відкрили виставку до 250-річчя Декларації незалежності США KPI4U-2 пн, 05/11/2026 - 22:42

Infineon Technologies AG of Munich, Germany has expanded its XHP 2 power module portfolio with new variants incorporating CoolSiC MOSFETs 2300V, designed for high-voltage power systems. The new 2300V-class devices support DC-link voltages of up to 1500V, addressing the industry trend toward higher system voltages...

Lumentum Holdings Inc of San Jose, CA, USA (which designs and makes photonics products for optical networks and lasers for industrial and consumer markets) has been included in the Nasdaq-100 Index. The firm is expected to join the index prior to the market opening on 18 May...

Custom ASIC/ASSP and power solutions provider Cyient Semiconductor Pte Ltd of Hyderabad, India has launched seven new gallium nitride (GaN) power devices for the Indian market, developed using the GaN technology of Navitas Semiconductor Corp of Torrance, CA, USA — which provides GaNFast gallium nitride (GaN) and GeneSiC silicon carbide (SiC) power semiconductors...

Photonic simulation CAD software developer Photon Design Ltd of Oxford, UK says that it has enabled the industry-first 3D quantum dot laser simulation, by integrating its HAROLD QD quantum dot laser simulation tool with its PICWave laser diode, SOA and photonic integrated circuit (PIC) simulator...

Market analyst firm TrendForce’s latest research into the micro-LED industry highlights how generative AI is driving rapid growth in demand for high-speed optical communications. Micro-LED technology offers power consumption as low as 1–2pJ/bit and ultra-low bit-error rates (BER) of ≤10-10. It is also emerging as one of the three major short-distance, high-speed intra-rack transmission solutions for scale-up data-center networks, alongside active electrical cables (AEC) and vertical-cavity surface-emitting laser (VCSEL)-based near-packaged optics (VCSEL NPO). As a result, TrendForce projects that the micro-LED CPO optical transceiver market will reach US$848m by 2030...

Кампус КПІ ім. Ігоря Сікорського стає ще зеленішим kpi пн, 05/11/2026 - 15:27

Kick-off GreenChem Accelerator 2026 у КПІ ім. Ігоря Сікорського kpi пн, 05/11/2026 - 15:20

Diminutive? Definitely. Flexible? Indubitably. Safety-cognizant? Thankfully…unless you activate “FORCE” mode, that is (hopefully intentionally).

A bit more than a year ago, within a blog post that talked about (potentially) resurrecting dead lead-acid batteries, I noted that I’d recently added additional members to my battery-charger stable. Historically, I’d relied on a legacy-design DieHard model, one of the two which, loudly humming and dubiously still working, I subsequently turned into a teardown target:

The others were all newer designs, solid-state (vs transformer-based) and both more flexible in their supported battery voltages and technologies and more feature-rich. Specifically, today I’ll be focusing on the NOCO Genius 1, a 1A trickle charge two examples of which I’d acquired on promo discount from Amazon’s Warehouse-now-Resale) site intending to tear one of ‘em down:

Walking while chewing gum

I’d teased the feature set a year-plus back, then focusing (given the overall writeup topic slant) on its battery-rejuvenating chops. Here’s the fuller feature-set list, requoted from the Amazon product page (from which, by the way, I’d acquired today’s dissection victim for only $20.12, ~1/3 off the current brand-new $29.95 price tag, which in and of itself also isn’t bad, or if you prefer, half off the $39.95 MSRP):

• MEET THE GENIUS 1 — Similar to our G750, just better. It’s 35% smaller and delivers over 35% more power. It’s the all-in-one charging solution – battery charger, battery maintainer, trickle charger, plus desulfator.
• DO MORE WITH GENIUS — Designed for 6-volt and 12-volt lead-acid (AGM, Gel, SLA, VRLA) and lithium-ion (LiFePO4) batteries, including flooded, maintenance-free, deep-cycle, marine and powersport batteries.
• ENJOY PRECISION CHARGING — An integrated thermal sensor dynamically adjusts the charge based on ambient temperature, preventing overcharging in hot weather and undercharging in cold, ensuring optimal battery performance.
• CHARGE DEAD BATTERIES — Charge batteries from as low as 1 volt, or use Force Mode to manually charge completely dead batteries down to zero volts. Perfect for recovering deeply discharged or neglected batteries.
• BEYOND MAINTENANCE — Keep your battery fully charged without worrying about overcharging. Our smart charger constantly monitors the battery, allowing you to leave it connected safely – indefinitely – for worry-free maintenance.
• RESTORE YOUR BATTERY — Precision pulse charging automatically detects and reverses battery sulfation and acid stratification, restoring your battery’s health for improved performance and extended lifespan.
• COMPATIBLE — Charges and maintains all types of vehicles, including cars, automobiles, motorcycles, mopeds, lawn mowers, ATVs, UTVs, tractors, trucks, SUVs, RVs, campers, trailers, boats, PWCs, jet skis, classic cars, and more.
• WHAT’S IN THE BOX — Includes a 1A charger, a direct wall plug-in, 110-inch DC cable with battery clamps, and integrated eyelet terminals, and 3-year warranty. Proudly designed in the USA.

It’s pretty tiny (that’s the aforementioned G750 behind it in the following photo, by the way); 3.62in (92mm) high, 2.32in (59mm) wide and 1.26in (32mm) deep, and weighing only 0.77lb (0.35kg):

And the manufacturer was even thoughtful enough to include a preparatory teardown diagram on the website product page:

(Simple) assembly required

Let’s see how close reality comes to matching that conceptual image, shall we? This charger arrived absent its packaging, so what you’ll see first (as usual accompanied by a 0.75″/19.1 mm diameter U.S. penny for size comparison purposes) is the other, ~$3 more, charger’s box:

Wonder what happened to the original “tab” for retail-display hanging purposes?

Opening up the box…

you’ll find user guide (also accessible here as a multi-language PDF, plus the product spec sheet) and promo literature, plus, in this particular case, the aforementioned formerly-MIA tab:

along with, of course, today’s two-part patient:

the base unit:

and the remainder of the cabling, including the battery terminal clamps:

Here’s the male-and-female connector pair that mates ‘em:

And what’s that lump partway down the “remainder of the cabling” span?

It’s a (user-replaceable, which is nice) fuse, as at least some of you may have already guessed. 2A is, IMHO at least, a reasonable choice considering the device’s 1A-max output specs:

Before putting the “remainder of the cabling” to the side, here’s a closeup of those “integrated eyelets” mentioned earlier in the bulletized feature list:

And this stock shot shows how to make ‘em usable:

A high degree of integration

Now for the base unit. Before diving inside, here are some real-life overview shots to augment the earlier stock ones:

You’ve probably already noticed the ultrasonic welds around the outside, holding the halves together. Regular readers may already recall that they’re a longstanding bane of mine. This time, since it was convenient to do so and I was under no delusions that the charger would be salvageable/reusable post-teardown anyway, I took a hacksaw to ‘em in conjunction with a vise:

Here’s what the inside of the back half looks like, revealing AC prong connections to the PCB:

And speaking of which, here’s our first look at the PCB itself, specifically the backside:

Nothing here is particularly surprising, nor is the broader fact that DC conversion circuitry dominates the landscape, given the physical proximity to the AC source. Most notable, probably, is the diminutive size of the two transformers, explained in part (but only in part) by this particular unit’s trickle-current characteristics. For the rest of the (hint: solid-state) story, we’ll need to see the other side of the PCB. No better time than the present:

Taking (which?) temperature

With the normally-restraining screws now removed:

and in the process of lifting the PCB out of the remaining chassis half:

I happened to notice, down by the DC cable exit point, two more wires alongside a NTC1 notation on the PCB:

I’m (fairly confidently) assuming that they reference a negative temperature coefficient (NTC) thermistor. My initial reaction, and one that in retrospect I admittedly clung to far too long, was that it somehow was used to ascertain if the battery itself was overheating, a situation which would compel the charger to “cut the juice”. Problem being, though, that there are only two wires (DC positive and negative) in the cable running from the main unit to the battery, so the thermistor would end up being nowhere near the battery itself (PDF).

In grasping at straws, I surmised that perhaps the battery temperature was being indirectly determined by the transferred temperature of the connected cabling, which admittedly seemed increasingly silly the more I thought about it. But then I re-read the device specs prior to sitting down to write and realized that what the thermistor was actually measuring was (probably) just the ambient environmental temperature. “An integrated thermal sensor dynamically adjusts the charge based on ambient temperature, preventing overcharging in hot weather and undercharging in cold, ensuring optimal battery performance.” Yeah, that’s it. Ahem.

Onward. Interesting PCB topside two-level sandwich, eh?

And speaking of which:

here’s the inside of the front half of the chassis:

And the PCB topside itself:

The largest IC, the one with the white dot on it and located at lower right on the top (of the two-PCB sandwich) mini-PCB, is the “brains” of the operation, an ABOV Semiconductor A96G148GR 8-bit 8051-class microcontroller with integrated flash memory. On the other (top) end, toward the center, is the multi-function toggle switch, which puts the charger in various operating modes, surrounded by a ring of LEDs, including two more toward the bottom. And to its far left is the multi-pin connector that mates the mini-PCB with its larger sibling below it.

I almost stopped at this point, clinging to the delusion that maybe I’d glue everything back together again in fully-functional form. But curiosity-while-writing eventually got the better of me (and anyway, that was a silly idea), so I rotated the assembly by 90° so the PCB markings could be read right-side-up and let ‘er rip:

Ok, now I’m done!

A (potentially fatal?) forcing function

In closing, let’s revisit that just-referenced multi-function toggle switch, specifically in the context of the “unless you activate “FORCE” mode (hopefully intentionally), that is” comment in this article’s subtitle. Quoting from the user guide:

Mode	Explanation
Force Mode Press & Hold (5 Seconds)	For charging batteries with a voltage lower than 1V. Press and Hold for five (5) seconds to enter Force Mode. The selected charge mode will then operate under Force Mode for five (5) minutes before returning to standard charging in the selected mode.

Here’s the ominous bit:

Force Mode. [Press & Hold for 5 seconds]
Force mode allow the charger to manually begin charging when the connected battery’s voltage is too low to be detected. If battery voltage is too low for the charger to detect, press and hold the mode button for 5 seconds to activate Force Mode, then select the appropriate mode. All available modes will flash. Once a charge mode is selected, the Charge Mode LED and Charge LED will alternate between each other, indicating Force Mode is active. After five (5) minutes the charger will return to the normal charge operation and low voltage detection will be reactivated.

CAUTION. USE THIS MODE WITH EXTREME CARE. FORCE MODE DISABLES SAFETY FEATURES AND LIVE POWER IS PRESENT AT THE CONNECTORS. ENSURE ALL CONNECTIONS ARE MADE PRIOR TO ENTERING FORCE MODE, AND DO NOT TOUCH CONNECTIONS TOGETHER. RISK OF SPARKS, FIRE, EXPLOSION, PROPERTY DAMAGE, INJURY, AND DEATH.

The entire quote, notably the all-caps portion, was 100% original, by the way, not “enhanced” in any way by editing from yours truly (explaining, among other things, the “creative” grammar in spots). Reminds you of Jason Hemphill’s “hack” that I highlighted back in mid-March, doesn’t it?

Death. I’ll just leave that for you to ponder as you wish. Memento Mori, my friends. And with that pleasant thought , I’ll wrap up for today and turn it over to you for your thoughts (feel free to skip posting the morbid ones, please) in the comments!

—Brian Dipert is the associate editor, as well as a contributing editor, at EDN.

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When structures bend, stretch, or compress, engineers need a way to translate that invisible mechanical stress into measurable data. Strain gauges do exactly that—tiny sensors that convert deformation into electrical signals with remarkable precision.

From monitoring bridges and aircraft wings to ensuring the reliability of everyday electronics, strain gauges are the quiet workhorses that make stress visible, quantifiable, and actionable.

How resistance reveals stress

At the heart of every strain gauge lies a deceptively simple principle: when a conductor or semiconductor is stretched, its electrical resistance changes. Engineers harness this effect by arranging strain gauges in a Wheatstone bridge circuit, amplifying tiny resistance shifts into measurable voltage signals.

It’s a clever translation—microscopic deformations become clear electrical outputs. Narratively, this is where the magic happens: the silent stress within a bridge girder or aircraft fuselage suddenly speaks in numbers, allowing designers to predict failures, validate models, and ensure safety long before cracks appear.

Stress signals in the real world

A strain gauge is the sensing element itself, while a strain gauge sensor is the complete packaged device that integrates the gauge with wiring, housing, and often signal conditioning for practical measurement. That distinction becomes critical when sensors are deployed in demanding environments.

Consider aerospace wing testing: engineers attach arrays of strain gauges across critical points of an aircraft wing. As the wing flexes under simulated flight loads, each gauge’s resistance shifts, feeding signals into a monitoring system. The sensor assemblies ensure those delicate gauges survive vibration, temperature swings, and handling. This is where theory meets reality—tiny resistance changes become the data that validates aerodynamic models, ensures passenger safety, and drives innovation in lighter, stronger aircraft designs.

Civil infrastructure offers another compelling example. Bridges endure constant stress from traffic, wind, and temperature cycles. Embedded strain gauge sensors provide early warnings of fatigue, helping engineers schedule maintenance before cracks or failures occur. In this narrative, strain gauges are not just measuring stress, they are safeguarding lives and economies by keeping critical structures resilient and reliable.

A technical note: A strain gauge directly measures strain (physical deformation). From this measurement, we determine the internal stress—the intensity of the forces resisting that deformation—using the material’s known stiffness.

Strain gauge vs. load cell vs. FSR

Since this post is focused on strain gauges, here is a quick distinction. A strain gauge measures material deformation as a resistance change, forming the basis of precise force sensing. A load cell builds on this, packaging strain gauges into a calibrated transducer for accurate weight and force measurement in industry. By contrast, a force-sensing resistor (FSR) is a low-cost sensor whose resistance shifts with pressure—handy for relative force detection in consumer and robotic applications, but far less precise.

Figure 1 Strain gauges and force-sensing resistors convert mechanical input into changes in electrical resistance, yet their responses vary in linearity, sensitivity, and application scope. Source: Author

So, in essence, when designers and engineers need to measure force, two of the most widely used technologies are force sensing resistors and strain gauges. Both convert mechanical input into changes in electrical resistance, yet their principles, accuracy, and applications differ greatly.

A force sensing resistor is a thin, flexible, polymer-based sensor whose resistance decreases as pressure is applied to its surface. A strain gauge, on the other hand, is made of fine metallic foil or wire arranged in a grid and bonded to a stable substrate. Rather than detecting direct pressure, it measures strain—the deformation of the material it is attached to. As the material stretches or compresses, the strain gauge deforms as well, producing a slight change in resistance. This change is typically measured using a Wheatstone bridge circuit for precise results.

Similarly, load cells build upon strain gauge technology by integrating one or more gauges into a mechanical structure that translates applied force into measurable strain. This makes load cells highly accurate and reliable devices for quantifying weight and force in industrial, commercial, and scientific applications.

Figure 2 A compact button-type load cell, based on strain-gauge technology, delivers compression measurements in space-limited applications. Source: ATO

Wheatstone bridge configurations for precision strain measurement

In practical applications, strain measurements typically involve very small changes rather than large strain values. Detecting these minute variations requires precise measurement of small resistance changes. A Wheatstone bridge circuit (WBC) is widely used for this purpose, as it translates subtle resistance shifts into measurable voltage outputs.

A standard Wheatstone bridge consists of four equal resistors arranged in a square. An excitation voltage is applied across one diagonal, while the output voltage is measured across the other. In its balanced state, the bridge produces zero output voltage. For strain measurement, one or more resistors are replaced with active strain gauges, whose resistance varies in response to external forces acting on the structure.

To achieve higher sensitivity and improved accuracy, different Wheatstone bridge configurations are employed: quarter-bridge, half-bridge, and full-bridge. In a quarter-bridge, a single resistor is replaced with a strain gauge. A half-bridge uses two strain gauges, while a full bridge replaces all four resistors. These configurations not only enhance measurement precision but also help compensate for temperature effects, making them essential in modern strain gauge instrumentation.

Figure 3 Diagram illustrates a quarter Wheatstone bridge, where one resistor is replaced by the strain gauge. Source: Author

Selecting the right strain gauge

Selecting the right strain gauge requires balancing geometry, resistance, and environmental compatibility to achieve accurate measurements while controlling installation costs. Options range from simple linear gauges for uniaxial stress fields to rosette configurations—rectangular, delta, or tee—for analyzing complex or unknown stress directions, and bridge arrangements for enhanced sensitivity and thermal compensation.

The choice of grid orientation and gauge length must align with the material’s homogeneity and the stress distribution being measured. Equally important are electrical parameters such as the nominal resistance, which determines compatibility with the measurement circuitry, and self-temperature compensation, which offsets thermal effects to maintain accuracy and improve signal-to-noise ratios under fluctuating operating conditions.

Environmental and installation considerations in strain measurement

As stated before, strain gauges are inherently sensitive to temperature variations, and changes in temperature can alter their electrical resistance. If not properly compensated or controlled, this effect can introduce significant measurement errors.

Beyond temperature, external factors such as humidity, moisture, vibration, and electromagnetic interference can also degrade performance and accuracy. Appropriate protective measures—such as encapsulation, shielding, and environmental sealing—are therefore essential to ensure reliable operation.

Equally important is the bonding of the strain gauge to the surface of the substrate. A strong, uniform bond ensures that the gauge accurately follows the strain of the underlying material. Achieving this can be challenging when working with dissimilar materials or irregular surfaces. Poor bonding may result in signal instability or inaccurate readings, undermining the integrity of the measurement system.

Practical strain gauge systems: Bridges, amps, and test kits

In a Wheatstone bridge, the strain gauge serves as the variable resistor whose resistance shifts under mechanical deformation, producing a differential voltage proportional to strain. Because this resistance change is extremely small—often less than 0.1% of the gauge’s nominal value—the bridge must be energized with a stable excitation source and paired with an amplifier stage to extract the signal from noise.

For basic designs, a differential amplifier can provide initial signal conditioning, but for precision applications, an instrumentation amplifier (INA) is preferred due to its superior common-mode rejection and high input impedance.

Keep in mind that the bridge configuration depends on accuracy requirements: a quarter-bridge offers simplicity, a half-bridge adds temperature compensation, and a full-bridge delivers maximum sensitivity. The choice of amplifier ensures the bridge’s delicate balance is preserved while enabling reliable strain measurement.

Today’s compact strain gauge amplifiers make the entire measurement workflow far more straightforward by integrating multiple critical functions into a single, easy-to-use module. Not only do they provide clean signal gain and low-noise performance, but many also feature built-in excitation voltage sources, eliminating the need for external supplies.

They often include automatic bridge balancing to correct minor mismatches in resistance, ensuring the Wheatstone bridge remains stable and accurate. With high input impedance, filtering options, and sometimes digital outputs, these amplifiers reduce design complexity, accelerate setup, and deliver reliable strain data. For engineers, this means less time spent on circuit design and more confidence in capturing precise measurements across lab and field applications.

Figure 4 Compact strain gauge amplifier modules meet growing demand for industrial strain measurements, where miniature size and easy setup are essential. Source: Transmission Dynamics

Moreover, when it comes to strain gauge test kits, they offer a practical, all-in-one pathway for converting mechanical stress into precise electrical signals. These kits typically include gauges with standard resistances (120 Ω or 350 Ω), along with surface preparation tools, adhesives for secure bonding, and protective coatings to ensure durability in challenging environments.

Once integrated into a Wheatstone bridge, the kit enables detection of minute resistance changes defined by the gauge factor, directly linking strain to output voltage. Thus, strain gauge kits simplify what would otherwise be a complex measurement workflow, making them indispensable across fields ranging from structural health monitoring and aerospace stress testing to advanced biomechanics.

That wraps up today’s dive into strain gauges. From foil to semiconductors, the evolution continues—and now it’s your turn to engineer what comes next.

T. K. Hareendran is a self-taught electronics enthusiast with a strong passion for innovative circuit design and hands-on technology. He develops both experimental and practical electronic projects, documenting and sharing his work to support fellow tinkerers and learners. Beyond the workbench, he dedicates time to technical writing and hardware evaluations to contribute meaningfully to the maker community.

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The post Strain gauges: Turning stress into signal appeared first on EDN.

For fiscal third-quarter 2026, Wolfspeed Inc of Durham, NC, USA — which makes silicon carbide (SiC) materials and power semiconductor devices — has reported revenue of revenue of $150.2m, down 10.6% on $168m last quarter and 19% on $185.4m a year ago...

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