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New unmanned aircraft expand the Indian company’s portfolio across long-range surveillance and tactical unmanned combat aerial vehicle applications.

Indian autonomous aerial vehicle supplier ideaForge Technology has announced the launch of two variants of its ZOLT tactical UAV system- the ZOLT Hybrid and the ZOLT Unmanned Combat Air Vehicle (UCAV). The move signals ideaForge’s entry into the long-range (ISR) as well as tactical unmanned aerial system (UAS) markets. The existing ZOLT system is already thought to be in service with the Indian Army. The ZOLT Hybrid is reported to have endurance of more than six hours and a range of 100km, and is intended for long-range surveillance and persistent overwatch missions. Its hybrid architecture, combining vertical take off and landing and longer endurance, offers an advantage in areas lacking suitable runways or where they are too hard to create.

The ZOLT UCAV is intended for tactical operations and precision effects. Endurance is said to be 2-3 hours, with a launch and recovery range of 30- 50 km. Its use case is clearly different from a surveillance aircraft, with more focus on the tactical deployment and mission-specific payloads. While this introduction mirrors a broader transition in defence aviation to unmanned aircraft that operate in difficult terrain and minimise personnel exposure to immediate risk, operational performance of these aircraft will always be defined by payload mix, comms resilience, environmental conditions and mission parameters.

The development also underscores the increasing involvement of indigenous manufacturers providing specialised UAV system services to India’s armed forces. Procurement, as well as the operational evaluation and fielding of the systems, will influence the pace at which the new variants are further integrated.

The post ideaForge Launches ZOLT Hybrid and UCAV Variants for Tactical Missions appeared first on ELE Times.

Indigenous lighter-than-air system reaches 21 km altitude during flight trial, supporting India’s high altitude surveillance ambitions.

India’s Defence Research and Development Organisation (DRDO) has successfully flight-tested a domestically developed High Altitude Platform (HAP) for long endurance surveillance and Communication capabilities. The Press Information Bureau of the Ministry of Defence issued a statement: “The experimental platform attained an altitude of 21 kilometres above mean sea level (AMSL) and hovered at 20 kilometres (AMSL) for over 30 minutes before being commanded to descend. The flight test system was recovered successfully, and post-flight performance data was analysed. The lighter-than-air platform, a potential long endurance, stratosp​heric surveillance system, is being developed by DRDO’s Aerial Delivery Research and Development Establishment (ADRDE), Agra.”

High-altitude platforms would enhance the satellite, aircraft, and existing UAS fleet by enabling constant monitoring of an area. These platforms might be used for border monitoring, intelligence collection, weather monitoring, communications support, etc. Its utility will be based on how long the platforms can stay in flight, how much equipment they can carry, and how well they can withstand the weather and stay where they are supposed to, which is called station-keeping. The trials required coordination with the Indian Air Force, CEMILAC, the Directorate General of Civil Aviation, the Airport Authority of India, and other organizations. “During the flight test, engineers at the ground control station collected real-time video as well as vehicle parameter data. The high-altitude platform payload carried an inertial measurement unit, a Global Positioning System (GPS) receiver, onboard cameras, an altitude-control system, and other electronic subsystems,” the statement mentioned.

The post DRDO Tests High-Altitude Platform, Advancing India’s Persistent Surveillance Capabilities appeared first on ELE Times.

A language model with 14.3 million parameters runs entirely on an ESP32-S3 microcontroller and makes every high-level decision for a small virtual fish tank: eat, hide, explore, socialize, rest or flee. The brain is a 7.56 MB file read directly from flash, with no network and no cloud. The tank lives on a 1.8-inch AMOLED display you can hold in one hand. So no server, no API, no connection is needed: the fish decides on its own, on the spot.

The project shows that a model distilled from roughly 26 billion parameters can run on a microcontroller costing a few dollars. The student, called pocket-tank, has 14.3 million parameters with dimension 384, 8 layers and 8 heads: about 1,818 times fewer than the teacher. In fp32 it would weigh 57 MB, in 4 bit it drops to 7.56 MB. The vocabulary is 58 tokens, a closed-schema lexicon, against the teacher’s roughly 262K tokens.

Three separate layers compiled identically in the simulator and the firmware

The architecture is split into three layers, all in common/ and compiled identically in the simulator and the firmware: the reflexes layer (tank.c), the LLM advisor (llm/) and the progression layer (progression.c). The reflexes layer handles physics, steering, schooling, touch gestures, feeding, hunger economy, vegetation and algae. It runs every frame and never blocks on the model. The LLM advisor, on the other hand, is a 4-bit inference engine in the style of llama2.c, with a word-level tokenizer and a shared state encoder.

The model runs on the ESP32-S3’s second core with SIMD dot products and quantized activations in internal SRAM. The weights are memory-mapped from flash and are never copied. That’s why the tank stays smooth while the model thinks. The fish are re-queried only when their situation changes significantly: that way four or six fish share a single brain.

Each fish periodically describes its situation to the model as a single line of text: hunger, energy, fear, who is nearby, its personality.

The model completes the line with a goal and an urgency.

The reflexes layer turns that goal into movement.

The model samples its own distribution instead of always taking the most likely answer.

When the top two choices are close, the fish visibly hesitates before committing.

There are no fallback heuristics that override the decision.

The training numbers tell the story of the distillation quality. The model was trained on 51,162 situations labeled by the teacher. The student picks the teacher’s goal in 75% of cases, while the teacher agrees with itself in 82% of cases. A hungry fish chooses seek_food at least 89% of the time, across all personalities. So the 4-bit quantization did not destroy the learned behavior.

The board, the 8 MB partition and the bench-measured timings

The firmware is based on ESP-IDF v5.4 with 8 MB octal PSRAM. The target board has 16 MB of flash and 8 MB of PSRAM. The model lives in a dedicated 8 MB raw partition and only needs to be flashed once, at address 0x290000. On the hardware side the project uses a Waveshare ESP32-S3-Touch-AMOLED-1.8 with ESP32-S3R8, a 368×448 AMOLED display, capacitive touch, IMU, PMIC and RTC. The board with screen and battery actually costs around 35 dollars.

On the real board a decision takes about 3.6 s at 12 tokens per second, with the tank rendered at 25-30 fps in parallel on the other core. In QEMU emulation a decision takes about 2.3 s. The tank starts with two fry and grows to as many as five fish. A meal lasts five or six minutes while awake. Holding a finger on the glass for three seconds calls over the fish that trust you. The reset prompt disappears after twenty seconds of silence.

For anyone who wants to rebuild the project, the software chain includes ESP-IDF v5.4, a 4-bit inference engine in the style of llama2.c, LVGL v9.2.2, SDL2, ESP Web Tools, the scripts tools/make_installer.py and tools/director.py, and QEMU in the Espressif version. Those who want to look at a board with an integrated display and LVGL graphics can also consider other options, but the heart of the project remains the 8 MB raw partition and the 4-bit engine. The code, the scripts and the flash procedure are collected in the project code repository.

Anyone who wants to replicate the sensor part can consider a 9-axis IMU module to add orientation and movement to the tank, or an RTC circuit on an I2C bus to keep track of time even when the board is off. Both components already appear on the target board, so the wiring stays consistent with the existing firmware.

Source: https://github.com/mediacutlet/pocket-tank

Related products

• Blebrick 9-Axis IMU
• I2C Real-Time Clock IC

The post A 14.3-million-parameter language model runs on an ESP32-S3 and decides the life of a virtual aquarium appeared first on Open Electronics.

I just made my first handmade PCB. I drilled and cut the lanes my self. There is no short circuit and its little bit messy. If you have any advice maybe how i can do it beter i will take it. I know i could make it with those fluid chemicals or whatever but my parents don't trust me with it. Its a 5-35 to 5 V Circuit with a LED that indicates when the 5V pin gives out power. submitted by /u/Current-Drama846 [link] [comments]

A 16-bit relay computer that computes Pi, the square root of 60000 and Dijkstra’s shortest paths. It sounds like an exercise in style, but it is a real machine, built by Peter with self-holding relays running at 24 V. The CPU is an accumulator-register design: all math and load/store operations go through the ACCU. The instruction set has 19 commands, enough to run algorithms that are usually seen on far more generous machines.

Computing Pi to 2 decimal places took a little over 8 minutes and 1,377 instructions. The integer square root of 60000 came out as 244, that is 1111 0100 in binary. These numbers say two things: the machine is slow, but the project is complete. In fact it is not a partial prototype, but a system with memory, peripherals and a 32×32 LED matrix display connected at the output.

The program counter, the SR register and the three addressing modes

The program counter has a dedicated adder capable only of adding 1. That is why the PC_HR register exists: the modified PC cannot be written directly to its own value plus 1, so an intermediate holding place is needed. The SR register stores the return address, so the CALL and RET instructions handle a single level of subroutine. No stack is implemented, and with 19 instructions none is needed.

The CPU supports 3 addressing modes. With LD X the ACCU is loaded with the word at the address following the opcode. With LD M(X) it loads the data at the address contained after the opcode. With LD M(M(X)) we reach indirect addressing. So the programmer already has the tools for pointers and tables, not just for adding two numbers.

• 16-bit CPU with ACCU accumulator register
• 19 instructions in the CPU instruction set
• 3 addressing modes, including indirect M(M(X))
• SR register for one subroutine level with CALL and RET
• Clock made up of 4 different pulses
• Relay supply at 24 V
• Memory implemented with an Arduino
• Clock generator built with a second Arduino
• 32×32 LED matrix display
• 16-bit I/O register and 16-port input register

Why the clock has 4 pulses and the memory sits on an Arduino

All registers made with self-holding relays must be cleared before any write. Consequently the clock is not a normal digital clock, but is made up of 4 different pulses. This is the part that surprises anyone trying to rebuild the project: the clear and load sequence has to be designed together with the logic, not afterwards.

The memory is not relay-based. It is implemented by an Arduino, and a second, separate Arduino builds the clock generator. That way the project stays within reach of anyone with a normal workbench: the relays do the electromechanical part, the microcontrollers do the rest. In addition, the I/O register is 16 bits and the input register is 16 ports.

Before soldering, Peter verified everything in simulation. The full-system simulation runs in the game Logic World, used to design the system and try out variants. Then there are the Excel macros, which execute the code step by step and show registers and memory up to a breakpoint. Finally the VHDL code on FPGA emulates the relay system design. Anyone who wants to follow the same path will find the full story on the page for Peter’s project on Hackaday.io, with the tests carried out and the variants discarded.

For anyone who wants to replicate the display part, the catalogue offers an FPGA-based development board to drive LED matrices, while a small 2.42-inch OLED module with 128×64 resolution and SPI or I²C interface can serve as a status panel for registers and memory. They are two different routes: the first stays consistent with programmable logic, the second costs little and connects with just a few wires.

Rebuilding this relay computer means starting from the 4-pulse clock and the accumulator register. Without those two pieces nothing runs, not even with 19 perfect instructions. The rest is patience: 24 V on the relays, flyback diodes, one Arduino for the memory and one for the clock.

Source: https://hackaday.io/project/189725-homebrew-16-bit-relay-computer

The post A 16-bit Relay Computer Runs Pi and Dijkstra appeared first on Open Electronics.

ROHM Semiconductor announces that its innovative power semiconductor solutions are being used in the electric vehicle platforms of a world-leading premium car manufacturer. In BMW’s “Neue Klasse”, ROHM’s SiC (silicon carbide) chips support the efficiency, performance and reliability of the vehicle’s electric powertrain systems.

Integrating SiC MOSFETs into the BMW Neue Klasse

The high-performance components integrated into the vehicle support key power electronics functions and are designed to ensure high energy efficiency as well as reliable operation under the harsh operating conditions typical of the automotive sector. In this way, they make an important contribution to optimising the range, charging performance and overall energy efficiency of electric vehicles.

Statements

“The integration of our SiC MOSFETs into the Gen 6 of BMW’s electric vehicles, better known as the Neue Klasse, highlights ROHM’s technological expertise in power electronics for the automotive sector,” says Wolfram Harnack, President of ROHM Semiconductor GmbH: “We are proud to contribute, together with the BMW Group, to the progress of next-generation electric mobility through our SiC technology. This underlines our long-term commitment to supporting our automotive customers with high-quality products and extremely high reliability.”

ROHM’s experience in the automotive sector

ROHM has extensive experience in the development and production of power semiconductors for automotive applications and works closely with vehicle manufacturers and Tier 1 suppliers worldwide to actively promote the electrification and decarbonisation of mobility.

For further information, visit the ROHM website.

The post ROHM Supplies SiC Chips for BMW Neue Klasse Electric Powertrain appeared first on Open Electronics.

Capturing 3D images without lenses is possible. The okooptics project proves it, starting from a Raspberry Pi camera whose lens is removed and over whose sensor a thin layer of Scotch tape is applied. The tape is not a market-stall trick: it acts as an optical diffuser and imprints a known point spread function on the scene. With the right deconvolution maths, the initially blurry capture turns into a real image.

The interesting part comes next. By weighting the point spread function across three dimensions and adding a directional bias to the process, an effect similar to a shift in the camera position is created. That way the scene reveals itself from a slightly different angle, without physically moving anything.

How deconvolution works on a blurry capture

The workflow starts with a Raspberry Pi camera without the normal lens element installed. In place of the lens, a thin layer of Scotch tape is applied over the sensor. That veil diffuses light in a controlled way, so every point in the scene leaves a blob of predictable shape on the sensor. The shape of the blob is the point spread function.

• You start with a Raspberry Pi camera without the lens element.
• In place of the lens, a thin layer of Scotch tape is applied over the sensor.
• The tape acts as a diffuser and defines the point spread function.
• Deconvolution recovers a real image from the initially blurry capture.
• Weighting the point spread function across three dimensions extends the concept to 3D.
• Adding a directional bias simulates a shift of the camera.

Once the point spread function is known, deconvolution is a linear algebra problem. The software takes the blurry capture and the diffuser function, then estimates the original image. It is the same idea behind many computational imaging techniques, but here the diffuser is a piece of tape costing a few cents instead of an optical element designed in a lab.

The directional bias that shifts the viewpoint

The jump to 3D lies in the weight given to the point spread function. Instead of treating it as a flat function, the project weights it across three dimensions. What is more, by adding a directional bias to the process, an effect similar to a shift in the camera position is created. The result is a view from a slightly different angle of the objects in front of the camera.

Rebuilding the project takes only a few parts. The Raspberry Pi camera is the heart of the system, and the Scotch tape is the diffuser. Anyone who wants to start from scratch can use a 5 megapixel camera module for Raspberry Pi, which carries the Omnivision 5647 sensor. The rest is software: the deconvolution runs on a computer or on the board itself, depending on how much power you have available.

If you want to do the computation directly on board, you need a board with a bit of muscle. The Raspberry Pi 5 with 2 GB of memory carries the Broadcom BCM2712 quad-core processor at 2.4 GHz with Arm Cortex-A76 architecture, so it handles deconvolution operations on reasonably sized images well.

The author does not hide the practical limits of the technique. The quality of the reconstruction depends on how precisely the point spread function is estimated, and tape is not an optical component that stays stable over time. What is more, deconvolution amplifies noise, so it is best to work with well-lit scenes and sensors with low background noise. Anyone who wants to dig deeper into the science behind the project will find the full story and references to the research papers on the project page on Hackaday.io.

Source: https://hackaday.io/contests

Related products

• 5 Mpx Camera for Raspberry Pi
• Raspberry Pi 5 – 2 GB memory version

The post Lensless 3D imaging with Scotch tape and deconvolution appeared first on Open Electronics.

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📰 Газета "Київський політехнік" № 33-34 за 2026 (.pdf) kpi сб, 10/10/2026 - 21:26

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GlitchCaster is an evaluation device for electromagnetic fault injection, or EMFI. It generates an electromagnetic pulse of about 250 V through coil probes and mounts directly on the head of an old 3D printer or a CNC machine. That makes security testing repeatable, because the probe moves along the X, Y and Z axes with the precision the machine’s mechanics already guarantee. The project comes from Diffused Tactics.

The coil is brought close to the target device and the pulses fire with precise timing. The disturbance is temporary and aims to make the target fail at the exact moment it performs a check. The mount also follows the same topology as 40 mm fans, so the bracket fits many heads already found in a workshop. The module has no built-in controller: it exposes 2.54 mm headers and screw terminals, and you choose the GPIO and PWM controller.

The 250 V flyback and the 630 V 470 nF capacitor

The high-voltage section uses a DC/DC flyback circuit built around the LDA111 and the ATB3225. The storage capacitor is rated 630 V 470 nF, so its working voltage sits comfortably above the 250 V of the pulse. The included probe coil is 4.7 uH, with a 4 x 15 mm ferrite core and a 17.5-turn winding. An adapter board lets you swap between coils with a through-hole lead and coils with an SMA connector.

The measurements of the three PCBs help you judge the footprint. The main board measures 71 mm x 32 mm x 1.65 mm. The SMA adapter board measures 11.6 mm x 10.1 mm x 1.65 mm, which becomes 29.3 mm once the connectors are included. Finally, the controller board measures 71 mm x 30 mm x 1.65 mm. The supplied jumper wires are 24 inches long, enough to carry the signals from the machine head to the controller without straining the cables.

PicoEMP firmware and interchangeable SMA connectors

The firmware stays compatible with that of PicoEMP-based projects, so anyone who has already worked on that design will find the same logic. On top of that, the firmware can be customised by advanced users, who can adapt the pulse timing to their own test bench. Mounting on the printer or CNC rail does the rest: the Raspberry Pi Pico kit with sensors and actuators covers the prototyping side around the controller, if you need something to connect to the GPIOs.

Anyone who wants to rebuild the test bench will find a description of the device and its parts in the Diffused Tactics campaign on Crowd Supply. For the rest, the list of parts that matter is short and worth reading through again in order.

• LDA111 and ATB3225 for the DC/DC flyback of the high-voltage section
• 630 V 470 nF storage capacitor
• 4.7 uH probe coil with a 4 x 15 mm ferrite core and 17.5 turns
• 2.54 mm connectors, 2.54 mm screw terminals and SMA connectors
• controller board based on the Raspberry Pi Pico
• 24-inch jumper wires and adapter PCB for the probes

The strong point is the recycled mechanics. A 3D printer sitting idle in a corner becomes a three-axis positioner for the probe, and every pulse starts from the same point with the same delay. As a result, tests can be repeated and compared, instead of depending on the hand holding the coil. The GlitchCaster makes EMFI security testing accessible and repeatable by exploiting a machine that is already in the workshop.

Source: https://www.crowdsupply.com/diffused-tactics/glitchcaster

Related products

• Raspberry Pi Pico Primer Kit – Plug&Play Sensors and Actuators

The post GlitchCaster: EM Fault Injection Rides on a 3D Printer Head appeared first on Open Electronics.

Melexis has introduced the MLX91224 and MLX91225, expanding its portfolio of isolated current sensors for high-voltage applications in the automotive and industrial sectors. Offering plug-and-play measurements up to 100 A RMS, ASIL B compliance and a fast analog response in three package options, these new devices simplify the design of electric vehicle powertrains, DC-DC converters, chargers and solar systems.

The challenge of current measurement in electrification

As electrification continues to advance across many applications (renewable energy, industrial, automotive, energy storage systems…), current measurement becomes increasingly complex. Designers need accurate, isolated measurements for system control and safety. For measuring small currents, a common solution is the shunt-based approach. However, these solutions generally involve increased ohmic losses, the need for isolated amplifiers, greater assembly complexity and a significant commitment to end-of-line calibration.

The MLX91224 and MLX91225 overcome these challenges by integrating the current conductor, the sensing element, signal conditioning and isolation into a compact SOIC package. Current flows directly through the package’s low-impedance leadframe, while two sets of Hall plates differentially detect the magnetic flux generated by the current. This architecture minimizes interference from external magnetic fields and delivers a linear, high-speed analog output proportional to the measured current, with isolation values that depend on the package and support working voltages up to 1640 V RMS.

Built-in safety and fast current measurement

For automotive applications, Melexis brings to market an integrated current sensor platform with ASIL B certification unprecedented in the industry for high-voltage current measurement, in the form of the MLX91224 and MLX91225. Developed as Safety Elements out of Context (SEooC) according to ISO 26262, the devices give designers a more solid starting point for measuring safety-related current in high-voltage automotive systems. This platform ensures a fast response for current measurement in motor control, electric drives, DC-DC converters, AC and DC chargers, solar installations, power supplies and many other applications.

The devices are available in DE, DG and DH package options to meet different current, isolation and impulse overvoltage requirements. The compact DE package offers a continuous operating current capability up to 50 A (RMS value) and overcurrent detection (OCD) in a cost-effective SOIC6FL format. In the SOIC16W format, the DG variant supports a similar continuous operating current range and working voltage, guaranteed by greater isolation and creepage distance. For higher-current designs, the DH package extends the platform to a continuous operating current capability of 100 A RMS in the SOIC12W FL package, with excellent impulse overvoltage values up to ±29 kA.

A versatile solution for automotive and industrial power

All devices support AC and DC current measurement, bipolar or unipolar detection and ratiometric or fixed output configurations. The MLX91224 is designed for 5 V systems, while the MLX91225 supports 3.3 V systems, allowing designers to select the device best suited to the available supply voltage and microcontroller architecture. The OCD function is provided through a dedicated pin, with thresholds defined internally or externally via the OCD-TH pin, to support protection and monitoring functions. With an operating temperature range from -40 °C to 150 °C, the platform is designed for use in particularly demanding industrial and automotive applications.

«Many customers design solutions across a wide range of power levels, from low-power motors to higher-current infrastructure», said Bruno Boury, Product Line Director at Melexis. «The MLX91224 and MLX91225 offer a current sensor platform that can grow with their power requirements, while helping to simplify isolation, overcurrent detection and functional safety integration.»

The MLX91224 and MLX91225 extend Melexis’ integrated current sensor portfolio toward higher-current applications, supporting the company’s strategy focused on electric vehicle powertrains, electrification and sustainable energy infrastructure. The devices are designed for use in the automotive sector and beyond, covering applications such as AC and DC chargers, electric drives, DC-DC converters, solar systems, data center power distribution units, power supplies and load and demand control.

The MLX91224 and MLX91225 are available in three package options. For more information, visit www.melexis.com/MLX91224-MLX91225.

The post Melexis MLX91224 and MLX91225: Integrated Current Sensors up to 100 ARMS appeared first on Open Electronics.

The TinyGo Starter Kit with Seeed Studio XIAO brings the Go language to embedded hardware. At its centre is the pre-soldered Seeed Studio XIAO ESP32-C3 board, with 2.4GHz WiFi and BLE 5.0, which plugs into the Grove Base for XIAO. The kit includes 11 plug-and-play Grove modules and a set of official tutorials for learning by building real projects. The price is 53.54 dollars.

Go was released to the public in 2009 and today is a widely used language on the server side. TinyGo brings a version designed for microcontrollers, with support for more than 150 development boards and WebAssembly as a target. Anyone who already programs in Go therefore finds a direct path into the embedded world, without changing language.

XIAO ESP32-C3, Grove Base and 11 modules with no soldering

Assembly requires no soldering. The XIAO ESP32-C3 board slots onto the Grove Base for XIAO, which acts as an expansion board for the modules. From there each module connects with the Grove connector, so you go straight to the code. For anyone who wants to start with a cheap and versatile board, an ESP12 board with mikroBus and Grove slots remains a different but equally easy-to-program option.

• Inputs: button, touch, rotary, light, sound, temperature, vibration and acceleration
• Outputs: RGB LED, OLED display and buzzer
• Sensors included: Grove Light Sensor v1.2 with LS06-S phototransistor, Piezo Vibration Sensor, Temperature Sensor, Rotary Angle Sensor
• Other modules: Piezo Buzzer/Active Buzzer and Sound Sensor based on the LM358 amplifier
• 0.66-inch Grove OLED display (SSD1306), IIC, 3.3V/5V
• Grove RGB LED Stick with 10 WS2813 Mini 3535 LEDs

Every hardware module is backed by programming tutorials written by Patricio Whittingslow of TinyGo. The path therefore does not stop at the board: you move from the light sensor to the buzzer, from the OLED display to the RGB LED, building projects that really work. For anyone looking for a compact board for embedded and IoT prototyping, a mini development board based on the RP2040 is an interesting alternative, but here the point is something else: the Go language.

TinyGo v0.41 and native wireless support on XIAO

TinyGo v0.41 brought native wireless support to the XIAO ESP32-C3 and XIAO ESP32-S3. As a result, you write Wi-Fi applications in Go and flash them directly onto the boards, without going through other languages. The WebAssembly target also remains available, so the same environment covers both the microcontroller and the browser.

The kit sells for 53.54 dollars and includes 11 plug-and-play Grove modules. The XIAO ESP32-C3 board has 2.4GHz WiFi and BLE 5.0, so it covers both network connectivity and connectivity to nearby devices. For anyone who wants to understand how to write a Wi-Fi application in Go on this board, the maker’s site with the TinyGo tutorials is the place to start.

The kit is designed for those who already know Go and want to bring it to hardware, but also for those who want to learn a language different from the usual ones. The combination of a pre-soldered board, plug-and-play modules and official tutorials reduces the barrier to entry to a minimum. The code does the rest.

Source: https://www.seeedstudio.com/tinygo-xiao-starter-kit.html

Related products

• GANIMEDE.E12 ESP12 Board with USB, Wi-Fi, mikroBus and Grove Sockets
• RP2040 Mini Development Board

The post TinyGo Starter Kit with XIAO ESP32-C3: Go Comes to Hardware appeared first on Open Electronics.

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An E-ink e-reader can become a printer. Nishant Joshi has modified the CrossPoint firmware to run the IPP protocol on a reader based on the ESP32-C3. This way the device announces itself to the operating system as a printing peripheral and receives documents without any dedicated software. You just select the printer from your computer and hit print.

The reader presents itself as a monochrome, single-sided printer at 300 DPI on A5 paper. It accepts Apple raster and PWG raster formats, so system drivers need no special translation. The fork also works on the Xteink X4 and Xteink X3, two models built around the ESP32-C3 microcontroller. The project page on Hackaday.io collects Nishant Joshi’s work.

Pixel by pixel, row by row, to avoid saturating RAM

The raster images of an A5 page at 300 DPI are too large for the microcontroller’s memory. So the firmware does not hold them all in RAM. It receives the pixels one row at a time and writes them immediately, both directly to the screen and to the SD card. As a result, the document remains available even after printing.

The fork of the CrossPoint firmware implements the IPP protocol on the ESP32-C3.

The reader announces itself as a monochrome, single-sided printer at 300 DPI on A5 paper.

It accepts Apple raster and PWG raster formats.

The pixels are received and written row by row, because the whole image does not fit in RAM.

Each row ends up both on the screen and on the SD card.

A folder on the SD card acts as the printer’s output tray.

Anyone who wants to rebuild the project starts from an ESP32-C3 module, the same microcontroller that powers the reader. For those looking for a compact board with integrated wireless connectivity there is the SuperMini form factor development module, suitable for IoT and embedded projects. Alternatively, for those who prefer to start from a more complete kit, the catalogue offers a kit based on the ESP32-C6-Zero with Wi-Fi 6 and integrated peripherals.

The folder on the SD card as an output tray

Every printed document ends up in a folder on the SD card. That folder works as an output tray: anyone who wants to re-read a page finds it there, without having to print it again. Moreover, writing to the SD card happens in parallel with writing to the screen, so the reader is not left blocked waiting for the save to finish.

The flow is linear. The operating system sees the printer, sends the job in raster format, the firmware breaks it down into rows and deposits them. Finally the document appears on the E-ink screen and stays archived on the card. No application is needed on the computer, because the IPP protocol is the standard one for network printers.

For those who want to follow the work closely, Nishant Joshi’s project page on Hackaday.io is the starting point. There you will find the fork of the CrossPoint firmware with the IPP implementation and the references to the two supported hardware versions.

Source: https://hackaday.io/contests

Related products

• Mini ESP32-C3 module
• ESP32-C6-Zero Wi-Fi 6 IoT Development Kit

The post Printing from an E-ink e-reader: the IPP firmware on ESP32-C3 appeared first on Open Electronics.

Designers and test engineers should carefully consider an application’s bandwidth requirements before selecting an instrument.

Engineers want accurate measurements over as broad a frequency range as possible. The commonly heard phrase is that measurements should extend from “DC to daylight.” With oscilloscopes offering 100 GHz or more, we are getting closer to that goal. However, several key factors matter when evaluating an instrument’s measurement bandwidth. This article provides some insight into bandwidth.

What is bandwidth?

Bandwidth measures the range of frequencies that an instrument, like an oscilloscope, can measure within a stated measurement accuracy. Bandwidth is measured in units of frequency, Hertz, and its multiples. Bandwidth thus governs the highest and lowest frequencies that an instrument can measure within a specified accuracy. Bandwidth is one aspect of an oscilloscope’s frequency response and is usually displayed as a Bode plot of measured amplitude and phase versus frequency.

When DC-coupled, oscilloscopes have a low-pass frequency response. The shape of that response varies by model. In general, low-cost instruments exhibit a single-pole response with a 6dB-per-octave roll-off. Mid-range to high-end oscilloscopes use what is called a “brick wall” response (Figure 1).

Figure 1 This graph compares an ideal single-pole and measured brick-wall frequency responses.

The single-pole response is the natural response of an analog front end, modeled as a resistor in series with a capacitor. It is a low-pass response that rolls off at -6 dB/octave above its -3 dB upper corner frequency. Its claim to fame is basically low cost.

The brick wall response is achieved using signal processing and has a very high roll-off rate. The intent is to have little signal loss up to the oscilloscope’s bandwidth and then have a high roll-off rate to suppress signals above the instrument’s Nyquist frequency to minimize aliasing. This gives the brick-wall response a wider usable bandwidth because it is flatter up to the instrument’s bandwidth.

Keep in mind that an instrument’s cost is proportional to its measurement bandwidth. Higher bandwidth generally requires specialized components and processing techniques.

Instrument settings that affect bandwidth

Most oscilloscopes offer a choice of input termination impedances; 50 Ohm and 1 Megaohm are common. The instrument’s bandwidth usually varies with the termination; 50 Ohm generally has the greater bandwidth. 

The instrument’s input coupling also affects its bandwidth. An AC-coupled input, intended to suppress DC, will attenuate low-frequency signals below the lower cutoff frequency, usually about 10 Hz, producing an overall band-pass filter response. 

Oscilloscopes also include analog band-limiting filters; typically, the filter bandwidths are 20 and 100 MHz, though this varies across models. Band-limiting filters help reduce noise in some applications.

How much bandwidth do you need?

Bandwidth requirements vary by application. Applications that primarily use sine waves require less bandwidth than those dealing with rectangular pulses. This is because the pulse waveform’s shape depends on multiple harmonics accompanying the signal’s fundamental frequency. For instance, a square wave is composed of a sine wave at the fundamental frequency and N odd harmonics, with the amplitude of the nth harmonic being the reciprocal of the harmonic number, N (Figure 2).

Figure 2 A square wave can be constructed by adding odd harmonics to the sine wave fundamental.

The greater the number of odd harmonics added to the fundamental, the closer the measured waveform approaches an ideal square wave. Current industry standards support having an instrument bandwidth wide enough to accept the fifth harmonic of a digital signal’s clock frequency. So, for a square wave with a fundamental frequency of “F” Hz, the suggested instrument bandwidth should be five times that value, or 5F.

Measurement bandwidth also affects the acquired signal’s rise time. In the single-pole case, the rise time, in seconds, is limited to 0.35 divided by the measurement bandwidth, in Hertz. The rise time of the brick-wall filter depends on the signal-processing algorithm used and varies by supplier and model. For the oscilloscope used in Figure 1, the rise-time limit is 0.45 divided by the bandwidth.

This information will guide the selection of an instrument’s bandwidth based on either harmonic content or required rise time.

Bandwidth and sampling rate

All sampled-data instruments must sample at more than twice the input bandwidth to prevent aliasing. Aliasing is a type of signal distortion in which high-frequency signal components above one-half the sampling rate (the Nyquist frequency) are folded back into the baseband spectrum of a signal (Figure 3).

Figure 3 These graphs compare correctly sampled and undersampled or aliased data acquisition.

A correctly sampled signal has a frequency-domain spectrum in which the baseband signal appears as upper and lower sidebands at multiples (images) of the sampling frequency. As the sampling rate decreases, the image frequencies also decrease and approach zero. If the sampling rate drops below a point where the lower sideband image falls within the instrument’s baseband analog bandwidth, it causes aliased signal distortion. So, keep the instrument’s bandwidth less than one-half the sampling frequency.

Currently available oscilloscopes with long acquisition memory lengths and high sampling rates are less likely to alias, but users should be aware of the possibility.

Can you have too much bandwidth?

In addition to aliasing due to instrument bandwidth, it is very possible to have more bandwidth than you need. Remember that all instruments generate noise and spurious signals. Manufacturers do their best to minimize noise, but it is still present. Much of the noise is spectrally flat broadband, or “white” noise, distributed across the instrument’s bandwidth. As you can imagine, the greater the measurement bandwidth, the greater the noise (Figure 4).

Figure 4 This graph shows the noise contribution to a measurement channel as a function of the channel bandwidth.

The figure shows time- and frequency-domain displays, along with rms noise-level measurements for a common 30 mV rms full-bandwidth noise input across four bandwidths. The top set of traces shows the noise input at the oscilloscope’s full 20 GHz bandwidth. The left-hand graph shows the time-domain trace. The right-hand grid displays the average Fast Fourier Transform (FFT) spectrum of the noise input. The noise spectrum is flat across the full 20 GHz bandwidth.

The lower sets of traces show time- and frequency-domain plots for bandwidths of 4.62 GHz, 1.16 GHz, and 0.32 GHz, respectively. The measurement parameters P1 through P4 measure the standard deviation of each channel’s amplitude. Standard deviation is also known as AC rms because it removes the mean value from the rms calculation, showing only the noise contribution, not the offset. P1 shows the mean rms level of the input noise as 29.7 mV. P2 reads the rms level of the noise band-limited to 4.62 GHz and has a value of 14.8 mV. P3 reads the rms level after filtering to 1.16 GHz as 7.2 mV. P4 reads the rms level for a bandwidth of 320MHz as 3.8 mV.

The peak-to-peak noise levels of the time-domain waveforms decrease as the bandwidth narrows, as seen in the time-domain views. The bandwidths step down by ratios close to 4:1, and the resulting rms levels decrease with bandwidth at approximately 2:1. So the noise level drops as the square root of the bandwidth.

Most mid- to high-range oscilloscopes have low-pass noise-reduction filters, like these, that can be applied to reduce the instrument’s bandwidth and improve the signal-to-noise ratio for signals that don’t require the oscilloscope’s full bandwidth.

Optional filtering applications may also be available, offering low-pass, high-pass, band-pass, and band-stop filters with programmable cutoff frequencies, attenuation, and flatness. These enable custom filter designs matched to the application, reducing noise and improving the signal-to-noise ratio.

Increasing an oscilloscope’s bandwidth

Newer technologies almost always require higher-bandwidth instruments. It is interesting to see how that bandwidth increase can be achieved. Three design techniques can extend a new instrument’s bandwidth. The first is using new, faster semiconductor devices. If you plot the highest bandwidth available in oscilloscopes from the three largest suppliers versus time, you will see that the increase in bandwidth due to improving semiconductor technology increases at an average rate of about 28 percent. This means bandwidth doubles about every 2.8 years. 

Need improved bandwidth sooner than that? Signal processing can moderately increase bandwidth. Equalization is a signal-processing technique that measures an instrument’s frequency response and applies a frequency-dependent correction factor to flatten the channel. The limitation of equalization is basically the increase in noise when gain is used to compensate for attenuation. Signal processing can shape the instrument’s frequency response to improve characteristics such as spectral flatness.

The final approach to increasing bandwidth is to use RF heterodyning to combine multiple channels, each covering a different frequency band, and then combine them. For example, a four-channel oscilloscope with each channel having a 33 GHz bandwidth can be reconfigured to provide two channels, each with a 65 GHz bandwidth (Figure 5).

Figure 5 This block diagram is of a wideband oscilloscope using heterodyning to double the bandwidth of each channel. (Image source: Teledyne LeCroy)

One channel handles the baseband signal up to 33 GHz. The upper band from 33 to 65 GHz is down-converted and applied to the second channel. The two channels are then recombined at a higher sampling rate to produce a single channel spanning 0 to 65 GHz.

Conclusion

The maximum bandwidth of instruments, such as real-time oscilloscopes, ranges from DC to over 100 GHz. The cost of these instruments varies directly with the bandwidth. Designers and test engineers should carefully consider the application’s bandwidth requirements before selecting an instrument.

Arthur Pini is a technical support specialist and electrical engineer with over 50 years of experience in electronics test and measurement.

Related Content

• Oscilloscope rise time and noise explained
• Aliasing, the bane of sampled data systems
• Oscilloscope input coupling: Which should you use?
• Using oscilloscope filters for better measurements

The post Measurement bandwidth appeared first on EDN.

Global automation leader Emerson today announced new radio frequency (RF) test capabilities that help engineers characterize increasingly complex devices and scale automated measurement workflows. The new NI PXIe-5633 four-port vector network analyzer (VNA), together with synchronization-focused software enhancements for the NI PXIe-5860 vector signal transceiver (VST), expands RF validation capability to new multiple-input multiple-output (MIMO) and multiport S-parameter applications within the scalable, software-driven NI PXI platform.

New capabilities will enable engineers to:

• Expand RF validation capacity with four-port vector network analysis capabilities that address more complex device architectures and emerging multiport measurement requirements.
• Address next-generation wireless test challenges through enhanced NI PXIe-5860 synchronization capabilities that support advanced MIMO, multichannel and timing-sensitive RF applications.
• Consolidate measurements within a single system by combining network analysis and modulated RF measurements in one PXI architecture, reducing system complexity and simplifying test workflows.
• Build adaptable test systems for growth with a scalable, software-connected platform that extends automated measurement workflows from design validation through production.

“RF test is no longer only about validating individual components in isolation. As wireless systems become more distributed, software-defined and antenna-intensive, engineers need test architectures that evolve as quickly as the technologies they are validating,” said Kevin Schultz, NI chief technology officer with Emerson’s test and measurement business. “These capabilities reflect our commitment to helping engineers build adaptable test infrastructure that supports system-level validation and future wireless innovation.”

The NI PXIe-5633 extends NI’s existing vector network analysis capabilities to four ports, helping engineers characterize more complex RF devices. As wireless systems increasingly rely on multiple RF paths, synchronized radios and distributed architectures, engineers must characterize interactions across entire systems rather than individual components in isolation. NI PXIe-5860 software enhancements support synchronization-focused and MIMO workflows for increasingly complex wireless test requirements.

Engineers can also perform S-parameter characterization alongside modulated RF measurements through a single RF connection. Combining these measurements in one software-driven PXI system can reduce the need for separate instruments and test setups while maintaining a consistent path for automation.

The new capabilities are being featured in booth A40B at European Microwave Week in a 4×4 MIMO demonstration using the NI PXIe-5860 and the four-port VNA. Applications span semiconductor validation, advanced wireless research, aerospace and defense systems and other RF-intensive technologies increasingly built around multi-antenna, multichannel and software defined architectures.

The post Emerson Extends RF Test Capabilities to New Multiport and MIMO Test Applications appeared first on ELE Times.

​AI is no longer just creating chatbots; now it can plan, use external tools, scrape data, and perform multi-step processes. Frameworks for creating AI agents are making this possible. AI agent frameworks are software suites for designing, prototyping, orchestrating, debugging, and deploying AI agents.

These frameworks mean that in 2026, you will be able to rapidly prototype new AI agents or create operational AI agents for complex workflows, multi-agent workflows, and enterprise-scale applications. Here are 10 popular frameworks and why to use them.

1. LangGraph

Created by LangChain, LangGraph is a framework for building stateful AI agents with granular control over execution. It incorporates a graph-based structure that manages new execution flows with conditional logic, persistence, human approval, and the ability to recover from interruption. It’s ideal for enterprise use and long-term agents.

2. CrewAI

CrewAI is a collaborative, role-based platform for managing multi-agent artificial intelligence. For multi-AI applications, coders can assign each agent its own role and then group them into teams to conduct research, analysis, content creation, or run a business. It has a very simple product design and user interface for fast prototyping.

3. OpenAI Agents SDK

The OpenAI Agents SDK allows you to construct agents that invoke functions, hand off tasks between agents, and utilize guardrails. It includes tracing, which allows you to observe agent behaviour and debug your application’s flow. A good choice for applications with tool use and multiple agents in collaboration.

4. Google Agent Development Kit (ADK)

The Google Agent Development Kit (ADK) can be used to develop, test, and deploy your AI agents- or multi-agent systems. The kit has a modular architecture, supports integrations with popular tools and coding languages (Python, TypeScript, Go, and Java), and may be useful for people building Gemini apps or using Google Cloud.

5. Microsoft Agent Framework

Microsoft Agent Framework offers the combined features of AutoGen and Semantic Kernel. It can implement single agents, multi-agent workflows, memory, tool integration, and human-in-the-loop execution. It supports Python and .NET​, the latter being useful for organisations building AI in the Microsoft ecosystem and on Azure.

6. LlamaIndex

LlamaIndex is a great fit for document-focused or enterprise knowledge agents. Its indexing and retrieval features, as well as data connectors, allow developers to create search functions over internal data or information, as well as generate context sensitive responses. It’s a good choice for RAG and document analysis tools or research assistants.

7. Mastra

Mastra is a TypeScript framework for creating AI agents and applications. It supplies tools to developers for creating agents, workflows, and integrations in the JavaScript/TypeScript ecosystem. This is mainly for teams creating AI based mostly web apps without a separate Python agent layer.

8. Pydantic AI

Type-safe application development for AI with structured data validation. Pydantic AI empowers developers to author and verify expected output, compose tools, and develop applications where the interface to the language model is more explicit and predictable than standard software. It is particularly relevant for Python teams looking for predictable data validation and maintainability.

9. Haystack

Haystack, a deep-set built tool, is a modular framework designed for developing AI applications with pipelines, retrieval, and agent components. Document search and processing, search, and RAG are all features of the tool. Developers can leverage search with tool use to develop knowledge-intensive chatbots and business information systems.

10. Claude Agent SDK

The Claude Agent SDK from Anthropic offers a set of primitives to build agents based on Anthropic’s Claude models. It provides support for tool-based workflows and integrations that might be useful for coding, file workflows, and research-based use cases. Review the model provider requirements and tool permissions before selecting this option.

How Should Developers Choose an AI Agent Framework?

The best framework for you will depend on your use case, programming language, provider, and operational needs: complex, stateful workflows might use LangGraph; CrewAI is a good choice for role-oriented, collaborative workflows; OpenAI Agents SDK provides an easy-to-implement path to tool-using agents; Google ADK is best if you’re in the Google Cloud world; for document-centric workflows, check out Llama Index and Haystack.

For TypeScript teams, Mastra; for anyone who loves typed Python, Pydantic AI; and for enterprise solutions, Microsoft Agent Framework. You’ll want to consider documentation, observability, security controls, deployment options, licensing, and ongoing costs. You don’t necessarily need an agent framework- a single model invocation or a traditional ETL-style workflow may be simpler to run.

Conclusion

Frameworks for AI agents are emerging as essential components of applications that require more than text generation. They help developers leverage AI capabilities into functional software by reducing the complexity of tool integration, orchestrating workflows, managing context across multiple agents, and orchestrating multi-agent systems. There’s no single best option. The best framework depends on the scale, complexity, technical stack, reliability requirements, and costs of your project.

The post Top 10 AI Agent Frameworks for Developers in 2026 appeared first on ELE Times.

Rapid technological acceleration and shifting regulatory landscapes warrant robust governance, risk management, and workforce readiness, skill development, essential to build national cyber resilience. Anwesh Koley of ELE Times interacted with key leadership from ISACA, who shared strategic perspectives on India’s evolving cybersecurity posture, the impact of legislative initiatives and the pressing need to bridge the domain’s skills gap.

ELE Times: At the onset, could you brief us on what is currently happening at ISACA regarding cybersecurity, governance, risk, compliance, and related fields?

Team ISACA: This is a pivotal moment for cybersecurity in India. Over the last five years, the government has made multiple moves indicating a clear focus on increasing national cyber posture and resilience.

Crucial legislation like the Digital Personal Data Protection (DPDP) Act has been pivotal. Furthermore, traditional regulators such as the Reserve Bank of India (RBI) and the Securities and Exchange Board of India (SEBI)—particularly within financial services—have consistently remained at the forefront of cybersecurity enforcement. Across sectors, there is expanding interest in skill development, awareness, and building a deeper appreciation of what constitutes a robust cybersecurity program.

However, the ecosystem remains fragmented. A wide spectrum of policymakers and regulators operate with varying levels of understanding regarding how cyber risks impact their specific sectors. While entities like CERT-In and the National Cyber Security Coordinator serve as positive signals, the lack of a single, unifying national body to tie these initiatives together leads to disparate, localised pockets of progress rather than a fully unified national strategy.

On artificial intelligence, the implementation across sectors is similarly experiencing fragmented approaches. While there is currently no plan to introduce national AI legislation in India—keeping the focus intentionally on fostering innovation—the rapid pace of AI adoption makes AI security and enterprise governance frameworks critical.

Finally, addressing the skills gap remains essential. Building a well-qualified workforce requires continuous, innovative development initiatives to establish standard capabilities across all domains.

ELE Times: You raised the important issue of skill development. What specific avenues is ISACA focusing on, and where does India feature in your strategic plans regarding quality skill development?

Team ISACA: India is a critical jurisdiction for ISACA, and our organisation is making significant strategic investments here. India represents our largest concentration of staff outside North America. Beyond building local cybersecurity postures and AI capabilities, India aims to leverage cybersecurity and AI as economic growth levers to position itself as a regional technology leader. We actively support this vision alongside our local network of 10,000 members organised across 12 chapters.

There is an important opportunity for India to make the cybersecurity sector a national economic success story, mirroring its historical success in the software and IT services industry.

Skill development extends beyond pure-play cybersecurity specialists; there is surging demand for cybersecurity expertise in adjacent corporate roles—including procurement, legal, project management, and executive board governance. Beyond specialised operational roles, building a robust national talent pool enables the creation and export of domestic cybersecurity products and services.

To support these goals, ISACA delivers a multi-pronged approach:

• Extensive Credential Portfolio: Offering structured pathways from foundational competencies through to specialist credentials, including new certifications designed as entry points into cybersecurity careers.
• Enterprise Governance & Benchmarking Frameworks: Providing frameworks (such as COBIT) that allow enterprises to review, assess, and benchmark their maturity in adopting AI, IT controls, IT audit assurance, and governance.
• Continuous Learning & Local Framework Alignment: Moving away from static, one-time certifications toward mandatory, continuous professional education (CPE). Additionally, our credentials and workforce frameworks adapt to local regulatory requirements to ensure seamless regional implementation.

ELE Times: How do you assess the current Indian workforce and its preparedness toward accepting cybersecurity norms and building long-term careers in this domain across various industry verticals?

Team ISACA: Workforce preparedness varies across sectors. Industries like financial services have made substantial investments, and critical infrastructure sectors are actively advancing their capabilities. However, operational challenges remain, particularly within public sector capacity and municipal-level infrastructure where personnel manage multiple operational responsibilities.

A central challenge is the sheer speed at which the field evolves. Rather than replacing cybersecurity roles, technologies like AI are reshaping job requirements rapidly. Cybersecurity professionals must continually adapt to keep pace with emerging technology stacks.

Additionally, growth is accelerating in intersecting domains like risk management and regulatory compliance. Navigating this environment demands an agile mindset and a commitment to continuous learning to stay ahead of evolving threats and technological shifts.

ELE Times: Expanding beyond India, how do you see the broader South Asian and regional markets performing in terms of cybersecurity readiness and willingness to adopt scaling frameworks?

Team ISACA: India acts as a primary technology and policy leader across South Asia. While smaller regional jurisdictions can sometimes move faster due to scale, there is a widespread recognition across South Asia that robust cybersecurity adoption is mandatory to participate effectively in the global digital economy.

Beyond South Asia, regions like the Middle East—Saudi Arabia in particular—are moving rapidly to establish strong national cybersecurity profiles. India holds a strong position to offer thought leadership and drive regional dialogue across these markets.

Regarding the willingness to adopt cyber norms and frameworks across the region, industry resistance is rarely the barrier. Instead, organisations face challenges around regulatory proliferation and a lack of harmonisation.

When enterprise teams must navigate overlapping, unaligned compliance requirements from multiple authorities, compliance becomes burdensome. Diverting technical staff and financial resources purely toward administrative compliance exercises can take focus away from vital operational security tasks—such as active risk management, system patching, and continuous monitoring.

The industry is receptive to regulation, standards, and guidance. However, the priority must be regulatory coherence and harmonisation so that compliance directly drives meaningful improvements in an organisation’s overall security posture.

The post Advancing Cyber Posture, Governance, and Skill Development in India and Beyond appeared first on ELE Times.