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The TPM1R408RH 80-V N-channel MOSFET is built on Toshiba’s latest-generation low-voltage U-MOS11-H process. It features an optimized device structure with an RDS(on) of 1.4 mΩ—about 26% lower than the 80-V TPM1R908QM based on the previous-generation U-MOS X-H process. It also improves the RDS(on)-Qg tradeoff, reducing figure of merit by ~45% versus the TPM1R908QM.

These reductions lower power loss in switch-mode power supplies for industrial equipment such as AI data centers and communication base stations. The TPM1R408RH also suppresses drain-source voltage spikes during switching, reducing EMI. This helps minimize late-stage design rework and simplifies filter and snubber circuits.

The MOSFET is supplied in the SOP Advance(E) package, which delivers approximately 65% lower package resistance and approximately 15% lower thermal resistance than Toshiba’s current SOP Advance(N) package. This reduces conduction losses and improves thermal performance, enabling higher power density in compact power supply designs.

The TPM1R408RH is available through Toshiba’s authorized on-line distributors.

TPM1R408RH product page 

Toshiba Electronic Devices & Storage 

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Infineon’s AIROC UWB TSL100 SoC enables centimeter-level distance measurement and localization using ultra-wideband (UWB) time-of-flight (ToF) technology. Designed for low-power, secure operation, the device targets automotive, consumer, and industrial applications such as secured vehicle access, in-cabin presence detection, contactless payment and ticketing, and industrial asset tracking and collision avoidance.

The TSL100 is the first member of a scalable UWB product family intended to align with upcoming standards such as IEEE 802.15.4ab. It includes a CCC-, FiRa-, and Aliro-compliant MAC. The PHY delivers 48-bit FiRa and CCC security in challenging non-line-of-sight conditions, detecting and verifying direct paths up to 100,000 times weaker than reflected paths.

The SoC enables more than two years of coin-cell battery life in CCC ranging schemes for key fobs, achieved through a dedicated low-power mode that reduces current consumption by more than 50%. Its RF architecture extends sensing functions to presence detection, kick sensing, intrusion detection, and NCAP scenarios. Additionally, AIROC zoning technology enables configurable unlock zones and inside/outside detection for Aliro-enabled smart locks.

Engineering sample kits for the AIROC UWB TSL100 are available upon request.

AIROC USB TSL100 product page 

Infineon Technologies 

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ST’s ST54M integrates a post-quantum cryptography (PQC) hardware accelerator, NFC controller, secure element, and eSIM on a single die. The chip helps smartphone and personal electronics manufacturers prepare for future post-quantum security requirements while enabling secure mobile connectivity. Applications include contactless payment, transit ticketing, access control, digital identity, and mobile driver’s licenses.

The ST54M’s hardware accelerator supports PQC algorithms such as ML-KEM and ML-DSA, aiding the transition from hybrid cryptographic approaches to full post-quantum deployment. It also helps protect against side-channel and fault-injection attacks and addresses emerging PQC requirements.

Based on an Arm Cortex-M3 32-bit MCU, the contactless front-end provides NFC card emulation, reader/writer, and peer-to-peer communication modes. It increases RF communication distance, simplifies NFC integration, and supports efficient low-power operation. An integrated step-up DC/DC converter enables transmit drive up to 3 W.

Samples are available now. Production and Common Criteria 2022 EUCC and EMVCo certifications are targeted for July 2026.

ST54M product page 

STMicroelectronics

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The Melexis MLX91229 Hall current sensor provides a second-order sigma-delta digital output that improves signal integrity in EV traction inverter applications. Optimized for automotive systems, this output tolerates heavy EMI, helping maintain signal integrity over longer PCB traces or wiring where electrical noise can introduce disturbances between the sensor and MCU.

Unlike analog sensors, the MLX91229 encodes measured current into a sigma-delta bitstream, with information represented by the density of digital pulses rather than absolute voltage levels. This encoding makes the signal inherently more resistant to electrical noise during transmission to the MCU. Because demodulation is performed in the host MCU, designers can optimize the tradeoff between fast overcurrent detection and high-accuracy current measurement.

Supporting current sensing from 200 A to 2000 A, the MLX91229 measures peak magnetic fields from 11 mT to 400 mT. It uses Manchester-encoded data transmission over differential RS-422 or LVDS interfaces. The AEC-Q100-qualified sensor operates over an ambient temperature range of –40°C to +125°C and is powered from a selectable 3.3-V or 5-V supply.

The MLX91229 is available in a 4-pin SIP through authorized distributors and is designed as a drop-in replacement for conventional analog sensors.

MLX91229 product page 

Melexis

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submitted by /u/jones_supa
[link] [comments]

Dynex Semiconductor Ltd of Lincoln, UK has developed a 450A, 650V gallium nitride (GaN) half-bridge power module, designed to deliver ultra-fast switching performance, high efficiency, and enhanced thermal management for demanding power conversion applications...

Старт другого Міжнародного конкурсу інноваційних проєктів Melville Sikorsky Challenge Accelerator kpi ср, 07/01/2026 - 17:31

Як університету готувати фахівців, яких індустрія телекомунікацій потребує вже сьогодні? KPI4U-2 ср, 07/01/2026 - 17:09

КПІ ім. Ігоря Сікорського — у трійці лідерів академічного рейтингу «Топ-200 Україна 2026» KPI4U-2 ср, 07/01/2026 - 17:06

A linearized output is a useful elaboration of a capacitive sensor design. But what if the circuit is located a significant distance from the control electronics?

Recently, Design Ideas included a circuit that comprised a simple analog interface to basic capacitive position sensors. Figure 1 shows its minimal six parts topology with complementary outputs: Out and –Out.

Wow the engineering world with your unique design: Design Ideas Submission Guide

Figure 1 U1a and U1b cross-coupled Schmidt trigger timers form a ~1MHz RC multivibrator. The Tsense pulse width is inversely proportional to sensor displacement Tref/Tsen = Cref/Csen = d.

Doubling the parts count to 12 transmogrifies Figure 1 into Figure 2 and provides a linear voltage mode output,  Then, with the exemplar 38mm-diameter sensor plate capacitor connected, separation d between plates reads out as d = (Vout – 1) = 0 to 4 millimeters as Vout goes from 1 to 5v.  Vout ripple is just half a millivolt pk-pk. The linear voltage output modification is described in this Design Idea.

Figure 2 Averaging integrator A1 implicitly computes the output voltage needed to linearly balance the charge transferred onto C1 during Tref through discharge during Tsense. Vout = Tref / Tsense  + 1 = Cref / Csense + 1 = d + 1.

So, let’s take it as granted that providing a linearized output was a useful elaboration of the original design.  But suppose the capacitive sensor is located a significant distance from the control electronics.  Voltage mode analog outputs are notoriously vulnerable to noise pickup and disturbances like ground loop voltage differentials.  What to do then?  Figure 3 shows a simple and plausible remedy.  It’s a classic, if I do say so myself.  A noise- and cable length- tolerant, linear 4 to 20mA, current mode output.

Figure 3 Dangling the TLV431 shunt voltage reference Z1 from the 15 volt supply is a shortcut toward implementing a noise- and cable length- tolerant current mode output.

Here’s how it works. Figure 3’s A1 integrator generates a 1 to 5 volt linear output, much like Figure 2’s A1 does.  The difference is this 1 to 5v is inverted, referenced to +15v, and developed across 249ohm current sense resistor R5.  It’s therefore an accurate readout of Pfet Q1’s 4 to 20mA source current.  Shunt reference Z1 provides both the 1.00v integrator reference and a 5v step-down supply for U1 and U2.  DC blocking C4 and R9 trickle protect the chips from being instantly fried in case the sensor capacitor plate shorts to ground.

Some random remarks: U1’s unused inputs should be tied to +15v.  C1, 2, 3, and 4 should be rated for the full supply voltage, which itself isn’t critical but shouldn’t exceed 20v.  Otherwise Q1’s gate will be at risk for over-voltage if the load becomes disconnected.  If  the supply equals 15v as shown, voltage compliance and consequent ground noise resistance is >9v. Iout ripple is ~0.01% pk-pk.  Figure 4 shows the net nicely linear response.

Figure 4 In this graph, black = sensor readout d in mm, and red = the nicely constant 4 microamps per micrometer resolution.

Stephen Woodward‘s relationship with EDN’s DI column goes back quite a long way. Over 200 submissions have been accepted since his first contribution back in 1974.  They have included best Design Idea of the year in 1974 and 2001.

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Нотатки з семінару Секції вихованців КПІ у Польщі 2026 Інформація КП ср, 07/01/2026 - 13:00

I recently purchased a new Rohde&Shwarz RTB2 scope. 300MHz and 10bit ADC with a lot of extra software options :). almost 50% off At the same time i purchased 2 new soldering stations from JBC to power a T245 and T210 soldering irons. Also i got the idea to put a small 7" screen close to my microscope to make work easier under the micropscope. As example i have designed a USB output adapter for bench power supplies, USBpwrME which can be found on DIY different sites when googled. I wanted to measure a specific pin on a IC. I magnified this IC on the 7" screen and then it was really easy to follow the pins and pcb traces on the screen while measuring :) Love my lab setup 😂 submitted by /u/KS-Elektronikdesign [link] [comments]

⭐ Вступ до магістратури 2026 kpi ср, 07/01/2026 - 12:00

🔔 Вступ до аспірантури 2026 kpi ср, 07/01/2026 - 08:30

Private rare-earths exploration and process development company US Critical Materials Corp (USCM) of Salt Lake City, Utah, USA (which is dedicated to advancing high-grade domestic sources of rare-earth elements and critical minerals essential to US national security, supply chain independence, and advanced manufacturing) has announced several major milestones: the relocation of its corporate headquarters to Darby, Montana; key leadership appointments; and the launch of a new public information website for the Sheep Creek Project in Montana...

Keysight Technologies Inc of Santa Rosa, CA, USA and WIN Semiconductors Corp of Taoyuan City, Taiwan — which provides pure-play gallium arsenide (GaAs) and gallium nitride (GaN) wafer foundry services for the wireless, infrastructure and networking markets — have announced a joint monolithic microwave integrated circuit (MMIC) design workflow that enables GaN MMIC design houses to achieve first-pass tapeout success. The workflow connects on-chip multi-domain simulation, 3D layout with verifications, and off-chip MMIC evaluation board design into a single environment. It supports the growing number of companies developing GaN MMICs for 5G base stations, Wi-Fi access points, satellite payloads, and defense radar systems...

In first-quarter 2026, patent activity in silicon carbide (SiC) technology remained particularly dynamic, both upstream in substrates and epitaxial wafers and downstream in power devices and modules, according to technology intelligence and IP strategy consulting company KnowMade in two new patent monitoring services dedicated to SiC technology:...

Hello everyone! I have made myself a simple function generator controlled by a raspberry pi Pico w. It's my first proper PCB work, as I have done one in the past but it was my first and had alot of mistakes. This one looks proper aswell, made it in altium and just wanted to share. If you're interested you can see Schematics / PCB and Github. Just finished second year of ECE. submitted by /u/S4vDs [link] [comments]

Почесна відзнака Вченої ради КПІ ім. Ігоря Сікорського Григорію Лупаренку KPI4U-2 вт, 06/30/2026 - 17:30

Advanced AI systems are forcing the semiconductor industry to rethink the boundary between silicon, package, board, power delivery, memory, cooling, and manufacturing. For several years, the dominant discussion has centered on advanced packaging capacity, high-bandwidth memory (HBM) integration, large interposers, organic substrate constraints, glass-core substrates, and scaling limits of 2.5D and 3D integration.

That discussion remains valid. But a deeper system question is emerging. What happens if the package substrate is no longer the center of the system-integration hierarchy? This question becomes especially important when comparing three architectural directions:

• CoWoS-style 2.5D integration
• Wafer-scale integration
• CoWoP/chip-on-wafer-on-platform-PCB concepts

Each approach is trying to solve the same industry problem: how to scale AI compute density, memory bandwidth, transient power delivery, thermal control, and multi-die integration beyond the physical limits of conventional packaging stacks. However, each architecture moves the bottleneck to a different place.

Chip-on-Wafer-on-Substrate (CoWoS) makes advanced packaging central to AI and high-performance compute (HPC) scaling. Next, wafer-scale integration pushes silicon integration to the extreme. Finally, Chip-on-Wafer-on-PCB (CoWoP) may create a new middle architecture where the platform PCB becomes part of the governed realization corridor.

Therefore, it’s not only a packaging phenomenon; it’s also about system realization.

CoWoS: The proven advanced packaging path

CoWoS has become one of the most important advanced-packaging architectures for AI accelerators and HPC silicon. It enables logic die, HBM stacks, and high-density interconnect to be integrated through an interposer and then connected to a package substrate and board.

The strength of CoWoS is apparent. It provides high-density die-to-die and die-to-HBM connectivity, supports large AI/HPC modules, and has become a production-proven integration path for high-bandwidth systems. However, CoWoS also exposes the limits of the modern package stack. See the complex corridor below:

Die/HBM → interposer → package substrate → PCB → voltage regulator module (VRM)/system

The package substrate must support escape routing, power delivery network (PDN) distribution, coefficient of thermal expansion (CTE) transition, mechanical stability, manufacturing yield, decoupling strategy, signal integrity (SI)/power integrity (PI) control, warpage management, and board attach reliability. And as package size increases, these challenges become more critical.

Many of the hardest problems in advanced AI packaging aren’t located in silicon; they occur in the package and package-to-board realization path.

• Warpage
• Substrate availability
• Package size
• Thermal gradients
• PDN impedance
• Loop inductance
• dI/dt response
• Decoupling placement
• SI/PI discontinuities
• Manufacturing complexity

In other words, CoWoS is powerful, but the package substrate becomes a major convergence burden. This is why glass-core substrates are receiving so much attention.

Glass substrates help, but they don’t remove corridor

Glass can improve dimensional stability, reduce warpage, provide better CTE control, support finer routing environments, and improve vertical power-delivery paths with through-glass vias (TGVs). For large AI/HPC packages and future electro-optical integration, these advantages are meaningful.

But glass should not be treated as a complete escape from package realization complexity. In most practical glass-core substrate architectures, the glass is primarily the core and the build-up layers still there. That means many high-speed routing-density challenges remain concentrated in the top build-up structure.

Moreover, bottom-side routing through the core is still not equivalent to short top-side interconnect. Signals passing through TGVs and returning through lower layers still face discontinuities, parasitics, reference-plane challenges, and SI/PI governance requirements.

So, glass changes the package problem, but it does not eliminate it. This distinction matters because CoWoP is not simply about replacing one substrate material with another. It’s about asking whether the realization hierarchy itself can change.

Wafer-scale integration: The extreme silicon path

Wafer-scale integration takes a different route. Instead of assembling many dies through a package-level integration strategy, it expands the silicon system itself. The result is an extremely large compute fabric with direct wafer-level integration, specialized power delivery, cooling, redundancy, and system infrastructure.

This can be technically powerful because it removes many conventional package boundaries and creates a very large on-wafer compute fabric. At the same time, however, wafer-scale integration does not eliminate realization complexity. It relocates it.

The board, power architecture, cooling system, mechanical structure, redundancy strategy, yield-management approach, and system-level service model must all adapt around a very large silicon platform. A useful way to summarize the difference is that wafer-scale integration expands silicon until the system must adapt around it. That can be attractive for certain AI workloads and specialized systems, but it’s not necessarily the most flexible path for every AI accelerator, custom ASIC, chiplet platform, or memory-rich architecture.

CoWoP: A possible middle architecture

CoWoP is interesting because it may offer a third path. Instead of the traditional path comprising die/HBM, interposer, package substrate and PCB, CoWoP points toward a shorter realization path.

Die/HBM → interposer/wafer-level structure → platform PCB

The deeper architectural value is not simply cost reduction. The deeper value is that CoWoP may change the power, memory, mechanical, and system-realization architecture. If the package substrate is reduced or removed, the system no longer needs to carry as much of the convergence burden through three separate layers: interposer, package substrate, and PCB.

Instead, the corridor becomes more direct. However, this directness should not be oversimplified. A realistic CoWoP architecture cannot simply assume that a fine-pitch silicon interposer can land directly onto a platform or PCB without a transition strategy.

The most important challenge may be the transition between wafer/interposer precision and PCB manufacturability. That transition may define whether CoWoP becomes a practical system architecture or remains only an attractive concept.

Dr. Moh Kolbehdari is senior director of IC/packaging at Socionext US.

Editor’s Note

This is Part 1 of the mini-series on advanced packaging. Part 2 continues with the advanced CoWoP concept: pitch translation, transition patches, VRM and memory placement, UCIe routing, and trusted realization governance.

Related Content

• True Wafer-Level Packaging
• Wafer Level Chip Size Package (WLCSP) Guidelines
• Intel’s Embarrassment of Riches: Advanced Packaging
• Nvidia, TSMC, and advanced packaging realignment in 2025
• Intel flash move could put wafer-level packages on the map

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