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Infineon Technologies AG of Munich, Germany is advancing its collaboration with NVIDIA on 800V direct current (VDC) power architectures for AI data centers. Timed to coincide with NVIDIA’s GTC Berlin developer conference on 20–22 October, the announcement centers on the high-voltage intermediate bus converter (IBC), one of the most critical and demanding conversion stages in the power delivery chain of AI data centers...

Photonic integration firm Photon Bridge of Eindhoven, The Netherlands has raised €10m to tackle the emerging bottleneck in AI infrastructure: producing the millions of lasers that will be needed to connect increasingly large clusters of AI processors...

Defense-grade Agilex FPGAs and SoC FPGAs from Altera operate reliably in harsh environments across a temperature range of -55°C to +125°C. Leaded-ball and ruggedized packaging options are designed to withstand temperature cycling, vibration, and shock in mission-critical aerospace and defense applications.

The defense-grade devices will span Altera’s entire Agilex portfolio, from cost-optimized Agilex 3 FPGAs to mid-range Agilex 5 and high-performance Agilex 7 and Agilex 9 Direct RF-Series FPGAs. The portfolio addresses varying requirements for performance, power efficiency, and integration in applications ranging from embedded processing to high-bandwidth communications, sensing, and electronic warfare. A common architecture lets designers adapt their systems as mission requirements evolve.

Altera’s HyperFlex architecture uses Hyper-Retiming and Hyper-Pipelining to balance pipeline delays and shorten critical logic and routing paths. These techniques enable higher clock frequencies and greater processing throughput.

Fabrication in the United States provides a domestic source of wafer production, supporting supply-chain resilience for aerospace and defense programs with long service-life requirements.

Initial shipments of defense-grade Agilex FPGAs are scheduled for Q1 2027. Contact an Altera sales representative for additional information.

Altera

The post Altera extends Agilex FPGAs to defense systems appeared first on EDN.

The Synaptics Astra SR200 series of xMCUs runs multimodal AI workloads without the memory and compute limitations of conventional MCUs. Devices combine heterogeneous, AI-native compute and acceleration with integrated high-bandwidth custom DRAM scalable to hundreds of Mbytes. This allows larger AI models and richer multimodal workloads to run entirely on-device.

Powered by Synaptics’ Torq AI engine with Google Research’s transformer-capable Coral NPU, the xMCUs deliver up to 400 GOPS of AI inference. They also feature Arm Cortex-M85 and Cortex-M52 cores, integrated vision and audio capabilities, and hardware-rooted security. A tiered architecture pairs up to 8 Mbytes of SRAM with extensible, high-bandwidth, high-capacity custom DRAM. Synaptics says this architecture runs workloads at one-third the power of typical system DRAM.

The Astra SR200 series comprises three pin-compatible product lines sharing a common hardware foundation and SDK. The SR210 reaches 200 GOPS for always-on voice and sensing; the SR230 adds vision, display, and optional audio at 300 GOPS; and the SR250 provides 400 GOPS with dual vision and display paths for demanding edge applications.

Locate a distributor or sales office here.

Astra SR200 product page 

Synaptics

The post MCUs accelerate multimodal edge AI appeared first on EDN.

Microchip’s POL-05-20S-T GaN point-of-load converter delivers up to 20 A of continuous current to power FPGAs, MCUs, and other processing-intensive digital loads in space. The radiation-tolerant device uses GaN power HEMTs to achieve high efficiency and power density in a compact, lightweight form factor, helping engineers meet the size, power, and energy constraints of onboard processing systems.

A synchronous buck topology with current-mode control provides fast transient response and stable operation. The 4.75-V to 13.2-V input range and adjustable 0.7-V to 5-V output accommodate multiple power rails and system architectures.

The POL-05-20S-T’s electrical parameters are specified before and after irradiation up to 50 krad(Si), and its single-event effects (SEE) have been characterized up to a linear energy transfer (LET) of 43 MeV·cm²/mg. The converter operates at full load over a temperature range of −55°C to +100°C.

Housed in a 1.51×1.51×0.45-in. surface-mount package, the POL-05-20S-T is now available in production quantities.

POL-05-20S-T product page 

Microchip Technology 

The post Rad-tolerant GaN converter powers space electronics appeared first on EDN.

BrainChip’s Sequora processor IP core runs generative AI and large language models (LLMs) directly on battery-powered edge devices, such as earbuds and sensor nodes. It pairs with the company’s Akida neural processor IP to handle complementary AI workloads.

Akida processes streaming sensor data, including vibration, audio, radar, raw RF IQ data, and biological signals. Sequora runs generative and sequential AI tasks, from on-device LLM inference to voice-to-voice interaction and AI agents. It is optimized for state-space models (SSMs), which maintain a fixed-size state to represent input history, keeping memory requirements constant regardless of sequence length. This architecture suits generative AI workloads on resource-constrained edge devices.

Sequora uses a unified multiply-accumulate (MAC) array for both signal processing and neural-network computation, eliminating the need for a separate DSP preprocessing stage. Its instruction-set architecture (ISA) also allows new algorithms to be deployed through software updates.

Sequora is available now as licensable semiconductor IP, delivered as process-portable, fully synthesizable RTL. The package includes verification IP, synthesis scripts, and an SDK with a compiler, C++ runtime library, and model zoo.

Sequora product page 

Brainchip Holdings   

The post Processor IP brings generative AI to edge devices appeared first on EDN.

AMD Helion is a rack-scale reference design for agentic AI infrastructure, combining open-source hardware and software. The design accommodates CPU-only configurations for hyperscale deployments and CPU/GPU configurations for enterprises. Based on Open Compute Project (OCP) specifications, the Helion 21-in. rack architecture lets customers balance CPU and GPU performance, core density, and power consumption to meet their application requirements.

A CPU-only rack can be powered by AMD EPYC processors supporting up to 32,768 Zen 6 x86 CPU cores. The all-in-one rack integrates AMD EPYC CPU nodes, up to 16 AMD Instinct MI350 GPU nodes, and general-purpose compute. A token router directs inference requests to frontier models in the cloud or open-source models running locally in the rack.

AMD plans to contribute the Helion specification to OCP for community development and adoption. Rack configurations are under development with ecosystem partners, with availability planned for November 2026.

Helion product page

AMD

The post AMD defines rack-scale infrastructure for agentic AI appeared first on EDN.

💥 Опитування про відкриту науку від Open4UA kpi ср, 10/21/2026 - 17:33

Teradyne is expanding the UltraFLEXplus platform with three new instruments designed to meet the increasingly complex testing needs of semiconductors destined for AI and data centers. The new UltraPin5000-EM, UltraPort-PCIe6 and UltraVS64-HP solutions introduce advanced capabilities in terms of speed, processing, precision and power management, keeping pace with the evolution of next-generation devices.

Particularly notable are the power-related performance figures of the UltraVS64-HP: up to 1,280 amperes per instrument, 5,120 amperes in a ganged configuration and more than 15,000 amperes overall for a test cell. These values give a measure of Teradyne’s ability to address the testing requirements of increasingly powerful and energy-intensive AI and computing devices.

Below is the press release with more information on the three new solutions.

Teradyne expands the UltraFLEXplus platform with new instruments for testing AI and data center devices

A suite of instruments delivers speed, power and precision to meet the new challenges of testing devices for AI and data center applications.

Teradyne, Inc., a leading supplier of automated test systems for electronics and advanced robotics, has announced the launch of three new instruments for its UltraFLEXplus platform, designed to meet the increasingly complex testing needs of semiconductors destined for artificial intelligence and data centers.

The UltraPin5000-EM, UltraPort-PCIe6 and UltraVS64-HP instruments are designed to deliver unprecedented scalability, flexibility and performance, enabling semiconductor manufacturers to verify the most advanced devices with maximum efficiency and accuracy. Together, these instruments aim to strengthen Teradyne’s position across the entire supply chain for AI devices, from the first wafer probing stage through to final rack validation, ensuring that the components used in a data center for AI applications meet the quality standards required by the industry.

“With the AI and data center market driving unprecedented growth in semiconductor complexity, Teradyne remains committed to delivering innovative solutions that enable our customers to maintain a competitive advantage in this rapidly evolving market,” said Greg Smith, CEO of Teradyne. “This new suite of instruments expands the capabilities of our UltraFLEXplus platform, delivering cutting-edge, future-proof solutions for testing next-generation devices.”

UltraPin5000-EM

The UltraPin5000-EM board is Teradyne’s next-generation digital instrument, designed specifically to meet the needs of AI and advanced computing devices that require a large number of test patterns. With vector memory up to 80 times greater than other solutions available on the market, it makes it possible to test even the most complex AI application devices, while ensuring the ability to support future innovations. Pattern loading is up to 10 times faster, while the new Persistence Mode operating mode enables near-instantaneous reloads, giving designers the ability to speed up debug and characterization activities and production departments the ability to improve equipment efficiency.

UltraPin5000-EM guarantees excellent signal integrity at data transfer rates of 5 Gbps, achieving high and reliable throughput of high-bandwidth patterns, while its flexible timing architecture supports independent clock frequencies for each pin, adapting to the different requirements of heterogeneous devices. Accelerated scan chain operation makes it possible to obtain per-core results in real time, enabling immediate adaptive test decisions and reducing the time needed to perform structural tests without compromising coverage. Compatible with the UltraPin2200 board, the new UltraPin5000-EM model protects customers’ existing investments while offering the scalability needed to meet the requirements of new, more advanced devices.

UltraPort-PCIe6

UltraPort-PCIe6 is the first high-speed ATE solution for verifying the I/O protocols of PCIe Gen6 interfaces, capable of reaching 64 Gbps (PAM-4) on 32 lanes per instrument. Excellent signal integrity performance, combined with a dedicated PMU (Power Management Unit) block for each pin and built-in loopback functionality, ensures greater test coverage, broader diagnostic capabilities and the cleanest signal path to the device, making it possible to configure test systems quickly and keep them stable in production. A dedicated server-class compute backend can scale up to 2 TB of high-performance memory, processing larger test data sets for faster test cycles.

The instrument supports both mission mode testing and high-speed I/O scanning, making it possible to shift part of the functional test coverage to earlier stages of the process, increase confidence in qualifying Known Good Die and reduce waste of HBM memory chips and high-value advanced packaging assemblies.

UltraVS64-HP

UltraVS64-HP is Teradyne’s most advanced power supply and delivers 1,280 amperes per instrument, 5,120 amperes per power supply in a ganged configuration and an overall test cell capacity of more than 15,000 amperes. Thanks to an exclusive operating range of up to 16 V, UltraVS64-HP is ready for testing emerging architectures with integrated voltage regulators (IVR), spanning from low-voltage, high-current devices to higher-voltage inputs. This greater availability of current and voltage allows customers to follow the evolution of advanced packaging roadmaps toward computing devices of ever greater size and power, all with a single instrument.

The new integrated multi-point sense system combines excellent dynamic load response to preserve device yield, keeping conditions stable while high-current activity moves between full-reticle-sized dies and multi-die packages. Advanced power profiling features provide access, with a simple command, to in-depth information on device behavior during testing, an essential element for characterizing next-generation architectures and optimizing test programs based on measured results. A new dedicated Intelligent Power interface introduces system-level power management elements into the test cell and adds fast hardware fault response, protecting against thermal runaway and the resulting costly damage to the probe card and socket.

For more information, visit teradyne.com/ultraflexplus.

The post Teradyne Expands UltraFLEXplus with New Instruments for AI and Data Center Testing appeared first on Open Electronics.

This engineer combines a fellow contributor’s design and analysis data with his own to deliver a “bit” better circuit result.

In his recent Design Idea, “DAC implementations: The spread-bit PWM strikes back”, frequent and favored contributor Christopher Paul does a terrific analysis of “spread-bit” versus “clustered-bit” PWM DACs. Something in Christopher’s results that I found particularly super impressive (and surprising) was his detailed tabulation of settling times for spread-bit DACs (see his Table 1). When combined with his design methods for precision 3rd order unity-gain ripple filters, they provide peak-to-peak ripple amplitudes of Vpp = 1/N.

What’s especially nifty is that, when normalized for length of the PWM cycle time (2b / 1mHz clock) and tabulated for some popular resolutions from b = 8 to 16, the number of PWM cycles required for the output voltage to settle to within one least significant bit (LSB) does a very interesting thing. It hovers around only 2 to 3 cycles. That was an impressive result. But of course it made me wonder if there might be a way to do perhaps even a a bit better.

Wow the engineering world with your unique design: Design Ideas Submission Guide

So I started digging. I didn’t really expect to succeed. But I found a candidate—from the Design Ideas archives of nearly two decades ago. The circuit in Figure 1 of “Fast-settling synchronous-PWM-DAC filter has almost no ripple” (full disclosure: also written by yours truly) avoids most of the problems of low-pass filtering by combining a differential integrator, A1, with a sample-and-hold amplifier, A2, in a feedback loop operating synchronously with the PWM cycle, T2 in Figure 2 of that same article.

If you make the integrator time constant equal to the PWM cycle time—that is, R1C1 =T2 —and, if the sample capacitor, C2, equals the hold capacitor, C3, then the filter can acquire and settle to a new DAC value in exactly one PWM-cycle time, i.e., a “unicycle!” Ripple suppression of the synchronous filter is, in theory, infinite. The only practical limit (there’s at least one of those, isn’t there?) is nonzero-charge injection from S2 into C3. However, the choice of a low-injected-charge switch for S2 and appropriately generous capacitances for C2 and C3 can easily result in ripple amplitudes in the order of microvolts.

Rewind to the present.

Figure 1 below shows that legacy circuit updated and supplied with an integrator time constant settling-time trim (R1). This simple mod completely removes the requirement stated in the 2008 Design Idea that the single-cycle settling critically depends on C2 and C3 being precisely equal.

Figure 1 This “unicycle” DAC ripple filter combines a differential integrator, A1a, with a sample-and-hold amplifier, A1b, in a feedback loop operating synchronously with the PWM and sample-and-hold timing signals. Note that the integrator time constant shown is centered around 65.4ms and 16bit “clustered bit” PWM resolution.

You can just twiddle R1 to precisely achieve the single-PWM-cycle (unicycle) settling. Note that this single adjustment not only effectively compensates for and cancels out the C2 and C3 tolerance, but also accommodates all integrator feedback loop passive components (i.e., R2, C1, C2, and C3). The compensation even includes U1 internal switch Rons.

However neither R1 nor the passive component tolerances have any effect on Vout = PWMdutycycle x Vref conversion accuracy, which is inherent—apart from small effects due to op amp A1 non-idealities (mainly comprising finite DC gain and input offset) and single-digit-ohms U1 internal switch mismatch. The latter are minimized by the paralleling of the U1a and U1b sections shown in Figure 1.

If  R1 is adjusted so that (R1 + R2)C1C3/C2 = Tpwm = 216 /1MHz, a precise unicycle settling will complete in exactly one 16-bit 65.536ms PWM cycle time (Figure 2). The final Vout = PWMdutycycle x Vref is inherent and is unaffected by R1 adjustment or passive part tolerances.

Figure 2 This settling DAC timing diagram sketch details the unicycle result.

It’s perhaps also worth noting that because rapid settling for this circuit doesn’t rely on “spread-bit” techniques with their dependence on software execution times, microcontrollers’ built-in PWM peripherals can be used for timing signal generation. This of course makes order-of-magnitude faster PWM frequencies and even faster settling times available. If required, that is.

Stephen Woodward‘s relationship with EDN’s DI column goes back quite a long way. Over 200 submissions have been accepted since his first contribution back in 1974.  They have included best Design Idea of the year in 1974 and 2001.

Related Content

• DAC implementations: The spread-bit PWM strikes back
• Cancel PWM DAC ripple with analog subtraction
• Implementing a DAC: The battle of the PWMs
• Cancel PWM DAC ripple and power supply noise

The post Clustered-bit PWM DAC pedals and settles in a “unicycle” appeared first on EDN.

📝 Інженерний тиждень KPISchool! kpi ср, 10/21/2026 - 14:54

Henkel Adhesive Technologies, the market leader in adhesives, sealants and surface treatments, has been actively developing and executing numerous initiatives geared towards sustainable, energy-efficient, lightweight solutions for the Automotive and Metals market in India. Anwesh Koley of ELE Times caught up with Manish Dave, Head of Industrials – India, Henkel Adhesive Technologies, to deep-dive into the company’s India initiatives and its completion of 150 years of operations.

ELE Times: Tell us about Henkel at Productronica this year. What is the company showcasing?

Manish Dave: We are very passionate about Electronica, and as you can see, we have a wide variety of offerings. Our business spans from data centres and AI—which obviously are seeing a lot of growth—to power and industrial automation, because all this data requirement now needs energy, and we supply solutions for that.

We also have aviation and avionics, which are growing significantly, alongside newer domains around life sciences and wearable items. Across all of these, we provide material solutions, whether it is circuit board protection or thermal materials to dissipate heat.

ELE Times: In terms of the current market for electronics in India, how do you perceive the Indian market vis-à-vis other Asian markets and from a global perspective? How do you see that?

Manish Dave: It depends upon the segment you talk about. For AI, we are behind; certainly, the US and China are far ahead. But India is catching up really fast. Over the last many months, I have continuously seen India coming in at number 3. It used to be maybe 5 or 6, with Japan, Germany, many European countries, and even South Asian nations ahead of us. If you look at Malaysia, Thailand—Thailand is really, really good—and Vietnam, India is certainly growing. We still have some work to do, so I would say a couple more years before we arrive on the global scene.

ELE Times: In terms of the latest innovations at Henkel that we are seeing, particularly in the AI domain, and then if you could talk about the defence sector which is also showing a lot of promise, please brief us about the initiatives at Henkel.

Manish Dave: For AI, for sure, there is data generation and heat management. An AI data centre would have servers and routers, and we are involved with all of them across the whole ecosystem. Our job is to make sure that piece of circuit board is protected—that you have underfills and conformal coatings, potting that protects it. And then for any heat on any active surface, we have our thermal interface materials that dissipate heat, keeping it at an optimal temperature. We see a tremendous amount of growth in data and AI, and I think India is probably at the cusp of getting into the lead at some point in time.

Defence is new for us, but there have been lots of announcements from the frontline objects, and Henkel is involved. Our Loctite products have been used on frontline objects onwards. From a structural strength perspective, I always say our products are used to bond primary and secondary structures on an aircraft flying at 24,000 feet, going 500 miles per hour, carrying 300 people. Our products play a very important role in that, delivering quality and innovation. We have several key innovations not just in electronics, but around structures—how to make them lighter—and composites are a big part of what we do.

ELE Times: In terms of current market dynamics and how you see India vis-à-vis other markets, there are also challenges the industry faces regarding process optimization. How does Henkel deal with that, and how does the cost factor feature in this?

Manish Dave: That is a very good question. What we have done in Bangalore is open an application centre, because we want to be closer to the customer and faster. The role of our engineers there is to welcome customers who bring in their challenges.

We had a recent case where they brought in a challenge, we worked together to find a solution, and within one week we delivered an end-to-end solution. That is really what we are trying to do: build our ecosystem to work with the epicentre here, working with both unicorns and established players.

ELE Times: The government is highly optimistic about semiconductors, not only in terms of products but also the investments coming up in recent years. What’s your take on the India Semiconductor Mission 2.0, the massive investments, and how do you see this sector going forward?

Manish Dave: I think this is the next big frontier for us. The government has done the right job of investing. You could argue we are a little late, but I think the speed at which India moves is what I am really enjoying.

I grew up in Ahmedabad, and I used to know this small town called Sanand. Now I go there and I see Tata Electronics and Tata Semiconductor, and it’s just breathtaking. There is massive potential, and public-private partnerships are playing a key role there. We are very actively involved on both sides of that, and NASSCOM is one area where we work very closely.

ELE Times: You mentioned PCBs and PCB designs. How critical is getting this technology right? Many manufacturers have been wary of introducing new technologies, preferring to continue with older ones due to the critical nature of the component. How do you see PCB design evolving, and what is your perspective?

Manish Dave: We are more focused on solutions to protect the circuit board and have seen the evolution of PCBs. I remember the early days—and I have been in the industry a long time across multiple roles—circuit boards went from being very small to massive boards for different subsystems, and now they are coming back down to smaller sizes, showing a tremendous amount of innovation.

For India, I think there is still a heavy reliance on China in terms of critical components. A lot of investment has gone into components and assembly being made in India, but not necessarily the raw materials required. If you look at a circuit board, there are so many materials required; I think bringing some of those in to achieve independence is the next big frontier. Then you can truly talk about cost, quality, and speed altogether.

ELE Times: Henkel has been part of the entire value chain in electronics. You talked about developing indigenous technology as of now and mentioned our reliance on China. What according to you can be the steps to increase self-reliance going forward?

Manish Dave: That’s an excellent question. One key factor is investment coming not just from the government, but from private players—the movement of capital is critical. I spent most of my life in the US, and I am convinced the entrepreneurial drive exists in India. However, people sometimes lack access to capital. How do they get access to that capital?

What I love about Bangalore and coming here is that we can find everything in one place: people with money, people with technology, and people with ideas and aspirations. Platforms like NASSCOM give them a chance to come together, and we work very closely with many corporations to help startups grow. We are still dependent on China, but if we keep doing what we are doing with no setbacks in our path forward. The next 10 years are going to be the golden 10 years for India.

ELE Times: Henkel is celebrating 150 years. Tell us about how this journey has been and how you expect the upcoming decades to be.

Manish Dave: It started with Fritz Henkel with a very small role in laundry—that’s where he started. Then he realized those sacks required adhesives, adhesives came into the picture, and now we are at a €22 billion public organization.

Dr. Simone Bagel-Trah, Chairwoman of Henkel’s Supervisory Board and Carsten Knobel, CEO of Henkel

Henkel is celebrating 150 years this month across the world, and in India, the celebration will be in two weeks. We are very, very excited and really proud of an organization that’s 150 years rich. We don’t just look ahead another 150 years; our plan is always long term, always sustainable. Our mantra is “Pioneers at heart for the good of generations.” We really want to create enduring value for generations to come for the next hundreds of years.

The post Interview | Manish Dave, Head of Industrials – India, Henkel Adhesive Technologies appeared first on ELE Times.

An ATmega2560 with 8 KB of RAM can support a multitasking desktop environment, complete with games, file management and video playback. That is what Vladimir demonstrated by building a DIY laptop around an Arduino-compatible board with an ATmega2560, the Mega 2560 Pro Mini. The device measures 12x11x3.4 cm and packs a QWERTY keyboard, a 128×64 monochrome display, audio, microSD, an RTC and an 18650 battery into a 3D-printed enclosure. The firmware runs on FreeRTOS and offers real multitasking, with task switching via Alt-Tab. So a video that has been started keeps playing its audio while you play Sokoban.

The architecture of independent tasks is the core of the project. Applications receive events and draw through the UI engine, while the shell handles registration, stacks, switching and events. As a result, adding a new application does not require touching the others. A new task is a class with setup and loop plus a couple of methods for its menu entry and icon.

The UI engine and the applications on FreeRTOS

The interface engine handles forms, buttons, checkboxes, lists, input fields and dialogs. It takes care of key presses, tabbing, redrawing and the events sent to the owning task. On top of it run the ready-made applications:

• file manager
• video player
• music player
• clock
• calculator
• Sokoban
• Snake
• Game of Life
• text editor

The ST7920 display is driven in parallel mode with a custom-written driver and a 1 KB video buffer in SRAM. The graphics functions range from a single pixel to text and XBM images. The AVR microcontroller runs at 16 MHz and everything runs on 8 KB of RAM, half of which is already taken up by global variables. That is why every byte of the buffer counts.

8×8 keyboard, debouncing and a 4-to-16 decoder

The keyboard has 64 keys in total, arranged in an 8×8 matrix that requires two 8-bit ports of the microcontroller. The keys were laid out in an 11×6 rectangle. Scanning happens column by column at hundreds of hertz, with software debouncing. In one revision a diode was added for each key and column selection moved to a 4-to-16 decoder. This way four pins are enough to select a column and the keyboard can expand to 16 columns.

The matrix rows are currently 6, but by reading a whole port of the microcontroller they can be brought to 8. The key labels were printed with a 0.25 mm nozzle. For the audio and memory side, the project relies on components that have a direct counterpart in the catalogue: an audio decoding shield for compressed formats, a microSD card reader with an SPI interface for the files, and a board that combines an ATmega2560 with Wi-Fi connectivity for anyone who would rather start from a different base.

24 fps video and XBM format plus MP3 in a single file

The video player uses a custom format with an XBM stream and MP3 in a single file. This way the player comfortably handles 24 fps video with audio, without keeping more in RAM than needed. The rest of the board is taken up by the RTC and the 18650 battery, which make the device self-contained. The enclosure was machined with a CNC3018 and 3D printed, while the schematics were drawn in EasyEDA.

Anyone who wants to rebuild the project will find the story of the work and the information to recreate it on the project page on Hackaday.io signed by Vladimir. Alternatively, an enclosure for an Arduino Mega can serve as a dimensional reference for the electronics, even though this laptop’s case is printed to measure.

Source: https://hackaday.io/project/206744-avr-laptop

Related products

• VS1053 MP3 Shield for Arduino
• MicroSD Card Reader module with SPI interface
• Board with ATMEGA2560 and ESP8266 Wi-Fi SoC Module

The post A DIY laptop built on the ATmega2560: real multitasking on 8 KB of RAM appeared first on Open Electronics.

With its new SOLO placement head, ASMPT SMT Solutions, the global market and technology leader in integrated hardware and software solutions for the electronics manufacturing industry, is expanding its portfolio of solutions for the production of complex circuit boards for AI and high-performance computing (HPC) applications. Developed especially for the reliable placement of particularly large and heavy processor BGAs, the new head can initially be used on the SIPLACE SX. It handles components measuring up to 240 × 240 millimetres (9.45 × 9.45 inches) and weighing over 2 kilograms (4.4 pounds), soon to be increased to up to 5 kilograms (11 pounds). 

The growing demand for AI applications and their associated computing power is driving the development of highly integrated multi-die modules. More transistors, higher memory bandwidths and thousands of power supply and signal connectors make processor BGAs increasingly complex, larger, and heavier. Whereas only one year ago large processor BGAs measured roughly 150 × 150 millimetres (9.45 × 9.45 inches) and weighed 500 grams (1.1 pounds), the next generation is already reaching 240 × 240 millimetres (8.45 × 9.45 inches) with weights of 2 kilograms (4.4 pounds) – about two times the area and four times the weight. To meet the dynamic growth of the AI market, ASMPT has developed within six months its completely new SOLO placement head as the perfect solution for handling these ever larger and more expensive processors.

Specialist for large and heavy processor BGAs

The new SOLO head is specially designed for picking and placing processor BGAs of this size and weight class. It is based on a new single-segment architecture with a strengthened and stiffened axis. The connection between the placement head and the gantry as well as the interface between nozzle and segment were also designed to withstand the greater mechanical loads. The maximum placement force is 200 newtons. Construction-wise, the head is already designed for significantly heavier components weighing up to 5 kilograms (11 pounds).

Since the highly complex processors can cost more than 20,000 U.S. dollars, they must be handled with an appropriate level of safety and reliability. The nozzles are matched to the respective housing surfaces and take into account any areas that must not be touched during pickup. And since the mass inertia of the large BGAs can be taken into consideration in the movement profiles, acceleration and rotational movements can be customized for the respective component.

The SOLO placement head handles the final step

The processor is merely one of many components on an AI server board. Before it is placed, many ICs, condensers, connectors and super-small passive components must be processed. To accomplish this, various placement heads can be combined on SIPLACE placement machines in an SMT line: The CP20 handles the speedy placement of the smallest components, the CPP covers a broad component spectrum, and the TWIN VHF handles large, heavy and unusually shaped components. The expensive processor BGAs are installed at the very end of the placement process. The new SOLO head handles this particularly critical step and ensures that these large and heavy components are picked up and placed with reliability and precision.

Process reliability along the entire line

The placement of large processor BGAs is only one part of the manufacturing process. Material feeding, circuit board handling and quality control must also be designed to meet the special requirements of AI server applications. The SIPLACE SX provides the necessary functions. Heavy-duty conveyors ensure the safe transport of large and heavy circuit boards while the SIPLACE Smart Pin Support provides the necessary support and prevents PCBs from bending and vibrating during the placement process. And before placing the processor, the machine can inspect critical board segments, especially those in the processor’s target area, for foreign matter and ensure the presence and correct position of spacers. After picking up the processor, it checks BGA connectors optically and can optionally measure the coplanarity of the solder balls via 3D laser triangulation. With the SOLO placement head, the SIPLACE SX is now keeping pace with the rapid developments in the size and weight of processor BGAs.

The post ASMPT Presents New SOLO Placement Head for AI Server Applications appeared first on ELE Times.

Стратегічне партнерство з університетами Німеччини та Франції KPI4U-2 ср, 10/21/2026 - 12:36

CyteSi, a Menlo Park–based innovator in digital microfluidics, today announced the successful validation of a next generation sequencing (NGS) library preparation workflow on CyteSi’s proprietary Turing Biosystem D1 platform using NGS library preparation kits from QIAGEN GmbH. The validation was conducted by Intelligent Biosystems in Hangzhou, China, applying its industrial-scale biological data-generation capabilities and integrated workflows to support automated NGS library-preparation performance on the D1 platform.

Compared with conventional manual library preparation, the Turing Biosystem D1 enables fully automated NGS library preparation for up to six samples per run with less than five minutes of hands-on time. By miniaturizing and digitizing key liquid-handling steps, the D1 system can reduce reagent consumption and lower reagent costs by more than 70%, dramatically reduce labour requirements, and help minimize batch-to-batch variance.

These advantages are especially important for clinical diagnostics markets in North America, Europe, and Japan, where cost control, workflow standardization, reproducibility, and operational efficiency are critical to broader adoption of NGS based testing. CyteSi and QIAGEN are positioned to support future NGS workflow adoption through validated kit compatibility and automated library preparation, while Intelligent Biosystems’ validation work demonstrates the D1 platform’s readiness for broader clinical-diagnostics applications.

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DigiKey, the global distribution leader of electronic components and automation products, is the exclusive distributor of the newly available Coralboard, a developer-ready edge AI board powered by Coral NPU technology from Google Research and Synaptics Astra embedded processors. Manufactured by Grinn, the development board offers a practical starting point for rapid prototyping, product evaluation, and production-oriented edge AI development.

“DigiKey is excited to partner with Synaptics and Google Research to bring the Synaptics Coralboard to the global engineering community,” said Mike Slater, vice president of global business development for DigiKey. “By carrying the full stack, from development board to module to silicon, DigiKey can support edge AI developers at every stage from experimentation to production. Google Research, Synaptics and Grinn have delivered a game-changing dev board to the electronics industry, and we are excited to support them in getting the board into the hands of engineers, designers, makers and developers worldwide.”

What is Coralboard?

The Coralboard is a development platform for edge AI powered by Coral NPU from Google Research and Synaptics Astra embedded processors. Built for rapid prototyping, the board features an integrated Coral NPU for fast, efficient on device AI acceleration, giving you the power to create, test, and deploy smart experiences with ease. The kit is fully equipped with everything needed to bring development projects to life and offers seamless plug-and-play support for cameras, displays and audio. It also effortlessly keeps devices connected with versatile options like Ethernet-over-USB and optional support for Wi-Fi and Bluetooth modules.

The Coralboard edge AI development board is available now from DigiKey worldwide. Designed for ultra-low-power, always-on applications using ambient sensing, the dev board enables fast, efficient on-device inference and supports all day AI experiences in battery-constrained form factors.

Typical Coralboard applications include smart cameras, industrial monitoring, predictive maintenance, voice-enabled devices and battery-powered edge AI systems.

The Coralboard is intended for embedded developers, AI and machine learning engineers, system architects, product teams, and device manufacturers building the next generation of intelligent edge products. Teams can begin with Coralboard for evaluation and rapid prototyping, move to product prototyping and integration, and scale to full production designs. This flexible path helps developers explore real-world AI workloads, validate product concepts, and move from experimentation to production using a common Edge AI technology foundation.

“We are excited that the Synaptics Coralboard is now available directly for developers through DigiKey,” said Billy Rutledge, director for Google Research. “With Coralboard, it is easier than ever to bring advanced AI to the edge, and this platform reflects our shared commitment to secure and accessible Edge AI for developers around the globe.”

“With Google’s Coral NPU technology, we are enabling a cutting-edge class of systems where power efficiency, performance and on-device intelligence characterize developer experience,” said Vikram Gupta, SVP & GM, edge compute & connectivity solutions division for Synaptics. “The Coralboard provides users and OEMs a faster path to building and deploying at-scale AI products for the edge.”

The post Synaptics Coralboard Edge AI Development Board, Powered by Coral NPU technology From Google Research, Now Available Exclusively From DigiKey appeared first on ELE Times.

This year again, Futura Elettronica, Elettronica In and Open Electronics are among the sponsors of Maker Faire Rome, the European fair for makers, inventors and technology enthusiasts. The 2026 edition is the 14th and runs from 23 to 25 October at the Gazometro Ostiense in Rome.

You can find us at stand M15 on all three days of the fair.

At stand M15 in Maker Faire Rome 2026

We bring as much electronics as we can carry: boards, kits, components, instruments, the magazine and books. At the stand you can also talk to us about your projects, ask for technical advice or simply see the products up close before choosing them.

Want to see a specific product?

If you already know what you are looking for, tell us before the fair. We cannot bring the whole catalog, but we will do our best to have your product at the stand, so you can see it in person.

Useful information

• When: Friday 23 to Sunday 25 October 2026
• Where: Gazometro Ostiense, Rome
• Our stand: M15
• Tickets and programme: on the official website, makerfairerome.eu

See you at the Gazometro!

The post Maker Faire Rome 2026: We Are Sponsors Again, See You at Stand M15 appeared first on Open Electronics.

ROHM has developed the SDR01 series) of anti-surge chip resistors, which offers a class-leading* rated power of 0.33 W in the 0402 (1005 metric) package. Designed for electronic equipment with ever-increasing mounting density, this series is particularly well suited to applications in the automotive, industrial, consumer electronics and AI server sectors.

Key features and benefits

The new products save board space and reduce component count, thanks to the ability to replace larger resistors and to group resistors together, while still maintaining the reliability required of anti-surge chip resistors.

Market trends and application requirements

As electronic equipment becomes increasingly sophisticated and demands more power, the automotive, industrial and consumer goods markets are seeing growing demand for electronic components that combine compact size with high power handling capability. These trends are also driving demand for smaller, highly reliable chip resistors, including anti-surge products. In power supply circuits and near interfaces, resistance to overvoltage and electrostatic discharge (ESD) is required, along with the ability to handle high power.

Optimised design and performance

To meet these requirements, ROHM has optimised the resistive element and electrode design of the SDR01 series, thereby ensuring a high rated power in the 0402 package while also guaranteeing the reliability expected of high-performance anti-surge chip resistors. The new products deliver 0.33 W up to a terminal rated temperature of Tk = 125 °C. This makes them easier to use in environments with challenging thermal conditions, such as high-density mounting and the areas surrounding heat-generating components, helping to reduce thermal design complexity. In addition, these products achieve a TCR of ±100 ppm/°C for 10 Ω ≤ R ≤ 2.2 MΩ. By eliminating resistance value fluctuations caused by temperature changes, these products ensure stable circuit operation and make it easier to build more compact and reliable power supply and peripheral interface circuits.

Availability and sales channels

Mass production of the new products and online sales have also begun: the products are available for purchase through ROHM’s online store and via online distributors such as DigiKey and Farnell.

Future outlook

ROHM will continue to expand its line-up of high-reliability chip resistors, contributing to greater miniaturisation and power handling capability, as well as higher reliability of electronic equipment.

Application examples

Power supply and control circuits in the automotive, industrial and consumer electronics sectors that require compact size, as well as high power handling capability and reliability.

*ROHM research dated 10 September 2026

The post ROHM SDR01: 0.33 W anti-surge resistors in an 0402 package appeared first on Open Electronics.

Murata Manufacturing Co., Ltd. announces the development of the world’s smallest 008004-inch size (0.25mm × 0.125mm) NTC thermistor, the NCU01 series. Compared with Murata’s previous smallest 01005-inch size (0.4mm × 0.2mm) product, the new series reduces mounting area by approximately 60% while achieving equivalent temperature sensing performance, with resistance tolerance of ±1% and B-constant tolerance of ±1%. Its ultra-compact size enables temperature sensing to be positioned in increasingly restricted spaces and closer to heat-generating components, supporting more accurate and responsive thermal monitoring in smartphones, wearable devices, and other densely integrated electronic devices.

Murata plans to begin sample shipments in October 2026 and mass production during 2027. The line-up will be expanded progressively, beginning with 100kΩ and 10kΩ resistance values.

Bringing Temperature Sensing Closer to the Heat Source

As electronic devices continue to become smaller and more sophisticated, component density on circuit boards and inside modules continues to increase. As a result, mounting space for electronic components is limited, making it difficult to place NTC thermistors close to heat-generating components. If a thermistor must be placed farther from the heat source, the measured temperature can differ from the actual component temperature, while rapid temperature changes may also take longer to detect.

This creates a demand for smaller NTC thermistors that can be positioned closer to critical components without consuming valuable board space. However, continued miniaturization makes high-precision processing and manufacturing more difficult, making it more challenging to maintain consistent sensing characteristics. For NTC thermistors, tight resistance and B-constant tolerances are critical to enable stable temperature sensing.

High-Precision Performance at 008004-inch Size

Murata addressed these challenges through its proprietary ceramic materials technology, high-precision processing, and optimization of the component structure and manufacturing process to develop the world’s smallest 008004-inch size NTC thermistor. Despite its significantly smaller footprint, the new NCU01 series maintains the ±1% resistance and B constant tolerances achieved by Murata’s previous 01005-inch size product.

By reducing the mounting area by approximately 60%, the NCU01 can be placed in locations that are difficult to accommodate with larger thermistors, including closer to heat-generating components. This can help reduce the temperature difference and detection delay associated with more distant measurement points while contributing to the stable operation of electronic devices with high-density component layouts.

Primary applications include temperature monitoring on circuit boards in smartphones and wearable devices, as well as in integrated circuit (IC) packages and system-in-package (SiP) modules.

Murata will continue to expand its NTC thermistor line-up and contribute to further miniaturization and improved reliability of electronic devices. For product inquiries, please contact us here.

The post Murata Develops World’s Smallest 008004-inch Size (0.25mm × 0.125mm) NTC Thermistor for Space-Constrained Temperature Sensing appeared first on ELE Times.