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N.A.N. Enaex, a 50:50 joint venture between N.A.N. GreenMet and Chile-based Enaex S.A., plans to enter the Indian market in 2027. The company will initially invest ₹750 crore to set up an integrated explosives manufacturing facility in India. It expects the Indian market to contribute around 10% of its global sales in the medium term, generating approximately $300 million in revenue.

The joint venture will provide emulsion explosives, electronic detonators, mine-to-mill optimisation services and digital tools powered by AI. These solutions will be used in mining, quarrying and infrastructure projects. Beyond supplying explosives, the company aims to improve blasting accuracy, workplace safety and operational efficiency while reducing the impact of blasting on nearby areas.

India’s explosives market is estimated to reach $1.7 billion by 2030 and $2.7 billion by 2035. Demand is being driven by expanding mineral production and large-scale infrastructure development. India is targeting 300 million tonnes of steelmaking capacity by 2030, while selected mining segments are projected to grow by 12–15% annually. The country also has a pipeline of more than 1,300 tunnels spanning 3,600 km across hydropower, railways, roads and metros, supported by the government’s ₹12.2 lakh crore capital expenditure allocation for FY2026-27 and 500 GW non-fossil electricity capacity target for 2030.

Enaex is a provider of blasting solutions with a 100-year history and a well-established international presence across the world’s most important mining markets. The company has direct operations in North and South America, Europe, Africa, and Oceania, with leading positions in countries such as Chile, Peru, Brazil and South Africa.

N.A.N. Enaex’s technology portfolio includes proprietary DaveyTronic electronic initiation systems, digital blast design and monitoring tools, and mine-to-mill optimisation services. These technologies are designed to improve fragmentation and blast control, helping customers increase productivity, reduce downstream processing costs and manage vibration and other environmental impacts.

Early discussions with leading Indian mining companies have been encouraging, revealing a clear appetite for technology-led blasting solutions over conventional explosives supply. Customers are seeking greater productivity, lower costs, improved safety and reduced environmental impact, especially near residential communities.

N.A.N. Enaex is bringing its first manufacturing unit strategically located close to customers and industrial infrastructure in Eastern India with phase 1 capacity of 150,000 tonnes of emulsion explosives and one million electronic detonators.

Annanya Agarwal, Co-founder and Director, N.A.N. GreenMet, said: “India is investing heavily in civil infrastructure, from hydropower and tunnelling to highways and railways, alongside the expansion of its mining sector. These projects need better technology, higher safety standards and more efficient operations. Our early conversations with customers have made it clear that the market is ready for this change. With Enaex, we have a partner with a strong global track record in product quality, technology and safety. Our investment is aimed at building a substantial Indian manufacturing and technology business, close to our customers and provide end-to-end reliable products and services to large infrastructure and mining operations.”

Juan Andrés Errázuriz Domínguez, CEO, Enaex, said: “India is undertaking infrastructure projects of a scale and complexity that demand a different approach to blasting. In our experience across some of the world’s largest mining markets, the real gains come from getting the blast right the first time, with greater precision, better fragmentation and tighter control. That is where technology makes a measurable difference to productivity, costs and safety. We have spent more than 100 years developing these capabilities, and through N.A.N. Enaex, we intend to bring that experience to India’s most challenging mining and infrastructure projects.”

The post N.A.N. Enaex Invests ₹750 Crore in India’s Explosives Market, Targets $300 Million Revenue appeared first on ELE Times.

The Rust epdsi driver runs e-paper panels on different microcontrollers without changing a single line of the panel code. Mariusz Jurgielewicz demonstrated it on two boards that are very far apart: an Adafruit RP2040 Feather ThinkInk with a Cortex-M0+ core and a Seeed Studio XIAO ESP32-C3 with a RISC-V architecture. On the XIAO, paired with Seeed’s ePaper Driver Board, the framework handles seven panels and five different controller ICs. Only the HAL glue changes, that is, the code that talks to the silicon of the board.

epdsi is a no_std framework based on embedded-hal 1.0. Its core idea is to separate four things that usually end up piled into the same file: the physical panel, the controller IC, the SPI transport and the orchestration. That way, adding a panel to an already supported controller requires just one new file, the one describing the panel. Mariusz Jurgielewicz’s project page on Hackster.io collects the complete work, with the code and the tests on the various panels.

EpdPanel, EpdController and SpiBusWrapper: how the framework is built

The epdsi architecture rests on four main types. EpdPanel is a zero-sized type that describes the physical panel: width, height, colour mode and voltage or LUT peculiarities. EpdController holds the command logic of the driver IC, so the init sequence, addressing, frame writing, refresh and sleep. SpiBusWrapper handles the physical transport, that is an embedded-hal SpiDevice plus the DC, RST and BUSY control pins. EpdDriver orchestrates everything through EpdBuilder and exposes the public API, while colours go through the ColorMode and ColorChannel enums.

• EpdPanel: describes the physical panel, dimensions, colour mode, voltage and LUT
• EpdController: init sequence, addressing, frame writing, refresh and sleep of the driver IC
• SpiBusWrapper: SPI transport plus the DC, RST and BUSY pins
• EpdDriver: orchestrates the components through EpdBuilder and exposes the public API
• ColorMode and ColorChannel: handle the colours passed to the API

The framework offers blocking builds on embedded-hal and asynchronous builds on embedded-hal-async, selected by feature flags. For those with little RAM there is render_paged(), which draws the panel in horizontal bands with buffers allocated on the stack. This way a 48,000-byte frame stays manageable even on limited hardware. The compilation target for the XIAO ESP32-C3 is riscv32imc-unknown-none-elf, with esp-hal 1.0.0 and embedded-graphics for the graphics.

Seven panels, five controllers and the timings measured over SPI

Several panels run on the XIAO ESP32-C3 with the ePaper Driver Board. The GDEQ0426T82 is a 4.26-inch mono panel, 800×480, with an SSD1677 controller. The GDEM0213B74 is a 2.13-inch mono panel, 122×250, with an SSD1680. The ZJY122250-0213AJH-E5 is a 2.13-inch quad-colour panel, 122×250, with a JD79661. The GDEM0154Z90 is a 1.54-inch tri-colour panel, 200×200, with an SSD1681. Then there are the SE0352N14 and the GDEY037T03, both with a UC8253 controller, the first a 3.52-inch tri-colour panel and the second a 3.7-inch mono panel. In total epdsi covers 8 controller ICs driving 13 panels.

The numbers help you understand what to expect. At 4 MHz of SPI, the 4.26-inch mono panel does a full refresh in about 3.75 seconds and a partial refresh in about 1.0 second. Moving a 4,000-byte frame over SPI takes about 8 ms. Tri-colour and quad-colour panels, on the other hand, need 14 to 17 seconds per update and have no meaningful partial mode. So the choice of panel depends a lot on how often you want to update the screen. The FPC socket of the Feather ThinkInk has 24 pins, while the 2.13-inch JD79661 panel is quad-colour.

Anyone who wants to rebuild the project starts from a XIAO ESP32-C3 with Seeed’s ePaper Driver Board, or from an RP2040 Feather ThinkInk. Either way the panel code does not change: only the HAL glue changes.

It is worth knowing that the debug build exceeds 5 MB, while the release build drops to about 750 KB. Anyone compiling for microcontrollers with limited flash must therefore work in release. The framework uses Rust with no_std, esp-hal 1.0.0, embedded-graphics, embedded-hal 1.0 and embedded-hal-async. These are all mature libraries, so the project can be rebuilt without exotic dependencies. The demonstration on two different architectures, Cortex-M0+ and RISC-V, is proof that the abstraction layer holds up.

Source: https://www.hackster.io/melastmohican/driving-e-paper-displays-with-rust-on-the-xiao-esp32-c3-7c6ecb

The post Rust epdsi driver takes e-paper from Cortex-M0+ to RISC-V appeared first on Open Electronics.

Cadmium telluride (CdTe) thin-film photovoltaic (PV) module maker First Solar Inc of Tempe, AZ, USA has signed a non-exclusive licensing agreement granting it access to the issued and pending US patents covering perovskite solar technology of CubicPV Inc of Bedford, MA, USA...

Wolfspeed Inc of Durham, NC, USA — which makes silicon carbide (SiC) materials and power semiconductor devices — has announced the commercial introduction of its proprietary transparent silicon carbide (TSiC) technology, expanding the potential of SiC to enable next-generation augmented reality (AR), quantum computing and advanced optical applications...

AI is getting better at navigating semiconductor design. It can search design spaces, optimize constraints, generate layouts, explore trade-offs, and increasingly interact with established EDA flows. But there is a major difference between designing a chip and manufacturing one.

Design lives primarily in a structured environment of models, rules, constraints, libraries, and solver outputs. Manufacturing does not; it creates a physical system. That physical system can vary from the intended design because of process conditions, materials, equipment behavior, geometry, assembly sequence, temperature, loading, and time.

Design intent isn’t the same as built reality

A design tool can work with intended geometry. Manufacturing must deal with as-built geometry. That distinction becomes especially important in advanced packaging. A package may be designed with nominal values for:

• Bump pitch
• Stand-off
• Bond-line thickness
• Die placement
• Co-planarity
• Alignment
• Substrate flatness
• Underfill thickness
• Thermal interfaces

But the manufactured package does not exist at one nominal point. It exists as a distribution. Placement shifts. Reflow changes geometry. Underfill flows and cures. Materials shrink. Warpage develops. Die tilt changes. Bond-line thickness varies across the interface. Thermal gradients change local dimensions during operation.

The physical system that exists after manufacturing is therefore not identical to the one that existed in the design environment.

Manufacturing AI must understand physical state

This is where AI faces a different problem. In design, the agent can often ask: Does this solution satisfy the rule or constraint? In manufacturing, the question becomes: What physical state did the process actually create? That requires a different type of evidence.

Manufacturing AI may need to interpret:

• Process history
• Equipment conditions
• Material lots
• Metrology
• Dimensional variation
• Defect maps
• Thermal data
• Electrical test
• Optical test
• Reliability results
• Yield signatures

The value is not simply in collecting more data. The challenge is determining which data describes the actual state of the product.

Warpage is a good example

Consider package warpage. A manufacturing database may contain a single maximum warpage value, but the package may contain several different spatial effects at the same time. Global package bow can produce regional die tilt. Regional die tilt can change local bump stand-off.

The same deformation can shift optical alignment. A local interface may then experience higher stress or reduced thermal contact. The product consequence may appear later as:

• Delamination
• Fatigue
• Optical coupling loss
• Thermal degradation
• Electrical margin loss

So, the relevant chain may look like below:

Process condition → Package deformation → Regional geometry change → Local interface change → Product response

An AI system that sees only the final failure signal may identify correlation. It may not understand the mechanism.

Underfill makes the problem even more difficult

Underfill is another good example. It’s easy to think of underfill as a material-selection problem. However, once integrated into the package, it becomes part of the mechanical structure and its effect depends on:

• Modulus
• CTE
• Cure shrinkage
• Viscosity
• Dispense pattern
• Bump pitch
• Die size
• Local gap
• Adhesion
• Reflow history
• Thermal history

A local underfill condition can change residual stress. That stress can redistribute regionally. The resulting deformation can influence package warpage, and package warpage can feed back into local interface stress. Therefore, manufacturing AI cannot reason from a material datasheet alone; it must reason from the material as it exists inside the manufactured structure.

Metrology becomes part of the intelligence loop

This is why metrology matters so much. Manufacturing AI needs a way to determine whether the physical state predicted by the process actually exists. Warpage measurement, acoustic inspection, X-ray, CT, optical alignment measurement, thermal mapping, electrical test, and other methods provide different views of that state.

The important point is that these measurements answer different questions. A package-level deformation map and a local interface-defect map should not be reduced automatically to one summary number. The spatial relationship between them may contain the real engineering information.

For example:

• Where is the highest curvature?
• Where is the delamination?
• Does the same region change after thermal cycling?
• Does die tilt correspond to optical-alignment movement?

That is the kind of evidence an AI system would need before making a useful manufacturing recommendation.

Correlation isn’t enough

This may be the biggest difference between manufacturing analytics and manufacturing intelligence. If warpage and delamination increase together, that does not prove that one caused the other. The real driver may be:

• Reflow profile
• Cure condition
• Material-lot variation
• CTE mismatch
• Local thickness
• Placement offset
• Thermal gradient
• Tool drift
• Mechanical constraint

This is where design of experiments (DOE) and controlled perturbation remain essential. The useful engineering sequence is:

Change a process variable → Measure the physical state → Observe the response → Test whether the relationship repeats

That begins to separate correlation from causality. For AI, this matters because a system that learns the wrong causal relationship can recommend the wrong process change.

Drift complicates causal reasoning

Manufacturing also changes with time. Tool state can drift. Material lots change. Ambient conditions change. Process chambers age. Maintenance events alter behavior. Even a valid counterfactual comparison can become misleading if the baseline itself has moved.

That means manufacturing with AI may need continuously updated reference conditions rather than a permanently fixed baseline. The question is not only: What changed? It’s also: What changed relative to the current process state? This is much closer to how experienced manufacturing engineers already think.

In other words, manufacturing with AI needs engineering context. The deeper challenge is that manufacturing data does not explain itself. A temperature excursion, alignment shift, acoustic image, yield drop, or warpage result only becomes useful when connected to the physical context around it. AI therefore needs more than pattern recognition.

It needs engineering context connecting:

Process → Geometry → Material state → Measured behavior → Product response

That is a much harder problem than simply adding another model to the factory.

The hard part Is trust

The final question is not whether AI can generate a manufacturing recommendation. It can. The harder question is whether engineers can trust that recommendation. That trust depends on whether the system can show:

• What physical state changed
• Which evidence supports the conclusion
• Whether the relationship is causal or merely correlated
• How stable the baseline is
• Whether the result repeats
• What uncertainty remains

That is where manufacturing AI becomes different from generic automation. The objective is not simply faster decisions; it’s better-grounded decisions.

From design AI to manufacturing AI

AI is already proving that it can participate meaningfully in semiconductor design. Manufacturing is the next challenge. But the rules change once AI leaves the design environment. The system must deal with:

• As-built geometry instead of nominal geometry
• Measured state instead of modeled state
• Process variation instead of deterministic rules
• Causal evidence instead of correlation alone
• Physical drift instead of static assumptions

That is why manufacturing may become the harder test. The next generation of semiconductor AI will not be judged only by whether it can design something that reaches tape-out. It will also be judged by whether it can understand what manufacturing actually built—and whether engineers can trust the decisions that follow.

Dr. Moh Kolbehdari is senior director of IC/packaging at Socionext US.

Related Content

• A real-world approach for AI-driven semiconductor manufacturing
• How AI Redefines Semiconductor Manufacturing, From Materials Up
• How AI is reshaping IC signoff: Trust, speed, and intelligent workflows
• The AI Packaging Challenge: 5 Reasons Panels Are Gaining Momentum
• SEMICON West 2026 Displays AI-Era Chipmaking, Workforce Development

The post AI can design the chip, manufacturing it is harder appeared first on EDN.

For three decades, white LEDs have depended on rare-earth materials such as yttrium aluminium garnet (YAG) layered onto a blue LED chip (Figure 1). Opto-semiconductor device maker Seoul Viosys Co Ltd (SVC) says that it has now broken that dependence by developing and mass producing a chip that emits white light without rare earths. The chip can be as small as 10µm...

Студенти ФЕА презентували результати міжнародного міждисциплінарного проєкту у сфері енергетики Інформація КП чт, 10/29/2026 - 19:10

An 8-key piano on a breadboard with an Arduino Uno R3, eight 6×6 mm tactile buttons and a passive piezo buzzer. Each key you press plays a note of the C major scale, from C4 at 262 Hz up to C5 at 523 Hz. That is enough to play tunes like Twinkle Twinkle Little Star. No shield, no external library and no soldering are needed: just a breadboard, jumpers and a USB cable.

Assembly is the quickest part. The tactile buttons go into the breadboard straddling the centre channel, one next to the other. Each button has one side connected to an Arduino digital pin and the other side to GND. The passive buzzer has its positive leg on pin D10 and its negative leg on GND. A jumper connects the breadboard’s GND rail to the board’s ground.

The keys occupy pins D2 to D9, eight consecutive digital pins. The Arduino Uno has 14 digital pins (D0-D13) and 6 analog pins usable as digital inputs, so there is plenty of room to add keys in a later version. For the keys, the catalogue has a 6×6 mm PCB mini pushbutton, the same format used in the project.

INPUT_PULLUP and the tone() function in the firmware

The code uses no library: it relies on the tone() function built into the Arduino IDE. Each button is connected between a pin and GND, so the firmware enables the internal pull-up resistor with INPUT_PULLUP. As a result the pin reads HIGH when the key is at rest and LOW when it is pressed. The code scans the eight pins, stores the first key pressed and calls tone() with the associated frequency.

The comparison if (pressedKey != lastKey) makes tone() fire only once per press, instead of repeating the call on every pass of the loop. When no key is pressed, the code calls noTone() and the sound stops. The serial monitor opens at 9600 baud and is used to check which keys are being read during testing.

• Key 1: C4 at 262 Hz
• Key 2: D4 at 294 Hz
• Key 3: E4 at 330 Hz
• Key 4: F4 at 349 Hz
• Key 5: G4 at 392 Hz
• Key 6: A4 at 440 Hz
• Key 7: B4 at 494 Hz
• Key 8: C5 at 523 Hz

The piano is monophonic, and that is a limitation of the tone() function: it generates only one frequency at a time. So if you press two keys together, the one with the lower number wins, that is, the first one the loop encounters. Anyone who wants real chords has to change approach, for example generating the waveforms by hand with a timer.

Passive buzzer, current draw and an alternative speaker

The passive piezo buzzer works from 3.3V to 5V and draws less than 30 mA, so you can drive it straight from an Arduino pin without a transistor. Its best output is around 2-4 kHz, while the notes of this piano run from 262 Hz to 523 Hz. The sound comes out, but don’t expect concert volume: to raise the sound pressure, a speaker is a better bet.

Instead of the buzzer you can use an 8 ohm speaker with a 100 ohm resistor in series. The resistor limits the current and protects the pin. On top of that, the sound is fuller on the low notes of the scale. The rest of the circuit does not change: positive on D10, negative on GND.

Rebuilding the project takes only a few parts: an Arduino Uno R3, eight 6×6 mm tactile buttons, a passive piezo buzzer, a breadboard, jumpers and a USB cable. The cost is low and so is the difficulty. In fact it is an ideal first project for learning about digital inputs, INPUT_PULLUP and the tone() function, and you can finish it in an evening.

If you want to see the build in action, on the maker’s site you will find the video with the piano played key by key. There you can see how the buzzer behaves on the different notes before soldering or buying anything.

Source: https://www.circuitschools.com/arduino-piano-project-with-8-keys-build-a-simple-piano/

Related products

• PCB Mini Pushbutton – 6x6x7 mm

The post Build an 8-Key Piano on a Breadboard with Arduino appeared first on Open Electronics.

AI processing, inference specifically, remains mostly a cloud-centric function, but not for long. Whether it shifts to client devices in tandem or completely, who will win?

Way back in December 2022, in the introduction to a teardown of an autonomous object-tracking accessory for a smartphone’s integrated camera, I more broadly positioned the trade-off between cloud- and edge-based AI processing, with the latter exemplified by the widget.

One common way to reduce the device BOM is to offload as much of the total required processing, memory and other required resources to other connected devices. A “cloud” server is one common approach, but it has notable downsides that also beg for consideration from the device supplier and purchaser alike, such as:

• Sending raw data up to the “cloud” for processing, with the server subsequently sending results back to the device, can involve substantial roundtrip latency. There’s a reason why self-driving vehicles do all their processing locally, for example!
• Sending data up to the “cloud” can also engender privacy concerns, depending on exactly what that data is (consider a “baby cam”, for example) and how well (or not) the data is encrypted and otherwise protected from unintended access by others.
• Taking latency to the extreme, if the “cloud” connection goes down, the device can turn into a paperweight, and
• You’re trading a one-time fixed BOM cost for ongoing variable “cloud” costs, encompassing both server usage fees (think AWS, for example) and connectivity bandwidth expenses. Both of those costs also scale with both the number of customers and the per-customer amount of use (both of each device and cumulatively for all devices owned by each customer).

Those points all remain valid nearly four years later, IMHO at least, although an added cloud-based set of downsides now also begs for inclusion in the list. Back then, the AI data center (also called a hyperscaler) build-out phenomenon was still in its comparative infancy, with much of the compute capability then coming online intended for cryptocurrency mining (which ironically has subsequently been redirected to deep learning processing). Nowadays, conversely, the data center phenomenon is in fuller stride, with understandable backlash from the broad populace.

• Speculative investment deals, often “circular” in nature (a hardware supplier invests in a data center developer, for example, with the latter promising to use the former’s chips and software in exchange), result in frequent stock market volatility and broader growing “bubble market” concern.
• Governmental jurisdictions provide lucrative tax breaks and other incentives to data center developers, even though any tangible increase in employment for the local populace will be time-restricted to only the subsequent duration of construction.
• Data center energy demands are substantially incremental, necessitating in-parallel built-outs of additional power plant facilities whose costs are assumed by all.
• The incremental energy predominantly comes from hydrocarbon-based power sources such as coal and natural gas, with substantive pollution and noise impacts.
• Water demands for cooling purposes are equally sizeable, redirecting and draining aquifer reserves no matter whether the sources are fresh, recycled, or a mix of these.
• And the facilities are massive in size, gobbling up available open space as well as fields formerly used for various agricultural purposes.

Edge demands

And here’s what I wrote about the edge processing alternative back in late 2022.

Another popular BOM-slimming approach involves leveraging a wired or (more commonly) wireless tethered local device with abundant processing, storage, imaging, and other resources, such as a smartphone or tablet. This technique has the convenient advantage of employing a device already in the consumer’s possession, which he or she has already paid for, and for which any remaining “cloud” processing bandwidth involved in implementing the complete solution he or she will also bankroll. The latency is also notably less than with the pure “cloud” approach, privacy worries are lessened if not fully alleviated, and although the smartphone’s connection to the “cloud” may periodically go down, the connection between it and the device generally remains intact.

All still valid, too, IMHO. And add to the list the facts that the alluded-to enhanced privacy not only applies in a general sense but also specific to keeping personal data out of the “cloud” provider’s training data set, and that the cessation of ongoing-cost outflows involves not only hardware but also monthly expenses for AI service subscriptions (if you’re a consumer) or tokens (for developers). However, the only downside I mentioned back then was the following.

The notable requirement for the manufacturer here is that whatever device-offloading application is running on the tethered mobile device must comprehend all common mobile operating systems (predominantly Android and iOS, along with the related iPadOS for tablets, nowadays) and the various devices that run on them, and it must also evolve as both operating systems and hardware evolve. Otherwise, the application will sooner-or-later stop meaningfully working, as will the device it’s tethered to.

Admittedly, in my defense, the device I was showcasing in that teardown heavily depended on a smartphone-based app, so it made at least some sense to focus on that nuance. But although I noted that the app leveraged the smartphone’s built-in image capture and processing resources, thereby obviating the need for costly redundancy in the accessory, I overlooked the not-insignificant and growing burden of that processing, along with the associated necessity for adequate memory—both nonvolatile for storage and volatile for code execution and temporary data—and how those memory capacity and speed needs might expand in the future.

Now we know. Not only are the not-unlimited supplies of SSDs (along with HDDs, interestingly, trading off raw performance and energy consumption for raw capacity and cost-per-bit) and DRAM being redirected to data centers, the required capacities of each in PCs, smartphones and the like for today’s edge AI processing functions are increasing in lockstep. Take, for example, the Gemini AI models embedded in latest-generation Chrome browser installs, which take up at least 4 GBytes of storage space. Or the Apple Intelligence included with iOS 27, now required vs. optional with the version 26 O/S predecessor, and using up to 14 GBytes of capacity. The similarly required-by-default AI model suite included with MacOS 27? 12-30 GBytes in size, although open source can come to the rescue in this case.

While a company called PrismML, which specializes in quantizing and otherwise compressing deep learning models for use in resource-constrained systems, was able to shrink Alibaba’s Qwen3.8 27B open-source model by between 9-10x while still matching 98% of Qwen’s aggregate benchmark scores, the resultant model was still 5.9 GBytes. Perplexity’s Portable Computer for local on-computer model storage and processing? 20 GBytes. And of course, storage needs in both cloud and edge scenarios will further increase in the future.

Hybrid intermediaries

One of many ironies here is that a not-insignificant percentage of the processing resources in data centers find use, at least on a part-time basis, not for inference but for training—initial training, periodic retraining to counteract performance decay, iterative training to encompass new and expanded datasets, and transfer learning to adapt frontier models for specific tasks. OpenAI recently reported, for example, that the training run for its latest-generation “Astra” GPT-6 fully consumed more than 100,000 GPUs. These particular operations are compute-intensive and highly parallelizable, which explains why GPU-derived architectures have come to the fore in this particular application.

For inference, conversely, only the prefill portion of the total task is parallelizable, therefore GPU-amenable (albeit not necessarily GPU-optimal). The subsequent decode portion of the total inference pipeline is conversely memory-intensive, from both capacity and bandwidth standpoints, the latter rationalizing the ascendance of advanced HBM approaches.

That all said, any claim that inference is instead going to transition fully to the edge in all cases is, once again IMHO, a pipe dream. Autonomous vehicles and other specific scenarios? Sure. But there are plenty of other applications where latency and privacy (which can alternatively be handled via encryption, anyway) aren’t an issue but the need for access to sizeable trained models is, and servers rule in such cases, as I noted in late-2024 follow-up coverage.

Hybrid approaches, in which a base level of inference occurs locally with cloud resources tapped as-needed for beefier-function requirements, will be increasingly common going forward. Alternatively, other local-ish (or, if you prefer, local networked cloud) scenarios are also beginning to emerge. Take, for example, NVIDIA’s Personal AI Router (PAIR), which enables spreading the overall inference (including agents) processing task across multiple LAN-connected computers (including non-NVIDIA-based Macs). Or instead consider storing the models on a LAN-shared NAS for common access, although RAM limitations will likely preclude full inference processing there.

Revenge of the commodity (and the proprietary)

The obvious beneficiaries of these trends include memory and broader mass storage suppliers. I admittedly find it ironic that after countless commodity boom-and-bust cycles, several of which I personally lived through from the supplier side, the semiconductor memory industry may have finally found a path to a predictable and otherwise sustainable business model.

The other potential winners are inference chip and IP core suppliers. As mentioned earlier, whereas GPU-based architectures will likely continue to reign into the future from a training standpoint (if for no other reason than proprietary software tools prevalence), an ever-increasing percentage of total growth in the AI processing space will instead be in inference, where toolset lock-ins are more fungible and other parallel-processing, not to mention more memory-centric architectures may indeed end up more optimal for the necessary tasks.

What are your thoughts on the trends I’ve identified, their root causes and beneficiaries, and their short- and long-term outcomes? Let me and your fellow readers know in the comments!

—Brian Dipert is the associate editor, as well as a contributing editor, at EDN.

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• Made by Google 2026: This limited silicon-supply situation really sucks
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• Training and inference: Two faces of AI compute
• HBM memory and AI processors: Happy together

 

The post Cloud to edge AI: If and when, to what degree, and how and why appeared first on EDN.

Cadmium telluride (CdTe) thin-film photovoltaic (PV) module maker First Solar Inc of Tempe, AZ, USA has inaugurated the first phase of its new $330m facility in Gaffney, Cherokee County, South Carolina, which onshores final production processes for the firm’s Series 6 Plus modules initiated by its international fleet...

OfficeNet, an HR technology company serving more than 10 million users across 500+ enterprises, has launched Smart Factory Solutions for large manufacturing companies. The platform is designed for organisations with over 10,000 employees and helps them manage workers across multiple locations and shifts. It brings workforce management, administrative tasks and key factory operations together on a single digital platform.

The platform brings key workforce tasks, including worker allocation, contractor management, production planning, expense claims, attendance and payroll, into one system. This reduces manual work, gives managers a clearer view of workforce availability and helps them assign workers more efficiently. It also helps manufacturers manage employees across multiple factories, locations and shifts while maintaining consistent processes.

The Officenet Smart Factory platform also covers the employee lifecycle from joining to exit, with centralised records, reporting and AI-powered analytics, along with biometric attendance, mobile absence tracking, multiple pay master’s and statutory compliance. This enables HR and business teams to move from fragmented workforce administration towards a more connected, data-led approach.

Sonali Chowdhry, CEO, Officenet, said, “Manufacturing productivity is not just about machines and automation; it is equally about how effectively people are managed and deployed. When organisations have thousands of employees working across plants and shifts, even small inefficiencies in workforce management can have a significant operational impact. With Officenet Smart Factory Solutions, we are bringing workforce data and factory processes closer together to improve visibility, reduce manual effort and help organisations make faster, more informed decisions.”

Officenet currently serves Bajaj Auto, LG Electronics, Havells, Amber Enterprises, Radnik Exports, Vishal Megamart with Smart Factory Solutions, the company is expanding its proposition beyond traditional HR technology to the Manufacturing Industry 5.0 landscape.

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AnalogAI has selected the memBrain Synaptic Analog Generative Engine (SAGE) neuromorphic hardware intellectual property (IP) from Silicon Storage Technology (SST®), a subsidiary of Microchip Technology, for its real-world edge AI processors. The analog edge AI processors feature a proprietary hardware-aware algorithm designed to train and simultaneously run inference on AI models in real-world environments.

Analog compute-in-memory for ultra-low-power edge

AnalogAI uses SST’s memBrain SAGE IP to deliver high levels of analog compute-in-memory (aCIM) performance at or below one watt for ultra-low-power edge applications. Leveraging the robust SST memBrain SAGE silicon IP, based on SST SuperFlash®, AnalogAI is developing new capabilities for real-world inference applications such as robots, drones, vehicles and humanoids that adapt to their environment.

Statements from Microchip and AnalogAI

“AnalogAI is pursuing innovative, co-optimized solutions for edge AI inference that let edge devices adapt in real time to sudden changes in the environment,” said Mark Reiten, senior vice president of the Intelligent Compute business unit at Microchip. “As the central inference engine for AnalogAI’s first products, SST memBrain SAGE IP delivers the compute performance needed together with the energy efficiency AnalogAI requires to reach its application goals. We are pleased to welcome AnalogAI as a new licensee of our SST memBrain IP, joining our rapidly expanding ecosystem.”

“AnalogAI selected SST’s memBrain SAGE intellectual property after extensive industry-wide research into the available offerings, and determined that the memBrain SAGE intellectual property allowed us to shorten development times while still achieving the ultra-low power and high performance required in our market segment,” said Jaejun Lee, chief executive officer of AnalogAI. “Analog compute-in-memory is a rapidly emerging field, and at AnalogAI we are innovating new features for edge AI devices that require real-world adaptation.”

Features of SST memBrain SAGE IP

• memBrain Tensor In-Memory Logic Element (TILE)
• memBrain solution with optimized ESF3 bitcell storing up to 8 bpc at nanoampere level
• custom memBrain solution array, decoders and driver circuits
• optimized DACs and ADCs
• summing-bias and high-voltage circuits
• nanoampere-level bitcell control logic
• proprietary memBrain test circuits
• SST memBrain technology documentation and simulation models
• full IP integration service and support

Production processes and technology roadmap

SST’s memBrain SAGE IP has been developed and delivered in 40 nm and 28 nm production processes using production-ready SuperFlash memory. The current technology roadmap includes the development of memBrain SAGE IP at 22 nm. Designed to provide reliable, high-performance, low-power non-volatile storage directly on chip, SuperFlash memory is widely used in applications that require fast access times, high endurance and data retention without the need for external memory components.

Pricing and availability

Customers interested in SST’s memBrain IP solutions and SuperFlash technology can visit the dedicated SST website or contact a regional SST sales executive through the contact page for more details.

Resources

High-resolution images are available through Flickr or editorial contact (images free to publish): Application image.

The post AnalogAI picks SST’s memBrain SAGE IP for its Edge AI processors appeared first on Open Electronics.

Renesas Electronics Corporation has introduced the RL78/G21, a new microcontroller (MCU) in its RL78 family. The company, which holds the leading global market share in 16-bit MCUs, has designed the new series for smart home appliances. The RL78/G21 combines low power consumption with built-in functions for efficient system control, helping manufacturers reduce energy use and product costs. It is designed for applications such as air conditioners, refrigerators, washing machines and microwave ovens.

Renesas has also expanded its RL78/G23 series with new microcontrollers that support more capacitive-touch inputs for advanced user interfaces. The RL78/G21 is designed for energy-efficient system control, while the RL78/G23 combines system control and user-interface functions in a single chip. This gives manufacturers more design options and can help reduce the overall cost of electronic components.

Ensuring Reliability, Security and Flexibility in Smart Appliances

For more than 15 years, the RL78 family has earned the trust of customers worldwide across a broad range of applications. The new RL78/G21 and RL78/G23 strengthen that foundation forward with enhanced security capabilities that help protect against physical threats, such as counterfeiting and cloning, as well as cyber threats, including unauthorized access, information leakage, tampering and spoofing. The RL78/G21’s high electrostatic discharge (ESD) tolerance of ±4 kV HBM contributes to higher reliability throughout manufacturing and assembly, as well as during operation of the end product. The RL78/G21 also adds the UARTA communication interface, an upgrade over the RL78/G13, enabling flexible system expansion such as the addition of sensors. Because the RL78/G21 is pin and function compatible with the existing RL78/G13 and RL78/G23, customers can transition designs seamlessly to the new devices with minimal redesign effort.

Ultra-Low-Power MCU Optimized for System Control

The RL78 family has demonstrated its ultra-low-power capabilities with products achieving top scores in the ULPMark-PeripheralProfile benchmark. Leveraging the advanced low-power technologies developed for the RL78 family, the RL78/G21 achieves an operating current of just 34 μA/MHz, nearly half that of the leading RL78/G13 MCU products. This helps reduce battery capacity, downsize power supply circuits and lower overall system costs. Optimization for system control also gives the device strong price competitiveness in the class of products with 128KB or 256KB of code flash memory. The integration of a high-speed on-chip oscillator (HOCO) with ±1.0% accuracy and 4KB of data flash eliminates the need for an external oscillator and EEPROM, reducing BOM costs.

Scalable Touch HMI Support

As demand for touch input grows with the increasing sophistication of human-machine interfaces (HMIs), Renesas expanded the RL78/G23 lineup with the RL78/G23 (R7F104G), which offers enhanced capacitive-touch sensing. Compared with the existing RL78/G23 (R7F100G), which provides 14 touch channels in the 44-pin version and 16 touch channels in the 48-pin version, the new devices significantly increase the number of touch channels to 24 and 25, respectively. Renesas provides common touch peripheral functionality and the QE for Capacitive Touch tool across the RL78, RX and RA families, enabling scalable HMI development ranging from simple user interfaces to advanced graphics displays.

“The RL78/G21 and RL78/G23 are built on the proven strengths of the RL78 family, delivering significant advances in low-power performance, reliability and security,” said Raji Mukhopadhyay, Business Division Manager, EP Mainstream MCU Business Division at Renesas. “The RL78/G21’s ±4 kV HBM ESD tolerance is a key differentiator. It further strengthens reliability, while its enhanced security capabilities address the growing need for more secure smart appliances.”

Additional Features

• Self-diagnostic functionality enabled by an IEC 60730-compliant self-test library
• Security features including flash read protection, flash shield window, Unique ID and Customer ID
• High ESD tolerance of ±4 kV HBM (Human Body Model) (RL78/G21 only)
• Pin and functional compatibility with the existing RL78/G13 and RL78/G23
• Wide operating voltage range from 1.6V to 5.5V
• Development support through Smart Configurator and the Fast Prototyping Board (FPB)

“Appliance makers are asking for more intelligence, better user experiences and stronger security without increasing cost or energy consumption,” added Mukhopadhyay. “With the RL78/G21’s ultra-low-power performance and enhanced security, alongside the RL78/G23’s expanded touch capabilities, customers can select the right MCU for their system control and HMI requirements and bring more efficient, reliable and secure smart appliances to market faster.”

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Wolfspeed Inc of Durham, NC, USA — which makes silicon carbide (SiC) materials and power semiconductor devices — has announced a multi-year agreement to supply its 1200V silicon carbide devices for the next-generation 800V SiC-based inverter platform of BorgWarner Inc of Auburn Hills, MI, USA (which provides sustainable mobility solutions for the vehicle market) as a strategic partner...

DigiKey, a global distributor of electronic components and automation products, expanded its product portfolio in the third quarter of 2026. The company added more than 27,000 new products to its in-stock inventory, making them available for immediate shipment. It also added over 507,000 products to its website and partnered with 93 new manufacturers to expand its product range.

“DigiKey’s strong inventory pipeline and in-stock availability continue to drive our record-breaking growth in revenue and customer count,” said Mike Slater, vice president of global business development at DigiKey. “Continued investments in our product portfolio, industry-leading website and global distribution center give customers quick access to the latest innovative products essential for accelerating their designs.”

DigiKey aims to keep more products in stock so that engineers, designers, makers and purchasing teams can order small quantities of components for prototypes and testing. This allows them to receive products quickly without placing large factory orders or waiting for long delivery times.

Q3 new manufacturer suppliers include:

• Alif Semiconductor, which provides the next-generation Ensemble family of microcontrollers and fusion processors, combining scalable performance, AI/ML acceleration, advanced security, integrated wireless and flexible processing for a wide range of applications.
• Chase Corporation is a global specialty chemicals company offering protective materials for high-reliability applications. Its HumiSeal  brand has over 60 years of experience providing conformal coating solutions that protect electronics across a wide range of industries.

DigiKey continues to expand its product inventory, helping engineers, designers and makers access the latest electronic components and newly launched products for their projects.

Some of the NPIs added in Q3 2026 include:

• The DFRobot LattePanda Mu Ultra, a compact x86 compute module designed for on-device AI, machine vision, local large language models and other compute-intensive edge applications.
• Same Sky’s anti-vandal switches combine rugged stainless-steel or black alloy construction with IP65/IP67 sealing, offering dependable performance in demanding industrial and outdoor applications.
• Schneider Electric’s TeSys Deca SNAP IN contactors feature tool-free, one-second conductor connections that can accelerate panel assembly by up to 96% while providing secure, vibration-resistant connections.
• Arduino’s VENTUNO Q Edge AI Computer combines high-performance AI processing, real-time control and advanced connectivity on a single platform for robotics and edge AI applications.
• The Sensirion SFA40, which combines high-sensitivity formaldehyde detection and low power consumption to enable next-generation indoor air quality monitoring devices for air purifiers, HVAC systems and portable monitors.
• The Nordic Semiconductor nRF93M1 Smart Modem delivers LTE Cat 1 bis connectivity, Wi-Fi and cellular-based positioning, along with robust security features in a compact, pre-certified module for global IoT applications.
• Amphenol RF’s high-flex RG-58 FAKRA cable assemblies combine flexible, durable construction and reliable RF performance to support automotive and industrial applications exposed to continuous movement and vibration.
• Eaton’s XVH Series supercapacitors combine high-density energy storage, ultra-low ESR and fast charge/discharge performance to support reliable backup power and energy recovery applications.
• SICK’s sensingCam SEC200 industrial code reader, which delivers reliable, cost-effective identification of 1D barcodes and 2D matrix codes, enabling simplified traceability, verification and automation across manufacturing, packaging and logistics applications.
• STMicroelectronics’ VL53L9CX direct Time-of-Flight (dToF) 3D LiDAR module delivers high-resolution depth sensing with up to 2.3K zones, accurate ranging to 9 m and low-power operation for robotics, smart building, AR/VR and industrial sensing applications.

Beyond investing in continuous inventory growth, the company recently announced a $100 million investment over the next 18 months to expand its global distribution centre and scale capacity and automation. The investment reinforces DigiKey’s position as a global leader in electronic component distribution, serving one million customers annually with more than 1.9 million products in stock and ready to ship the same day from the U.S. product distribution centre.

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Microchip Technology is expanding its 10BASE-T1S portfolio with the arrival of the LAN8679 and the LAN8680 10BASE-T1S PMD transceivers, together with the LAN8660X/1X/2X endpoint family with integrated transceivers. Designed to support next-generation zonal architectures, these solutions offer flexible, space-efficient connectivity that extends Ethernet all the way to the edge of the network.

Scalable edge connectivity for automotive and industry

As automotive, industrial and robotic systems evolve toward fully Ethernet-based networks, designers face growing demand for simplified architectures, lower wiring complexity and efficient integration of edge nodes. Microchip’s latest 10BASE-T1S devices address these challenges and are designed to meet the AEC-Q100 and ISO 26262 functional safety standards, building on Microchip’s VelocityDRIVE portfolio with additional multidrop connectivity solutions featuring an optimised interface.

OA3P interface and integrated SBC features

It provides a standardised Open Alliance 3-Pin (OA3P) interface in a compact 8-pin VDFN package, supporting space-constrained edge nodes while reducing pin count and design complexity. The LAN8680 builds on these capabilities by integrating System Basis Chip (SBC) functions, including power management, wake/sleep system control and watchdog supervision. Both devices are designed to improve reliability and safety in demanding environments such as automotive and industrial applications.

The statement from Charlie Forni

“Microchip’s latest 10BASE-T1S portfolio strengthens our commitment to enabling scalable, all-Ethernet network architectures,” said Charlie Forni, corporate vice president of the networking and connectivity business unit at Microchip. “By combining the simplicity of the OA3P interface with integrated endpoint features, these devices give designers the flexibility to build efficient and reliable systems while significantly reducing complexity at the edge.”

LAN8660X/1X/2X endpoints with integrated transceiver

Complementing these devices, the LAN8660X/1X/2X endpoint family integrates a PMD transceiver into a single-chip Remote Control Protocol (RCP) solution. This approach lets designers implement compact, fully integrated edge nodes for applications such as control systems, lighting and audio without the need for external PHY components.

Multidrop topology and lower system cost

Leveraging the 10BASE-T1S multidrop topology, Microchip’s solutions allow multiple nodes—typically eight or more—to share a single bus line. This reduces wiring weight, lowers system cost and eliminates the need for gateways, making it easier to connect sensors and actuators directly at the edge of the network.

Applications and availability

Microchip’s expanded Single Pair Ethernet portfolio targets a wide range of applications, including automotive zonal architecture, industrial automation, robotics and aerospace and defence systems. The products align with industry trends toward consolidated networks and simplified connectivity frameworks, letting designers implement efficient and scalable all-Ethernet architectures. For more information on Microchip’s Single Pair Ethernet solutions, visit the dedicated website.

Pricing and availability

The LAN8679, LAN8680 and LAN8660X/1X/2X are available in limited samples. For more information, contact a Microchip sales representative.

Resources

High-resolution images are available through Flickr or editorial contact (images free for publication).

Application image.

The post Microchip expands its Single Pair Ethernet portfolio with new 10BASE-T1S devices appeared first on Open Electronics.

Emerson has introduced new NI PXI instruments to expand its range of automated testing hardware and software. The new instruments aim to make AI-assisted testing more affordable and accessible, helping engineering teams develop tests faster and simplify product testing across different industries.

The new NI PXIe-4086 digital multimeter and new versions of the NI PXIe-5160 and PXIe-5162 oscilloscopes expand the NI PXI automated testing platform. The platform offers accurate measurements and precise timing and synchronisation when testing multiple signals and systems. It is designed for applications in semiconductor manufacturing, transportation, aerospace, defence and research. Combined with NI software and NI Nigel AI, the platform helps engineers build and automate complex testing systems more quickly while making it easier to adapt them to future requirements.

“Our new, entry-level NI PXI instruments are making NI’s AI-accelerated approach to automated test accessible to more engineering teams,” said David Hall, vice president of NI product marketing with Emerson’s test and measurement business. “By combining the industry’s most powerful platform for automated test with software that accelerates test automation, we’re helping engineers accelerate product development, solve problems faster and spend more time engineering rather than designing their test systems.”

The new instruments and software capabilities enable engineering teams to:

Build and expand test systems with more cost-effective instrument options.

• NI PXIe-4086 DMM: A cost-effective entry point into high accuracy, high-throughput measurements with 6½-digit of resolution and 35 ppm accuracy.
• NI PXIe-5160 and PXIe-5162 oscilloscopes: Up to 1.5 GHz of bandwidth in 2- or 4-channel configurations with 1 GB onboard memory options for high-bandwidth signal capture and analysis.

Move from hands-on measurement troubleshooting to automation with purpose-built test software.

• NI InstrumentStudio: New support for the latest PXI instruments and switches expands no-code configuration, system bring-up and debugging across multi-instrument systems.
• NI Nigel AI: Continued advancements of the test-optimized AI, help engineers accelerate the development and debugging of automated tests.

The new offerings build on Emerson’s earlier expansion of the NI PXI portfolio, extending the range of affordable hardware and connection into NI software available to automated test teams. Together, these additions broaden access to automated test by bringing cost-effective instrumentation, integrated software workflows and AI-assisted productivity to a common platform. Engineering teams can start with the capabilities they need today and scale as product complexity, validation demands and automation requirements grow.

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Ascent Solar Technologies Inc of Thornton, CO, USA — which designs and makes lightweight, flexible copper indium gallium diselenide (CIGS) thin-film photovoltaic (PV) panels that can be integrated into consumer products, off-grid applications and aerospace applications — was co-host of an executive networking event on 20 October in Willow Springs, California, that brought together leaders and innovators from across the commercial space industry to discuss emerging technologies, mission requirements, and opportunities for future collaboration...

AXT Inc of Fremont, CA, USA — which makes gallium arsenide (GaAs), indium phosphide (InP) and germanium (Ge) substrates and raw materials at plants in China — says that its majority-owned China-based wafer manufacturing subsidiary Beijing Tongmei Xtal Technology Co Ltd has entered into definitive agreements for a private equity financing to fund further expansion of its manufacturing capacity for indium phosphide substrates, expansion of its principal business operations, capital expenditures, and general working capital. The financing agreements provide for a private equity investment in Tongmei by certain institutional investors of a minimum of RMB1,912,350,000 (about US$285m) and up to a maximum of RMB3,668,639,053.25 (about US$545m) in ordinary shares of Tongmei...

Particularly in consideration of current (and over-time increasing) semiconductor constraints, this has been a surprisingly busy (albeit pricey) October from a systems-release standpoint.

Nearly two months ago, as is typical for the season, Apple announced new smartphones, watches and earbuds. Several weeks before that, the company had somewhat-typically-for-fall unveiled two new processors and systems containing them. But wait, there’s more. Just two weeks back, and atypically, Apple had rolled out more hardware, this time for the smart home. And this week? Three straight days of even more hardware. Very atypical.

I’ll get to Apple’s most recent news shortly. But it wasn’t the only tech heavyweight to unveil new mobile computing devices—a mix of laptops and tablets—this month.

Microsoft and Nvidia go “Ultra”

Last November, within my yearly “Holiday Shopping Guide for Engineers” (this year’s edition which I’m now reminded I need to begin writing shortly), I suggested (among other things) you consider purchasing, for others and/or yourself, Nvidia’s DGX Spark mini AI workstation.

(it’s the gold-colored device to the right of the laptop, not the laptop itself. Hold that thought).

As background info for today’s discussion, I noted the following back then.

Its application processor, originally referred to as the N1X, is now renamed the GB10. Co-developed by NVIDIA (who contributed the Grace Blackwell GPU subsystem) and MediaTek (who supplied the multi-core CPU cluster and reportedly also handled full SoC integration duties), it was originally intended for—and may eventually still show up in—Arm-based Windows PCs. But repeated development hurdles have (reportedly) delayed the actualization of both SoC and system shipment aspirations, and lingering functional bugs preclude Windows compatibility (therefore explaining the DGX Spark’s Linux O/S foundation).

Those bugs have apparently finally been squashed—or at least sufficiently worked around—because Nvidia and lead mobile systems partner Microsoft publicly released the Surface Laptop Ultra on October 7. The history lesson here is interesting (IMHO, at least) and instructive.

Microsoft has been steadily working on Windows-on-Arm, spanning operating systems, applications suites and hardware to run them on, since June 2012 with the Windows Surface RT, which was powered by the multi-core Arm Cortex-A9-based Nvidia Tegra 3 SoC.

 

From then until now, everything else Arm-related, including my latest Surface Pro 11 “Plus” acquisition (along with several generations of developer-tailored desktop hardware), ran Qualcomm-developed silicon, even if the SoCs were Microsoft-stamped. But Nvidia’s back, baby. And it’ll only cost you $2,599 (baseline, as much as $5,899.99 top-end) to own one. With delivery “later this year” (which, I’m compelled to note, has only two more months left in it as I type this). Gulp.

Two versions of the Nvidia RTX Spark N1X (apparently, in a clarification of the earlier rename mention, both GB10 and N1X are valid monikers, for different system form factors) exist, both with the same NPU core inside:

• 5120-core GPU and 18-core CPU, and
• 6144-core GPU and 20-core CPU

System memory ranges from 24 GB to 128 GBytes in capacity, LPDDR5x DDR unified in all configurations. SSD options start at 512 GBytes (PCIe Gen 4), with 1 and 2 TByte PCIe Gen 5 configurations also offered. And by the way, an RTX Spark-based developer platform, $5,999.99 and up, is also available for pre-order (perhaps a replacement for the canceled Qualcomm one?).

Amazon loves generic Android (again)

Next stop: tablets. I’ve said it before, I’ll say it again today, and I’m unfortunately sure I’ll be saying it more in the future, given where semiconductor building block prices and tariffs are going: when your bill-of-materials costs increase, the best way to “hide” them is to bail on entry-level models and conversely double-down on already-profit-margin-padded high-end product variants. Enter Amazon’s no-longer-Fire, now Alexa-branded, latest-generation tablets.

Plastic cases are gone (except for the kiddie-tailored ones), replaced by thin unibody aluminum chassis, wrapped around higher-quality LCDs, multi-speaker arrays and other integrated goodies. Gone too is access to the Amazon Appstore (which won’t be a surprise to anyone who read my last-October Amazon coverage); Amazon’s back to leveraging the Google Play Store.

More generally, the new tablets run “vanilla” Android instead of the “forked” Fire OS precursor. They come in 8”, 11” and 12” “Pro” flavors, each with multiple storage capacity tiers (along with two DRAM capacity options for the 8” version, interestingly), with prices starting at $299 and ranging up to $679.99, not including cases or the high-end model’s optional pen and keyboard accessories.

Speaking of October Amazon coverage, by the way, the company chose today, at the tail-end of competitor Apple’s three-day announcement cadence, to roll out this year’s collection of Echo speakers (one even complete with a camera? SMH), smart displays and such. I won’t be covering them in this particular piece, so to tide you over until I have time to discuss them, I’ll hand you over to Engadget (or any of the other usual suspects, for that matter) for coverage purposes.

Touch me. Finally.

And speaking of unwise chronological congruity, what did Apple roll out this week? Monday brought a new generation of the iPad mini (the prior generation of which, which I own, was dubbed “cute” by my wife just the other day), no longer with a trailing-edge SoC versus its larger siblings (now with the A20 Pro), and with a slightly larger display (8.5” in diameter this time) that, even more impactfully, switches from LCD to OLED. The front camera is conveniently relocated to the landscape edge, too. And yes, all this goodness is accompanied by price increases. The entry-level 128 GByte Wi-Fi-only variant of my 2024 model was originally $499 but got bumped by Apple up to $599 in June of this year, while this year’s edition is $699 and up. Yup.

 

Yesterday? Thanks for asking. The 14” (but not 16”, interestingly…the same thing happened last year, so I’m guessing the larger one’s “Pro” and “Max” only from here on out) entry-level version of the MacBook Pro now runs the M6 SoC, versus last year’s M5, while the 24” iMac makes a two-gen (and associated two-year between-updates) jump from the M4 to the M6.

Yep, that’s basically it; form factors, etc. remain unchanged. Yawn. Even the MacBook Pro stock image shown above, from Apple’s press release, was boring. And if I was a betting man, I’d lay my odds on the earlier-leaked theory that the next SoC iterations of the higher-end “Pro” and “Max” MacBook Pro variants will await the M7 Apple Silicon generation.

Apple instead “kept its powder dry” for today’s unveiling of its first touchscreen-augmented (and broader PROLED XDR-based) computers, MacBook Pro laptops in both 14” and 16” display and both M5 Pro and Max SoC options.

Now that’s a snazzy stock image…err…video, right? Unsurprisingly, there’s a whole lot of underlying software evolution of both MacOS and key apps such as the Safari browser (beta-examination insights into the latter which were discovered two weeks back) as enablers of the enhanced hardware. And equally unsurprisingly, those hardware enhancements come with an associated price tag increase. Depending on size and configuration, you could pay anywhere from $2,899 to…hold your hat…$14,549 for the privilege of a display that responds to your touch.

You may now pick yourselves up from the floor and climb back in your seats. Although I’m sure Apple’s done no shortage of advance market research, including conversations with potential customers under NDA, I’m admittedly somewhat skeptical about the prospects for long-term high volume success here. I say this although I have absolutely no doubt in the first-generation fiscal-and-other enthusiasm of technology early adopters, and even though I acknowledge (in a nod to my earlier Microsoft Surface case study comments) that Apple’s a late adopter here as compared to Windows-powered touchscreen counterparts (along with its own iPad, for that matter).

Speaking of case studies, let’s take me as an example. Including my current x86-based Surface Pro 7+ (and spare, along with two Pro 8+ successors in the queue) and earlier mentioned Arm-based Pro 11 models, I’ve to date purchased nine (six to-date actively used) touchscreen Windows laptops, if my recollection is correct. But I’ve barely used their touchscreens at all, far from for any meaningful period of time.

Partly, speaking of fiscal blessings, it’s because I’ve in-parallel owned multiple generations of iPads. And to that point, I’m most enthused about the concept when it’s applied to hybrid systems like the Surface Pro that can operate as both a tablet and a laptop, depending on if a physical keyboard is connected at the time. But that’s not the form factor of these new MacBook Pros. And I’d wager that anyone who’ll buy one is capable of buying an iPad (or few), too.

Thoughts, readers? Let me know in the comments!

—Brian Dipert is the associate editor, as well as a contributing editor, at EDN.

Related Content

• Apple’s processor cadence: A pending stutter-step for improved long-term edge inference?
• The Microsoft-reminiscent iPhone Duo: How much customer holding-and-folding is necessary to keep Apple from folding on the experiment?
• Apple heads Home: Distributed identity validation, and how much does Matter matter?
• Amazon and Google: Can you AI-upgrade the smart home while being frugal?
• The Microsoft Surface Pro 5 succession: Selections, motivations, and initial impressions

The post Amazon, Apple and Microsoft: New mobile computing platforms take off appeared first on EDN.