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Quectel’s 4G SH602FA and 5G SE505FE smart modules feature built-in Android 16 to accelerate industrial and commercial IoT development. The modules enable developers to build connected products such as handheld terminals and inspection devices with rich user interfaces and enhanced multimedia performance.

The 4G SH602FA is powered by a MediaTek MT8786 chipset with a 64-bit octa-core processor comprising two Arm Cortex-A75 cores and six Cortex-A55 cores. An Arm Mali-G52 MC2 GPU supports graphics-intensive embedded applications without requiring an external host processor. The smart module integrates LTE Cat 4, Wi-Fi 802.11ac, Bluetooth 5.1, and GNSS, along with camera and touch-panel interfaces. 

Offering Android 16-powered 5G connectivity, the SE505FE leverages a MediaTek MT8863T chipset with a 64-bit octa-core processor comprising two Arm Cortex-A76 cores and six Cortex-A55 cores, along with an Arm Mali-G57 GPU. The module supports 5G sub-6-GHz and LTE Cat 4, together with Wi-Fi 6, Bluetooth 5.2, and GNSS.

A timeline for module availability was not provided at the time of this announcement.

SH602FA product page 

SE505FE product page 

Quectel Wireless Solutions 

The post Smart modules bring Android 16 to IoT designs appeared first on EDN.

A Class-D mono audio amplifier, the PAM2011Q from Diodes delivers up to 3 W of output power for automotive applications. Designed for instrument clusters, dashboard and backup cameras, driver notification chimes and warnings, and emergency call (eCall/T-box) systems, the filter-free amplifier provides 1.8-mA quiescent current and up to 94% efficiency.

The PAM2011Q comes in a compact, thermally enhanced package and requires minimal external components, simplifying design and reducing system cost. It operates from a 2.8-V to 6.0-V supply and delivers 2.53 W at 1% THD and 3.15 W at 10% THD from a 5-V supply into a 4-Ω load. Audio specifications include THD+N below 0.03% and 21-µV integrated output noise (A-weighted) at 6-dB gain.

The amplifier is AEC-Q100 qualified and operates over a junction temperature range of -40°C to +125°C. Integrated de-pop circuitry provides silent startup and shutdown while eliminating unwanted noise. Overvoltage and overtemperature protection with auto-recovery are also integrated to enhance system reliability.

The PAM2011Q is available now from Mouser Electronics.

PAM2011Q product page

Diodes Inc.

The post Class-D amplifier enhances automotive audio performance appeared first on EDN.

The Vertex 6.0 channel emulation platform from VIAVI supports carrier frequencies up to 23.6 GHz and 400 MHz of instantaneous bandwidth. The company says it is the industry’s first channel emulator for 6G and Wi-Fi 7/8 testing, meeting newly defined 6G waveform requirements and exceeding Wi-Fi 7/8 bandwidth requirements. The enhanced platform features field-replaceable RF modules that can be installed in an existing 6U Vertex chassis.

Building on the 5G FR1/FR2 capabilities of the previous generation, Vertex 6.0 recreates real-world wireless conditions in the lab for complex cellular, Wi-Fi, military, and aerospace RF applications. Combined with the VIAVI FR3 MIMO converter and raytracing, the platform serves as a digital twin for RF propagation, enabling use cases such as FR3, Wi-Fi 7, AI-RAN, and ISAC.

Each chassis accommodates 36 RF ports, 256 digital links, and up to 1.6 GHz of bandwidth. For cellular technologies, the platform handles FR3 bands with up to 1 GHz of bandwidth. For Wi-Fi 7/8, it offers native support for 320 MHz and 4096 QAM in 2×2 to 8×8 configurations. The channel emulator supports land-to-land, land-to-air, and air-to-air transmissions, including anechoic and reverberation OTA chambers, NTN (LEO, MEO, and GEO), mesh, drone, and ISAC networks.

Vertex 6.0 product page

VIAVI Solutions  

The post Channel emulator adds 6G, Wi-Fi 7/8 testing appeared first on EDN.

Kinetic Technologies’ KTS1642Q AEC-Q100-qualified load switch protects automotive loads from abnormal power-supply or load conditions. When used with the appropriate external TVS diodes, the device supports ISO 7637-2 transient requirements while helping designers address the electrical stress conditions of ISO 16750-2.

Operating from 4 V to 40 V, the KTS1642Q integrates two N-channel MOSFETs with 41-mΩ on-resistance and delivers 6 A of continuous output current. It provides reverse-battery protection to -28 V, fixed 20.3-V overvoltage protection with a typical 360-ns response time, overtemperature protection with auto-retry, battery detection, and a fault flag output. Input ESD protection meets IEC 61000-4-2 Level 4, with ±2-kV HBM ESD protection on other pins per AEC-Q100-002.

The load switch operates over a temperature range of -40°C to +125°C and is supplied in a 4×4-mm TDFN. The KTS1642AQGDV-TR features an active-high enable, while the KTS1642QGDV-TR features an active-low enable. Both versions are available now.

KTS1642Q product page 

Kinetic Technologies 

The post Load switch guards automotive power rails appeared first on EDN.

Standard MCUs in Toshiba’s TXZ+ Series M4V Group enhance security and data management in IoT devices and industrial control equipment, ranging from smart home appliances to factory automation systems. The devices feature a multilayered security architecture that combines access control, memory protection, and execution control functions, helping protect systems against unauthorized access and program tampering.

Based on an 80-MHz Arm Cortex-M4 core with an FPU, the M4V MCUs’ on-chip memory includes 128 KB of code flash, 64 KB of data flash, and 32 KB of RAM with parity support. Both flash memories support up to 100,000 rewrite cycles, and dual mode enables one flash area to be rewritten while instructions are executed from the other. The data flash can retain rewritable data such as configuration and log data, enabling data management tailored to the operating conditions of the equipment.

The MCUs operate with a supply voltage of 2.7 V to 5.5 V, making them suitable for consumer and industrial equipment with 5-V power supplies. An integrated 10-MHz oscillator provides ±1% frequency accuracy over the full operating temperature range of -40°C to +105°C, eliminating the need for an external oscillator.

Toshiba has started shipping engineering samples of the TXZ+ Series M4V Group MCUs. The M4V Group includes four package options to accommodate different PCB sizes and assembly requirements.

TXZ+ M4V Group product page 

Toshiba Electronic Devices & Storage

The post MCUs strengthen security in IoT and control systems appeared first on EDN.

HexSeed Technology Ltd of Banchory, near Aberdeen, Scotland, UK has raised more than £600,000 in an early-stage funding round led by Carbon13, with participation from Net Zero Technology Centre and Vento Ventures. The cumulative investment unlocks a Partnership Grant from overnment agency Innovate UK (part of UK Research and Innovation), awarded on a provisional basis earlier this year...

Clas-SiC Wafer Fab Ltd of Lochgelly, Fife, Scotland — which was founded in 2017 and is the UK’s only commercial wafer fabrication facility dedicated to silicon carbide (SiC) — is one of the first recipients of Scottish Enterprise’s new Capital Grant, which has been designed to help drive levels of business investment and productivity. As part of a £12m company investment, the £1.9m government grant will support the growth of Scotland’s Critical Technologies supercluster...

📢 День Першокурсника 2026 kpi ср, 08/19/2026 - 21:06

Panasonic Industry Europe announces the release of its new ECWFJ series of metallized polypropylene film capacitors, developed to support cost-effective designs while maintaining a high level of safety and long-term reliability. The new series is aimed at engineers working across industrial and automotive power electronics (it is qualified to AEC-Q200 standards) who require dependable performance under demanding environmental conditions.

The ECWFJ series demonstrates proven resistance to moisture, maintaining stable operation under conditions of 40°C and 95% relative humidity for up to 1.000 hours. This ensures long-term reliability even in humid environments, while still offering a cost-efficient solution. As a result, the capacitors are well suited for a broad range of industrial uses as well as automotive applications.

Typical application areas include electric mobility systems such as DC/DC converters, on-board chargers and e-compressors, along with solar inverters and EV charging infrastructure. The series is also designed for use in industrial power supplies, LED lighting, smart meters and embedded power systems, where consistent electrical performance and durability are essential.

Technically, the ECWFJ series covers voltage ratings from 600V up to 1.100V DC. Capacitance values range from 1µF up to 12µF. The capacitors operate across a temperature range from -40°C up to +110°C, with the 1.000V variant rated up to 105°C. The devices are engineered to withstand thermal shock from -55°C up to 85°C over 1.000 cycles and can tolerate maximum ambient temperatures of up to 125°C for limited durations.

Panasonic’s proprietary patterned metallization with an integrated fuse mechanism helps ensure stable capacitance over the lifetime of the component and enhances overall system reliability. The design is complemented by a flame-retardant plastic enclosure and non-conductive resin, supporting compliance with UL and other regulatory standards. In addition, the capacitors are fully compliant with RoHS requirements.

The post New Cost-Effective Metallized Polypropylene Film Capacitors for Industrial and Automotive Applications appeared first on ELE Times.

This basic beat oscillator makes continuous wave keyed code and single sideband suppressed carrier signals audible.

A recent Design Idea from contributor Gavin Watkins shows an inexpensive add-on beat frequency oscillator (BFO) for inexpensive and vintage short-wave radio receivers.  It makes reception of highly efficient amplitude modulation transmission formats like CW (continuous wave keyed code) and SSBSC (single sideband suppressed carrier) possible on basic, inexpensive radios that otherwise couldn’t.  It’s very cute and thrifty.

Wow the engineering world with your unique design: Design Ideas Submission Guide

Today’s Design Idea (Figure 1) does a similar job, but takes less space while needing only about half as many components.  Also, the parts it does require are easier to source.

Figure 1 This 455 kHz intermediate frequency beat frequency oscillator is tuned by R1.  The amplitude of the injected IF signal is adjusted by R3.  It works happily with a wide range of supply voltages and so needs no regulator.

Here’s how it works.

Both single-sideband suppressed carrier (SSBSC) and (the somewhat misleadingly named) keyed continuous wave (CW) radio transmissions share the lack of a steady carrier wave reference.  Eliminating the carrier and redundant sideband is good because it increases transmission efficiency in both bandwidth and transmitter power utilization.  But it adds complexity to the receiver because then it must provide the missing reference frequency to produce an audible and intelligible signal. 

Some basic, mainly older, receivers can’t do that.  What to do for them?  We can simply tack on a BFO. An add-on BFO works by injecting a low-level signal into the receiver’s IF chain that:

1. Is manually adjustable to be the correct amplitude that allows the receiver’s existing automatic gain control (AGC) loop to respond to and follow the incoming RF signal normally.
2. Is tuneable to accurately match and sum with the IF frequency so that, when mixed with the IF signal by the receiver’s final detector, it can recreate the SSB suppressed carrier and modulation audio.

The oscillation frequency is given by the following equation:

Fo = 1/(ln(2)(R3 + R4)(C1 + Cs) + Td)
where
Cs = stray capacitance = ~15pF
Td = internal 555 delay (See Related Content link #2) = ~212ns

With the component values shown, it’s tunable over 455 kHz +/-20%.

The oscillator output is taken from pin 7 rather than 3 to maximize isolation and minimize coupling between the IF chain and BFO oscillation frequency.  This is important for audio quality. 

The output amplitude is adjusted by R3 over a range of 0 to (V+)/2.

Stephen Woodward‘s relationship with EDN’s DI column goes back quite a long way. Over 200 submissions have been accepted since his first contribution back in 1974.  They have included best Design Idea of the year in 1974 and 2001.

Related Content

• Add-on beat frequency oscillator (BFO) for shortwave radio
• Improve 555 frequency linearity
• Add one resistor to give bipolar LM555 oscillator a 50:50 duty cycle
• Gated 555 astable hits the ground running
• Can a free running LMC555 VCO discharge its timing cap to zero?

The post Single sideband radio meets LMC555 beat frequency oscillator appeared first on EDN.

EPC Space LLC of Andover, MA, USA (which manufactures high-reliability radiation-hardened enhancement-mode gallium nitride-on-silicon discrete transistors, ICs and modular devices for power management in space and other harsh environments) has announced three new eGaN power transistors in plastic surface-mount packages, designed to deliver high-performance power conversion for next-generation space computing systems...

For its fiscal full-year 2026 (ended 27 June), Lumentum Holdings Inc of San Jose, CA, USA (which designs and makes optical and photonic products for optical networks and lasers for industrial and consumer markets) has reported revenue of $3014m, up 83.2% on fiscal 2025’s $1645m...

​A team of researchers at Penn State University has now come up with a bio-hybrid device that pairs custom-synthesised human DNA with a perovskite crystalline semiconductor to present a new form of low-power data storage and computation. Their study was published in Advanced Functional Materials in the latest edition released August 17, 2026. Such a device may in time help reduce the energy used for powering AI computing centres and huge data centres, the scientists say.

The technology addresses a growing challenge in modern computing: the enormous energy required to model and process data. An increasing number of high-performance AI workloads and the overall compute and memory demand of data centres mean that there is pressure to find a more efficient way to store and process data.

The researchers used synthetic DNA – a chemically engineered molecule arranged into short molecular sequences and a crystalline perovskite semiconductor material (used in things like solar cells and electronics). The combined pair of these materials created a memristor: a type of electronic memory that retains clues about its past electrical experience.

Such technology could potentially go toward energy-efficient AI-computing hardware; as well as data centres and even the burgeoning field of neuromorphic computing by coupling the storage and processing information within the same device.

The development highlights a broader trend in semiconductor research: instead of relying solely on conventional silicon scaling, researchers are exploring biological materials, memristors and unconventional computing architectures to address the energy and memory demands of next-generation AI systems.

The post DNA-Powered Memory Could Cut Computing Energy Use by 100x appeared first on ELE Times.

Nuvoton Technology is preparing to begin mass production of its KA49703A and KA49713A battery monitoring ICs (BMICs) in September 2026. The devices are designed for Battery Backup Units (BBUs) used in AI servers, helping monitor battery-cell conditions and support reliable power management in high-performance computing systems. As AI servers become critical infrastructure supporting modern society, ensuring continuous operation requires highly reliable power systems capable of running 24/7 throughout the year. By leveraging the company’s proven automotive-grade daisy-chain communication technology in high-voltage 400V/800V BBU applications, the KA49703A and KA49713A help realize highly reliable and efficient power architecture.

Achievements:
1. Supports daisy-chain communication and connection of up to 55 devices, simplifying large-scale battery system design.
2. Incorporates a transportation and storage mode that extends storage duration and reduces operational costs.

Data centers are mission-critical infrastructure that must operate continuously without interruption. Consequently, their power systems require exceptional reliability and stability. In recent years, the rapid growth of generative AI and cloud services has significantly increased AI server power consumption, driving demand for higher efficiency and reliability in power delivery systems.

At the same time, adoption of 400V and 800V high-voltage power architectures is accelerating to improve power efficiency,
while server and power-system densities continue to increase. These trends require battery systems not only to provide safe
monitoring under high-voltage conditions but also to ensure long-term reliability and low thermal generation during continuous
operation.

Battery systems are no longer simply backup power sources for outages. They now play an increasingly important role in
absorbing instantaneous power fluctuations, protecting systems, and ensuring service continuity, making them foundational
technologies for modern data centers and communication infrastructure.

Building on its proven automotive daisy-chain communication technology, Nuvoton has developed the KA49703A and KA49713A battery monitoring ICs for high-voltage 400V/800V BBUs used in industrial and infrastructure applications. Mass production is scheduled to begin in September 2026.

The KA49703A and KA49713A can accurately monitor up to 16 battery cells while integrating communication functions for high- voltage systems and safety features such as cell anomaly detection, addressing the demanding requirements of next generation energy storage systems.

Features of New Product:

1. Daisy-Chain Communication Supporting up to 55 Devices
AI-server BBUs and Energy Storage Systems (ESS ) operating at 400V/800V levels require large numbers of lithium-ion battery cells connected in series. Conventional battery monitoring systems typically require a dedicated MCU and isolation device for each monitoring IC. As cell counts increase, component count and communication wiring also increase, creating challenges in communication reliability and system complexity.

To address these issues, the KA49703A and KA49713A incorporate daisy-chain communication technology. Multiple battery monitoring ICs can be connected in series, enabling systems with up to 55 devices while minimizing wiring requirements and ensuring robust communication even in high-voltage environments. This architecture reduces the need for additional MCUs and isolation components, simplifying system design, reducing component count, minimizing board space, and improving overall reliability. The compact QFP-48 package (7 mm × 7 mm) also helps address the stringent space constraints found in AI server BBUs. Combined with high-precision voltage measurement accuracy of ±2.9 mV, the device enhances both monitoring performance and safety in next-generation power systems.

2. Transportation and Storage Mode Reduces Maintenance Costs

AI-server BBUs and large-scale ESS installations contain numerous lithium-ion cells and are often transported over long distances by ship or truck. Minimizing power consumption during transportation and storage is therefore essential.

However, conventional ICs incorporating daisy-chain communication typically exhibit increased shutdown current, leading to
battery drain during storage and transport.

To solve this issue, the KA49713A incorporates a dedicated transportation and storage mode that reduces shutdown current to less than 0.1 μA.

This significantly minimizes battery depletion during transportation and storage, extends allowable storage periods, reduces recharge requirements, and contributes to lower operating costs.

These battery monitoring ICs enable customers to address increasing power demands in the AI era and the transition toward higher-voltage power systems. They support improved reliability and operational efficiency in energy storage systems for data centers, industrial equipment, and social infrastructure.

Through continued expansion of its BM-IC product lineup, Nuvoton will further advance battery monitoring technologies and contribute to realizing a sustainable and highly reliable energy society.

Applications:

・Battery Backup Units (BBUs) for AI servers
・Large-scale Energy Storage Systems (ESS)

Product name:

Industrial Battery Monitoring ICs
・KA49703A
・KA49713A

Specifications:

Start of mass production:

Sep. 2026

Definitions:

• BBU (Battery Backup Unit). A backup power system equipped with rechargeable batteries, such as lithium-ion batteries, that supplies power during outages or momentary voltage drops.
• Daisy-Chain Communication. A communication method in which multiple monitoring ICs are connected in series. It reduces wiring complexity while providing high immunity to electrical noise.
• ESS (Energy Storage System). An energy storage system used for renewable energy integration, peak load management, and power supply-demand balancing.

 

The post Nuvoton Launches Mass Production of 16-Cell Battery Monitoring ICs with Daisy-Chain Communication for AI Servers appeared first on ELE Times.

I read the different values on each tap in can capactor the get a single matching cap with equal or greater voltage and temp. Then set them as you see on a daughterboard, binding all grounds to a common ground post. Then run wiring to the appropiate terminal or junction of where that value capactor was in the circuit before. I find this way an efficient and orderly way to replace older multi-can capactors. The daughter board is attached to chassis by one or two small, "L" brackets. submitted by /u/RefrigeratorLess9786 [link] [comments]

Ascent Solar Technologies Inc of Thornton, CO, USA – which designs and makes lightweight, flexible copper indium gallium diselenide (CIGS) thin-film photovoltaic (PV) panels that can be integrated into consumer products, off-grid applications and aerospace applications – plans to expand testing of its CIGS PV technology beyond low Earth orbit (LEO) as the firm has received an increase in requests for solar solutions capable of supporting missions across multiple orbital environments. Ascent is preparing a series of in-house characterization campaigns designed to validate the survivability and performance of its thin-film solar technology in increasingly challenging space conditions, concluding in fourth-quarter 2026...

🎓 Додатковий набір до КПІ ім. Ігоря Сікорського на бакалаврат kpi вт, 08/18/2026 - 18:26

The future of advanced packaging is not one universal package. It’s a technology platform capable of placing the right interconnect, material, die, memory stack, optical engine, and thermal structure at the right system boundary.

For many years, the design sequence appeared straightforward:

Design the chip → select the package → connect it to the board

That sequence is becoming less accurate. AI accelerators, high-bandwidth memory (HBM), chiplets, optical I/O, advanced cooling, and high-current power delivery are now so tightly coupled that the package can no longer be selected after the system architecture is largely complete.

The package increasingly determines:

• How the system can be partitioned
• How many chiplets can be integrated
• Where silicon-class interconnect density is required
• Where broader and lower-cost routing is sufficient
• How HBM is placed and connected
• Where electrical path should transition to optic
• How power reaches the compute elements
• How heat leaves the package
• How assembly can be manufactured, tested, repaired, and qualified

The package is no longer merely supporting the system. It’s defining what system can be built.

From package choice to packaging platform

Traditional packaging discussions often compare individual technologies:

• Should the design use a silicon interposer?
• Would a local silicon bridge be sufficient?
• Should fan-out redistribution replace part of the substrate?
• Should the system use 2.5D or 3D integration?
• Should optics remain at the front panel, move near the package, or become co-packaged?

These remain important questions, but they are no longer independent choices. A modern AI system may require several of these technologies at the same time.

A broad interposer may connect compute chiplets and HBM. Here, localized bridges may provide silicon-class density only at selected die boundaries. And fan-out redistribution may extend routing across a larger area. Next, vertical stacking may integrate cache, memory, control, or specialized processing. Then there are optical engines that may sit near the package edge.

A thermal structure may also need to remove highly non-uniform heat from several dies with different power densities. Finally, the system may also require test access, known-good-die strategies, repair paths, redundancy, and manufacturing flows that span several suppliers. This is why advanced packaging is moving from isolated process choices toward integrated technology platforms.

A platform does not force every product into one structure. It provides a coordinated set of technologies from which the system architect can select the right realization method for each boundary.

Vertical integration’s two meanings

The phrase vertical integration is often interpreted physically. But that is the first meaning.

Physical vertical integration

Dies, memory stacks, interconnect layers, optical engines, power-delivery structures, and thermal components are placed beside or above one another. This includes technologies such as:

• 2.5D integration
• 3D die stacking
• Package-on-package structures
• Through-silicon or through-glass vias
• Vertically-integrated power delivery
• Stacked memory and logic

Physical stacking is important because it can shorten interconnects, increase bandwidth density, reduce footprint, and place functions closer together. But there is a second meaning that may be even more important.

Technology platform integration

Different packaging technologies become coordinated elements within one ecosystem. A platform may combine:

• Broad-area fan-out routing
• Localized silicon bridges
• Full silicon interposers
• Vertical stacking
• System-in-package integration
• Co-packaged optics
• Assembly and bonding processes
• Package-level test
• Thermal and mechanical structures
• Manufacturing and reliability flows

In this model, vertical integration does not mean that every component must be stacked. It means the complete realization capability is integrated across design, materials, process, assembly, test, and system requirements. That is the deeper transition.

In other words, the future is not one package replacing all others. It’s a platform selecting the right precision, material, and integration method at each boundary.

Different boundaries need different precision

One of the most important architectural questions is: How much of the package truly requires silicon-class interconnect density?

A full silicon interposer can provide extremely dense routing and short connections across a broad area. But that precision comes with cost, area, yield, manufacturing, and mechanical consequences. Not every connection requires the same pitch or routing density.

Some die-to-die boundaries may require very fine-pitch interconnect. Other regions may only need moderate-density redistribution. Still others may be adequately served by an organic substrate or board-level connection.

A platform approach allows the package to become hierarchical: Silicon-class density where necessary.

• Fan-out or redistribution where broader routing is needed
• Substrate-level routing where lower density is sufficient

This avoids using the most expensive and complex technology everywhere. The objective is not maximum integration at every location; the objective is appropriate integration at every boundary.

Fan-out more than a package format

Fan-out packaging is often discussed as a package category. But within a larger platform, fan-out can perform several architectural roles. It can:

• Provide broad redistribution beyond the original die footprint
• Support heterogeneous die integration
• Reduce dependence on a large silicon interposer
• Connect local high-density regions to broader package routing
• Create a transition between chiplet-scale and substrate-scale interconnect
• Support system-in-package or package-on-package structures

Fan-out chip-on-substrate approaches can combine redistribution-layer density with the mechanical and routing capabilities of a larger package substrate. A fan-out bridge architecture can place localized silicon-class interconnect only where adjacent dies require it.

This allows precision to be concentrated rather than distributed uniformly across the complete package. That is not simply a manufacturing variation; it’s an architectural choice about where density should reside.

Bridges and interposers are complementary

Silicon bridges and full interposers are sometimes presented as competing technologies. They are better understood as different tools.

A broad interposer can provide:

• Dense routing across a large region
• Extensive die-to-die connectivity
• Controlled electrical paths
• Close integration between compute and HBM
• Broad placement flexibility

A local bridge can provide:

• Very high density at selected chiplet boundaries
• Reduced silicon area
• More localized precision
• Potentially lower cost for systems that do not require a full interposer
• A path to combine high-density and conventional routing within one package

The correct decision depends on:

• Die placemen
• Required pitch
• Routing density
• Signal reach
• Power delivery
• Thermal expansion
• Warpage
• Assembly tolerance
• Yield
• Test
• Cost

A packaging platform should therefore not declare one technology universally superior. It should allow the architecture to place each technology where it creates the greatest system value.

HBM makes package a compute boundary

HBM has already transformed the package. The connection between the accelerator and HBM is no longer a peripheral interface; it’s part of the compute architecture.

HBM placement determines:

• Achievable bandwidth
• Energy per bit
• Interposer or bridge requirements
• Package area
• Routing density
• Power delivery
• Thermal interaction
• Mechanical balance
• Yield and assembly complexity

As the number of HBM stacks grows, the package becomes larger and more difficult to manufacture. So, the system must manage:

• Interposer scale
• Reticle boundaries
• Die placement accuracy
• Warpage
• Underfill
• Bump reliability
• Heat-spreader geometry
• Non-uniform thermal loading
• Package-level test

The package is therefore not merely connecting compute to memory. It’s determining the physical shape of the compute system.

CPO an element of the platform

Co-packaged optics (CPO) is often treated as a separate technology story. But CPO cannot scale independently from advanced packaging. Moving the optical engine closer to a switch ASIC or accelerator may reduce electrical reach, SerDes power, and front-panel density pressure.

It also introduces new package-level responsibilities:

• EIC-to-PIC connectivity
• Optical attach
• Fiber routing
• Laser placement
• Wavelength control
• Thermal drift
• Calibration
• Optical test
• Compound yield
• Repairability
• Serviceability

A future AI package may combine:

• Compute dies
• HBM
• A full or partial interposer
• Localized bridges
• Fan-out redistribution
• Electrical I/O chiplets
• Optical engines
• External laser interfaces
• Power delivery structures
• Integrated cooling

CPO is therefore not simply another component added beside the ASIC. It changes the electrical, thermal, mechanical, manufacturing, test, and serviceability boundaries of the complete package. However, the package must create the environment in which optical performance can ensure repeatable system performance.

Optics moves inward only when the package platform can absorb the consequences of moving it inward. This is why CPO belongs inside the larger packaging-platform discussion.

Thermal architecture chosen with the package

As more functions move into the package, thermal design can no longer be treated as an external cooling problem. Different dies produce different heat fluxes. HBM, compute chiplets, I/O dies, optical engines, voltage-regulation structures, and control electronics may all have different temperature limits.

The package architecture determines:

• Which devices share a heat spreader
• Where thermal-interface materials are placed
• How bond-line thickness is controlled
• Whether a lid, cold plate, vapor chamber, or direct-liquid structure is required
• How mechanical pressure is distributed
• How thermal expansion affects interconnect reliability
• Whether optical alignment drifts with temperature

A package platform must therefore support more than electrical connectivity. It must coordinate the thermal path with the die placement, interconnect architecture, assembly process, and reliability requirements.

The best electrical placement may not be the best thermal placement; the best thermal placement may complicate fiber routing or package test. This is why package architecture is a system trade-off, not an isolated layout decision.

Power delivery also a package decision

AI systems require large current with rapidly changing load demand. As package power rises, the distance between voltage regulation, decoupling, power planes, and compute dies becomes increasingly important.

So, the package may need:

• Improved vertical power delivery
• Backside or near-die power structures
• Integrated voltage regulation
• Lower-inductance current paths
• More distributed decoupling
• Coordinated signal and return-current design

Power delivery interacts with:

• Chiplet placement
• HBM placement
• Interposer routing
• Thermal density
• Mechanical structure
• Package height
• Available routing layers

Manufacturing and test platforms

A package can be electrically attractive and still be difficult to manufacture. A platform approach must connect architecture choices to process capability. Questions include:

• Can the required die-placement tolerance be achieved?
• Can the redistribution layers be fabricated at the required scale and yield?
• Can the bridge or interposer be assembled without unacceptable warpage?
• Can underfill penetrate the available stand-off?
• Can thermal stack be controlled within bond-line limits?
• Can optical interface survive assembly and thermal cycling?
• Can each die be tested before integration?
• Can the completed assembly be tested after integration?
• Can failed modules be repaired or replaced?
• Can failed modules be repaired or replaced?

The package architecture is not complete when the drawing is complete. It’s complete when the process can repeatedly produce the intended geometry and performance. Manufacturing does not merely build the package; it creates the physical structure through which the system must operate.

Next, as the number of integrated dies increases, test complexity grows rapidly. A platform must account for:

• Known-good-die requirements
• Pre-bond test
• Post-bond test
• Interposer and bridge continuity
• Memory test
• Optical loopback
• Thermal calibration
• Power-delivery validation
• Fault isolation
• Repair or redundancy strategies

The challenge is especially severe when dies from different suppliers are integrated into one product. A failure in one small component can affect the yield of the entire assembly. This creates a compound-yield problem.

The value of a platform is therefore not simply that it offers several package technologies. It should also provide coordinated design rules, assembly flows, test access, metrology, failure analysis, and reliability evidence across those technologies.

System architecture now begins with workload

The new design sequence should begin with the workload and move downward into physical realization. Here, the deterministic chain encompasses:

• Workload requirements
• System partitioning
• Compute and memory placement
• Electrical and optical boundaries
• Package architecture
• Power and thermal architecture
• Manufacturing and test strategy
• Verified system performance

This reverses the older assumption that the package is selected near the end. The package platform must be taken into consideration from the beginning because it defines which partitioning options are physically and economically possible. A system architect cannot decide where compute, memory, optics, and power should reside without understanding the package technologies available to connect and sustain them.

Platform is not product

There is one important caution. A large portfolio of packaging technologies does not automatically produce a successful AI system. The platform provides options, but the product must still select and coordinate them correctly.

Adding more technologies can also increase:

• Process interactions
• Supplier dependencies
• Yield risk
• Test complexity
• Thermal coupling
• Mechanical stress
• Qualification burden
• Cost

The winning package will not be the one that includes the greatest number of advanced technologies. It will be the one that uses each technology only where its benefit exceeds its integration burden.

A local bridge may be better than a full interposer in one system. A full interposer may be essential in another. Near-packaged optical (NPO) may provide the right optical boundary for one product and CPO may be justified for another.

Vertical stacking may reduce latency but worsen thermal density. Fan-out may reduce cost but impose different warpage and process constraints. Therefore, the architecture must be selected based on system evidence, not technology enthusiasm.

Advanced packaging is no longer a menu of isolated process choices. It’s becoming the architecture through which compute, memory, electrical interconnect, optics, power delivery, cooling, manufacturing, and test are assembled into one realizable system.

The future is not one universal package. It’s an integrated technology platform capable of placing:

• Silicon-class density where it’s necessary
• Broader redistribution where it’s sufficient
• Vertical stacking where proximity creates value
• Optics where electrical reach becomes limiting
• Cooling where heat is generated
• Test access where failure must be isolated

The package is no longer selected after the system is defined. It increasingly determines which system architecture can be realized, manufactured, qualified, and scaled. The winning platform will not be the one that stacks the most technologies. It will be the one that places each technology where its system benefit exceeds its realization burden.

The chip defines capability. The package platform defines the system.

Dr. Moh Kolbehdari is senior director of IC/packaging at Socionext US.

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The post AI silicon: Package becoming system architecture appeared first on EDN.

This proposed design eliminates traditional additional requirements for AGC, AC coupling, and post amplification circuitry.

This Design Idea presents a simple op-amp-based sine wave oscillator that directly generates a low-impedance bipolar output of approximately 20 Vpp at frequencies above 100 kHz. The circuit was developed to directly drive an AD633 in an on–off keying (OOK) digital transmission system.

Wow the engineering world with your unique design: Design Ideas Submission Guide

Many sinewave oscillators reported in the literature provide a unipolar output and require additional circuitry for automatic gain control (AGC), AC coupling, and post amplification to achieve the desired amplitude. The proposed circuit eliminates these requirements by directly generating a high-amplitude bipolar sinewave.

The circuit (Figure 1) consists of an LC tank connected in a feedback loop with an op-amp configured as an inverting amplifier with a gain set by the R3/R2 ratio. At the resonance frequency, fosc = 1/(2π√(L·Cs)), where Cs = C1 || C2, the LC network introduces 180° phase shift, while the inverting amplifier provides an additional 180°, resulting in a total loop phase shift of 360°, thus satisfying the Barkhausen phase condition.

Figure 1 This simple LC oscillator uses an op-amp and the intrinsic losses of the resonant tank to generate a stable low-distortion 20 Vpp sine wave without AGC.

The topology can be viewed as a simplified Colpitts oscillator in which the op-amp both sustains oscillation and compensates for the losses of the resonant network. A key practical advantage is that the oscillation amplitude is set by the op-amp closed-loop gain, primarily through the feedback resistor R3, allowing straightforward amplitude control without additional circuitry.

The prototype was implemented using the LT1357, a high-speed op-amp featuring high slew rate and wide gain-bandwidth product. In general, a wideband op-amp with sufficient slew rate and gain-bandwidth product is required, particularly as the oscillation frequency increases.

Resistor R1 is not critical in value and primarily serves to isolate the op-amp output from the LC tank, preventing degradation of the phase margin due to the reactive load. At resonance, assuming an ideal inductor, R1 is effectively in series with R2 and forms a voltage divider. Its value should therefore be kept small relative to R2 to limit attenuation of the LC network, but not so small as to excessively load the op-amp, resulting in a practical design trade-off.

At startup, the loop gain is greater than unity, allowing oscillation to build up from noise. As the amplitude increases, current in the LC tank also increases, leading to higher losses due to winding resistance and ferrite core dissipation. These losses introduce additional attenuation in the resonant network, progressively reducing the loop gain until it reaches unity.

At equilibrium, the energy provided by the op-amp exactly compensates for the tank losses, and the oscillation amplitude stabilizes. The op-amp remains in its linear region, and the resulting waveform is very close to an ideal sine wave, as confirmed by oscilloscope capture (Figure 2).

Figure 2 The waveform generated by the circuit is very close to an ideal sine wave.

The oscillation frequency remains essentially constant as the amplitude varies, indicating that inductance variation due to core nonlinearity is negligible. The circuit was built and tested experimentally (Figure 3).

Figure 3 The circuit was breadboarded, versus simply simulated, to more definitively validate its functionality.

The measured frequency is approximately 120 kHz, compared to a nominal value of about 124 kHz, with the difference mainly attributable to component tolerances, particularly in the ceramic capacitors and the inductor .

The value of R3 depends on the characteristics and quality factor of the inductor. In the prototype, the inductor was hand-wound on a ferrite toroid to obtain approximately 100 µH. When reproducing the circuit, R3 may require empirical adjustment depending on the specific inductor used.

This oscillator provides a simple and effective solution for generating low-distortion sine waves at medium–high frequencies, offering easy amplitude control via op-amp gain while eliminating the need for dedicated amplitude control circuitry and directly delivering a low-impedance bipolar output.

—Luca Bruno has a Master’s Degree in Electronic Engineering from Politecnico of Milano. He taught electronics and telecommunications for many years at ITI Hensemberger and has published numerous Design Ideas in EDN on analog and electronic circuit design.

Related Content

• Simplified Sine – Wave Oscillators
• Ultra-low distortion oscillator, part 1: how not to do it.
• Ultra-low distortion oscillator, part 2: the real deal

The post Op-amp LC oscillator uses tank losses for amplitude stabilization appeared first on EDN.

Materials, networking and laser technology firm Coherent Corp of Saxonburg, PA, USA has begun sampling its 300mm high-thermal-conductivity silicon carbide (SiC) substrates to leading AI semiconductor partners, advancing its scalable materials platform for the growing thermal management requirements of artificial intelligence (AI) and high-performance computing (HPC) systems...