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The planet is facing a crisis in energy demand versus supply, and data centers are at the center of this dilemma due to the increasing demand from new data-intensive applications. This article will explore the causes of data center inefficiency and speculate on methods to improve efficiency. It will also acknowledge the U.S. Department of Energy’s analysis on energy efficiency, which provides a basis for this work.

Energy demand and where it’s being used

The announcement that Three Mile Island nuclear reactor was being recommissioned to power an AI data center might have been shocking news to some, but it’s no secret in the industry that the exploding demand for energy is outpacing our ability to deliver power to data centers. For the first time, power efficiency is now a higher priority to data center architects than performance of the individual components.

Semiconductor Research Corp. modeled this increase in energy demand in the context of the planet’s projected energy generation capacity, which includes the assumption that more nuclear power plants will be deployed. Figure 1 shows a daunting projection, and the potential for the lines of supply and demand to intersect around the year 2055 has the electronics industry rethinking its choices in how data centers can be designed.

Figure 1 The worldwide energy consumption trends show that we will eventually consume more energy than we produce. Source: Stanford University

Sadasivan Shankar at Stanford University broke down the places where we are spending that energy. In addition to AI, another culprit in energy demand is cryptocurrency. When combined, AI and crypto are consuming over 1.5% of the planet’s energy already. Some projections estimate that their data consumption will increase to 3% by 2030 and 4.4% by 2035 (see Figure 2). Note the scaling for the Y-axis in Figure 2: Applications such as cryptocoin mining require 18 orders of magnitude more energy than the base instructions on which the computers operate.

Figure 2 The energy demands for AI and cryptocurrency are a magnitude greater than that of other operations. Source: The U.S. Department of Energy

With this in mind, it makes sense to determine the efficiency of a data center by measuring the work accomplished for each watt that is spent. Figure 3 breaks down the power consumption per operation. It’s critical to note that almost every operation in the top two-thirds of the table refers to moving data around, while the bottom third of the table represents data processing.

Figure 3 Data centers consume different amounts of power for different functions. Source: Wolley Inc.

The memory, storage, and communications hierarchy is commonly shown as a pyramid, with processor registers at the top, various levels of cache followed by DRAM, then storage and communications at the bottom. This article will use this simplistic model, as shown later in Figure 5. The pyramid’s biggest issue is that it does not highlight how each resource is on a separate bus. In addition, moving information from one resource to another typically involves multiple movements on many buses, each of which consumes power and generates heat.

Figure 4 shows an example in which an application is read from the disk though the CPU across one channel—for instance, a PCIe—to be written to the memory over another channel (for example, a DDR), only to be read back to the CPU one cache line at a time to execute the application and store the temporary results back to the memory.

Figure 4 Here is how data movement demands high power. Source: IEEE

The application may read content across a communications channel, such as PCIe to a wide area network, then crunch that data to be written back to the disk. Even in this simple example, it’s obvious that data processing is an exceptionally minor outcome and that data movement is dominant. The percentage of data operated upon rather than moved around is close to zero as to be unmeasurable.

Why focus on memory?

Memory utilization is a focus area because there is a high potential to make substantial improvements in energy efficiency. Memory consumes as much power as many CPUs, at about 22% of server power. The increasing number of tiers of memory creates both the best and worst of trends.

The good news is that more power-efficient memories are being added closer to the processor. The bad news is that these near-memory tiers have limited capacity and require additional larger capacity, higher power memories to keep filling the datasets into the local memory. The power consumption of each tier adds to the total power footprint.

High bandwidth memory (HBM), for example, offers an interface around 1.5 pJ/bit, which compares favorably to a double data rate memory module at 15pJ/bit (see Figure 5). Unfortunately, these memories still burn significant power—for instance, 75 W or 100 W per HBM stack—and they are co-located with the high-power processor on the same substrate. This makes cooling extremely challenging compared to DDR modules, which are around 15 W each but located farther from the processor in areas that may be air-cooled.

Figure 5 Memory and accompanying storage consume considerable amounts of energy. Source: Monolithic Power Systems

Efficiency by tier

Speculation can improve system performance tremendously, but speculation always implies waste as well—even processor registers have implied waste. A system variable with a 32-bit integer that never assumes a value outside the range 1 to 10 has an implied waste factor of 87.5%. Processor caches have very high hit rates of 95% and higher, so one could invert that number to imply a 5% waste. DRAM access efficiency drops the further the memory is from the processor, with direct attached DDR memory at 27% waste and CXL-attached DDR at over 40% waste.

These numbers may not sound bad until one considers the activity inside each DRAM that allows cache line hit rates. The majority of processors operate with a 64-byte cache line. Consider how 64 bytes map to the internal structure of a DRAM. Each DRAM has an internal page buffer of 1 kB, and DRAMs are typically combined into ranks for 10 DRAMs energized per access (see Figure 6).

Figure 6 DRAMs are typically combined into ranks for 10 DRAMs energized per access. Source: Monolithic Power Systems

To fulfill a single cache line, a DRAM module is “activated” to read 1 kB from each DRAM into its sense amplifiers, or 10 kB across the width of the module. 64 bytes are read and sent to the processor. DRAM activation is destructive—the cells of the memory core are wiped out by the activation—so the cells must be rewritten from the sense amplifiers back into the core. The math for a single random access is 20 kB moved for 64 bytes of work, or 99.7% waste.

This factor of 0.3% efficiency is only against that movement of a 64-byte cache line. If that DRAM tier is operating at a 60% hit rate, efficiency drops to 0.18%. If only 1 byte from that cache line was actually needed, the waste factor increases to 99.98%. As you can see in this simple example, data center efficiency is rapidly approaching zero.

Another form of speculation that improves system performance is execution and access speculation, where a processor may pre-load code on both sides of a branch condition in case the branch is taken. Many SSDs do the same, pre-loading pages that may be accessed. These forms of speculation have 100% waste if the branch is not taken or the access is never made.

Total cost of ownership (TCO)

With electricity access becoming a bottleneck for data center expansion, architects are finally acknowledging that total cost of ownership (TCO) is a primary factor driving system design. While processor vendors focus strictly on performance, their customers are forced to determine whether they can power these machines and cool them. By some estimates, cooling a data center is currently consuming 43% of the cost of operating a data center, which is equivalent to the 43% required to run the machines themselves.

This expenditure is driving architects to measure efficiency not only as petaFLOPS/second but also petaFLOPS/watt-hour.

Improving memory energy efficiency

Improving the accuracy of speculative accesses is an obvious key to taming memory subsystem power consumption. Similar to telling a doctor “It hurts when I do this,” system architects should ask the question, “Is this speculative access successful often enough to pay for the energy consumed?”

For example, if a CXL memory module is in a memory pool and shared by multiple processors, what is the hit rate on any particular bank of DRAM? Should a page be left open, delaying precharge in case of another hit on that row of memory or be closed, issuing the precharge immediately under the assumption it will not be accessed?

Non-uniform memory access (NUMA) has been in server architectures for years to allow tightly coupled processors to share memory resources as demand shifts. However, multiple hops for each memory access can more than triple the power consumed, whereas moving the task to a processor closer to the memory resource can significantly reduce power (see Figure 7). Computational storage is a variation of task relocation that has had some success, though this success is limited by standards for the tasks executed on the devices.

Figure 7 For a server DRAM module, moving the task to a processor closer to the memory resource can significantly reduce power. Source: Monolithic Power Systems

Similarly, placing data in the appropriate tier of memory can have a significant impact on energy consumption. Figure 8 shows the temperature of the data, where hot data is accessed often, and cold data is accessed less often.

Figure 8 Map data based on how often it’s accessed to determine its temperature (where “hotter” data is accessed more often). Source: Monolithic Power Systems

Persistent memory is a system option that can be exploited for data reliability. Persistent memory is either based on a memory technology that does not lose its contents if the power fails (for example, MRAM) or uses an energy source to maintain data integrity by saving DRAM contents in a non-volatile memory (NVM), such as a flash-on power failure. Persistent memory can also be thought of as a significant way to reduce system power by eliminating the need for “checkpointing,” or saving intermediate results (see Figure 9). In many systems, checkpointing is responsible for 7% to 8% of the system traffic and therefore power.

Figure 9 Persistent memory can reduce checkpointing. Source: Monolithic Power Systems

Hybrid memory modules that combine storage and direct access memory on the same module are available to minimize system traffic as well. For example, flash memory mounted as an SSD can be coupled with DRAM, which is directly accessed by a cache line at a time. The efficiency of hybrid modules comes from the statistic of the typical 4-kB block moved from SSD to system memory; only 100 bytes on average are used, which results in an efficiency of only 2.5%.

Software has a huge impact on efficiency

Hardware cannot fix every challenge; software plays a significant role in taming this beast, too. Zooming in on the power consumed by data type, orders of magnitude more power are used for complex and large data types such as floating point, whereas integer math consumes far less power (see Figure 10). This may be as simple as programmers considering the range of values needed by variables in their software. For example, “for (i=0; i<10; i++)” does not need for i to use a 32-bit counter value.

Figure 10 Software plays a significant role in energy consumption. Source: The U.S. Department of Energy

The choice of variable types is sometimes the result of using the wrong programming language for the task (see Figure 11). Not all programming languages allow much flexibility in choosing the data types for variables, and these impacts are magnified tremendously by the matrix math employed by languages such as Python, a common tool for AI applications. Python has another energy-consuming characteristic: the programmer source is compiled to bytecode and then interpreted by a virtual machine as opposed to C programming, which compiles to processor native codes.

Figure 11 Programming languages can be ranked based on their energy consumption. Source: Wireunwired Research

You can’t fix what you can’t measure

Measuring runtime power is a key to tuning efficiency. The voltage regulators for memory modules—such as the MPQ8894, MPQ8895, and MPQ8896—are power management integrated circuits (PMICs) with an integrated system management interface to I2C, I3C, or SidebandBus. This system management interface allows the host system to interrogate the PMIC while the system is running. The current used by each voltage rail can be read from the PMIC to calculate the total power for the memory module while running test and measurement programs, or even while customer applications are running.

Triggers may be configured into the PMICs, and these devices can keep logs of any conditions that exceed the expected maximums. The host system may respond to the triggers by reading the telemetry registers and then acting on those conditions, such as by throttling applications that exceed system-imposed limits.

Choosing the right PMIC is a power-saving measure. With improved 4% power regulation efficiency when compared to competing solutions, this results in a total data center power reduction of 2%. For a typical 300 megawatt-hour installation, this would reduce power by 6 MWh and CO2 emissions by roughly 4 metric tons per year.

The power balancing act

Data centers are projected to keep increasing power demands until they become physically or financially impossible to expand. So, the total cost of ownership has become a focus for all datacenter architects as they balance the needs for performance from their customers with the reality of providing those services in a cost-effective manner.

Data center efficiency, as measured by the data processed vs. data moved around, is embarrassingly low. However, there are several ways to adjust efficiency, from cache management parameters to speculation priorities. Resource and job allocation over fabrics such as NUMA and CXL enable new classes of optimization.

The careful selection of energy efficient components such as voltage regulators can play a significant role in reducing the energy use of a data center. Every percentage of efficiency improvement leads to major reductions in CO2 emissions, a leading cause of pollution. Voltage regulators, for instance, take a holistic view of the system solution, providing high efficiency coupled with methods for measuring and fine tuning the solution to achieve optimal power savings.

Software plays a huge role in efficiency as well, from the low-level allocation of data types to the choice of programming languages for each task. In addition, measuring system efficiency at runtime helps data center operators monitor the health of the system and give insight into ways to improve or limit power as needed. Next, telemetry information helps system software to understand where energy is being used.

Most importantly, TCO analysis requires a change in mindset from operations per second to operations per watt-hour, a major shift forced on the industry by skyrocketing power demand. The use of high efficiency voltage regulators helps reduce data center energy usage, which lowers the cost of providing data services.

Bill Gervasi is principal memory solutions architect at Monolithic Power Systems.

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The post Taming the beast: Memory efficiency in an AI/crypto world appeared first on EDN.

Opened up a clock so I can make it a tiny guitar amp. Was not expecting what looks like a ghost got…excited…all over this RadioShack clocks innards. submitted by /u/mrmeatypop [link] [comments]

submitted by /u/1Davide [link] [comments]

submitted by /u/1Davide [link] [comments]

Toshiba is sampling its TXZ+ Entry-Class M4H microcontroller group for small-scale system control of consumer and industrial equipment. Powered by a 120-MHz Arm Cortex-M4 core with an FPU, the devices deliver the real-time performance needed for applications ranging from home appliances to factory automation.

M4H MCUs operate from a 2.7-V to 5.5-V supply, supporting 5-V powered equipment. A built-in high-speed oscillator provides ±1% accuracy across a –40°C to +105°C temperature range, eliminating the need for an external oscillator. Integrated peripherals include a 12-bit ADC, timers, UART, SPI, I²C, and DMA. The devices also feature an advanced programmable motor driver for brushless DC motor control.

Engineering samples are available for evaluation, along with starter kits, sample software, CMSIS-compliant drivers, and support for major IDEs.

TXZ+ Entry-Class M4H product page 

Toshiba Electronic Devices & Storage

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Two 3.3-kV SiC power modules from Wolfspeed target high-voltage energy infrastructure, including AI data centers, renewable energy systems, and grid equipment. The HAB900C33LM4 half-bridge baseplate module supports applications above 800 A, while the IBB020A33GM4 full-bridge baseplate-less module is rated for 100 A. Both modules accommodate 2-kV and higher DC-link architectures, allowing designers to reduce power stages and use simpler 2-level topologies.

Part of the LM platform, the HAB900C33LM4 half-bridge module is intended for converters used in solar, grid-scale energy storage, and wind-power systems. Wolfspeed states that it delivers up to 42% lower switching losses than comparable SiC products and more than 90% lower switching losses than IGBTs under the same test conditions. A member of the WolfPACK family, the IBB020A33GM4 baseplate-less device is designed for modular converter architectures, including solid-state transformers and series-stacked or parallel systems.

Both power modules use Gen 4 SiC technology and advanced packaging techniques, including sintered die attach, to enhance durability and power-cycling performance. Wolfspeed says the modules also maintain switching performance over temperature, helping reduce the size of magnetics and EMI filters while increasing system power density.

Samples of the HAB900C33LM4 and IBB020A33GM4 in industry-standard packages are available through Wolfspeed’s direct sales representatives.

Wolfspeed

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AMD has introduced the Ryzen AI Halo developer platform alongside Ryzen AI Max PRO 400 Series processors to support next-generation agentic AI systems. Both platforms are designed to run AI workloads locally, reducing reliance on cloud infrastructure while supporting low-latency operation, real-time response, and large memory footprints. AMD says the platforms target AI-enabled PCs and workstation-class systems that can execute complex AI workflows, including autonomous agents, on a single machine.

The Ryzen AI Halo developer platform is powered by Ryzen AI Max+ 395 processors and provides up to 128 GB of unified system memory, allowing developers to run AI models with up to 200 billion parameters locally. Designed as a compact AI development system, it supports both Linux and Windows environments and works with frameworks including PyTorch, vLLM, llama.cpp, Ollama, ComfyUI, and LM Studio. AMD ROCm software optimization further supports local execution of large language models, diffusion models, and agent-based workflows.

Based on AMD’s Zen 5 architecture, Ryzen AI Max PRO 400 Series processors combine RDNA 3.5 graphics, an XDNA 2 NPU, up to 192 GB of system memory, and 160 GB of VRAM. The processors target commercial AI PCs, mobile workstations, and compact desktop systems handling AI, simulation, and visualization workloads.

Ryzen AI Halo systems will be available through Micro Center, with pre-orders starting in June 2026. AMD plans to expand the platform in the third quarter of 2026 with Ryzen AI Max PRO 400 Series processors.

Advanced Micro Devices 

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The MLX81119 RGB LED controller from Melexis integrates a 1-A DC/DC converter to reduce power dissipation in automotive lighting systems. The converter generates an optimized local LED supply voltage programmable from 2.5 V to 6 V.

Unlike external DC/DC converters, which add heat, components, and layout complexity, the MLX81119’s converter dynamically adjusts the LED supply voltage to match the active color mix and operating conditions. This helps minimize power losses and thermal stress. With lower power dissipation, reduced component count, and smaller space requirements, the MLX81119 is well-suited for space-constrained vehicle applications such as door panels, dashboards, and charge-port lighting.

The MLX81119 provides 18 low-side current sources configurable up to 60 mA with independent 16-bit PWM control. It supports up to six RGB LEDs per device for smooth color transitions and lighting animations. Built-in direct and indirect temperature sensing enables active compensation across all channels to maintain stable color points over the automotive temperature range.

Along with a 16-bit MCU and 32 KB of flash, the MLX81118 integrates a complete LIN system, including a transceiver and protocol handler compliant with LIN 2.x and SAE J2602. It also supports implementations up to ASIL B for functional safety-relevant interior and exterior lighting applications.

MLX81119 product page 

Melexis

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An automotive bipolar Hall-effect latch from Diodes, the AH3711Q provides high magnetic sensitivity with operate and release points of ±10 Gauss. It can be used for brushless DC motor control, rotational speed measurement, linear and incremental rotary encoders, and position sensing. Typical applications include tailgate opening and closing mechanisms, motorized sunroofs, and power windows.

The high sensitivity of the AH3711Q enables detection of weaker magnetic fields, allowing the use of smaller magnets to reduce system size and BOM cost. Increased magnetic margin also permits greater duty-cycle reduction, lowering power consumption and extending battery life.

Operating over a 3-V to 27-V range, the Hall-effect latch integrates a reverse-blocking diode and Zener clamp on the supply, while the output includes overcurrent limiting and a Zener clamp. A chopper-stabilized design minimizes switch-point drift across the full -40°C to +150°C temperature range. These features protect against 40-V load dumps, reverse polarity, and short circuits. High 8-kV HBM and 1-kV CDM ESD ratings further enhance robustness in harsh environments.

The AEC-Q100 qualified AH3711Q is priced at $0.20 in 2,000-piece quantities.

AH3711Q product page

Diodes Inc.

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Huawei’s new chip design and how it aims to bypass Moore’s Law amid a lack of access to the latest EUV lithography is now the talk of the tech town. At the heart of this semiconductor breakthrough is 3D stacking—which Huawei calls LogicFolding—alongside aggressive use of hybrid bonding technology. Huawei’s He Tingbo recently presented details of this 1.4 nm chip—to be released in 2031—at an industry event in Shanghai, China.

Read the full story at EDN’s sister publication, EE Times.

The post A closer look at Huawei’s chip design workaround without EUV appeared first on EDN.

DefTech Bharat successfully concluded its 2026 edition in Bengaluru, reaffirming its position as one of India’s emerging platforms for aerospace, defence, and space technology collaboration. Held from May 20–22, 2026, at the Karnataka Trade Promotion Organisation (KTPO), Whitefield, the exhibition and conference attracted strong participation from defence manufacturers, technology developers, government stakeholders, startups, research institutions, and international delegations.

According to the organisers, the exhibition featured over 200 exhibitors from India and more than 12 countries, showcasing advanced technologies and next-generation solutions across air, land, sea, cyber, and space domains. The event also saw participation from more than 15,000 business visitors, including procurement officials, defence personnel, OEMs, system integrators, engineers, and policymakers.

The co-located DEFTECH Conference brought together industry leaders, technology experts, and government representatives for strategic discussions on indigenous defence manufacturing, AI-enabled warfare systems, aerospace innovation, cybersecurity, advanced electronics, and C4ISR technologies. More than 20 conference sessions and technical seminars were organised during the three-day event, focusing on technology collaboration, innovation pathways, and future battlefield requirements.

A major highlight of DEFTECH Bharat 2026 was the extensive display of cutting-edge technologies including autonomous and unmanned systems, UAVs and counter-drone solutions, AI-driven surveillance platforms, defence electronics, rugged embedded systems, aerospace subsystems, secure communication technologies, radar and sensor systems, additive manufacturing, semiconductor solutions, cyber defence technologies, and advanced manufacturing equipment. Live demonstrations and interactive technology showcases generated strong interest among both domestic and international visitors.

The exhibition also served as a strong networking and business development platform, enabling direct interaction between OEMs, MSMEs, startups, R&D organisations, armed forces representatives, and global technology providers. Several exhibitors reported high-quality business enquiries and strategic partnership discussions during the event.

Building on the strong response to the 2026 edition, the organisers announced that the next edition of DEFTECH Bharat will be held from May 19–21, 2027, at the Bangalore International Exhibition Centre (BIEC), Bengaluru. The move to the larger BIEC venue comes in response to increasing exhibitor demand and rising visitor participation. The exhibition area for the 2027 edition is expected to expand significantly to accommodate a broader range of aerospace, defence, homeland security, and space technology exhibitors.

With India accelerating its focus on indigenous defence production and technology-led modernisation under the Atmanirbhar Bharat initiative, DEFTECH Bharat continues to evolve as an important industry platform connecting innovation, manufacturing, research, and strategic capability development for the future defence ecosystem.

The post DEFTECH Bharat 2026 Concludes Successfully, Sets Stage for Expanded 2027 Edition at BIEC appeared first on ELE Times.

Simple circuit ratios sensor capacitance to reference capacitor to measure micrometers.

It’s hard to imagine a simpler electromechanical sensor than the capacitance type, consisting of little more than two plates (or even just one if the sensed target is conductive) separated by a dielectric (e.g. air).  Sensor capacitance is approximately: C = 8.854pF S/d where S = area of the plates and d = their separation (both in meters).  C then becomes a sensitive readout of plate separation.

Wow the engineering world with your unique design: Design Ideas Submission Guide

Here’s a plausible example. With 38mm diameter circular plates and initial separation of 1mm, you get a nominal capacitance of C = 8.854pF * 0.0382 * pi / 4 / 0.001 = 10pF.  C would span 3.3pF at d = 3mm to 33pF at d = 0.3mm which, with a little math, can be converted into the distance between the plates.  But how to measure C?

For that, we’ll need an interface circuit.  The one in Figure 1 is a suitably simple match for the simplicity of the capacitive sensor itself, consisting of just 8 inexpensive off-the-shelf (OTS) parts.  Here’s how it works.

Figure 1 U1a and U1b cross-coupled Schmidt trigger timers form a ~1MHz RC multivibrator. For the example sensor dimensions and parts values, Output duty factor = x = Out / 5V = d/(d + 1mm). Therefore d = x/(1 – x)

U1a and U2a form an RC timer with a time constant equal to R1Csense while U1b and U2b do the same job for R2Cref.  Cross coupling them as shown in Figure 1 creates a square wave oscillator whose ~1MHz cycle on U1 pin 3 consists of dwelling at +V for Tref = 50ksec Cref = 500ns and at zero for Tsense = 50ksec Csense = 500ns / d where d, as earlier, is measured in mm. 

Thus, the Output duty factor “x” = Tref / (Tref + Tsense) = 500ns / (500ns + 500ns / d) = 1/(1 + 1/d) = d/(d + 1). Starting from x = d/(d + 1), a bit of rearranging yields x(d + 1) = d, then xd + x = d, x = d(1 – x), and finally d = x/(1 – x).  Figure 2 shows how this math performs when the Out signal is fed into a 12bit ADC.

Figure 2 This graph shows sensor performance when Out is connected to a 12bit ADC using +5V for its reference. The black curve (left axis) = plate separation (d) in millimeters, while the red curve (right axis) = ADC least significant bit (LSB) resolution in micrometers.  Note that the resolution is close to 0.1% (d/1000) over much of the range.

Details of circuit operation include the inherent matching and tracking of U1’s gates simply because they share the same chip, and of accurate duty factor digitization if the connected ADC uses +5V as its reference voltage.  Asterisked parts (R1, R2, and Cref) are precision types.  Stray wiring and layout capacitances should be scrupulously minimized.

If there’s a chance the sensor plates might come into contact and short out, then it’s a good idea to protect U2 with a series capacitor.  0.1uF (from the same bag as C1 and C2) will work well and be sufficiently larger than Csense such that its precision and stability (or lack of thereof) won’t matter.  I’d also put another one in series with Cref, although it’s not strictly necessary, just so things look more balanced.

If your application needs position sensing in two dimensions (e.g. an XY stage), the other halves of  U1 and U2 are ready and willing, which helps to keep things capaciously and suitably simple!

Stephen Woodward‘s relationship with EDN’s DI column goes back quite a long way. Over 200 submissions have been accepted since his first contribution back in 1974.  They have included best Design Idea of the year in 1974 and 2001.

Related Content

• Capacitor matchmaker
• CMOS flip-flop used “off label” implements precision capacitance sensor
• From gap to signal: Non-contact capacitive displacement sensors
• Simple circuit interfaces differential capacitance sensor
• The sensor parade at CES 2025

The post ~0.1% resolution capacitive position sensor appeared first on EDN.

Microchip Technology Inc of Chandler, AZ, USA has announced the availability of its new 3.3kV HV-D3 mSiC power modules, designed to simplify and accelerate the adoption of solid-state transformers (SSTs) in AI hyperscale data centers and other high-voltage power applications. The new modules integrate 3.3kV silicon carbide (SiC) mSiC MOSFETs and Schottky diodes in an industry-standard 62mm package, enabling efficient power delivery from the medium-voltage grid directly to the server rack...

New gallium nitride (GaN)-based power semiconductors from STMicroelectronics of Geneva, Switzerland are designed to improve efficiency and increase power density in high-voltage power supplies for high-demand applications that support electrification. The 700V PowerGaN devices in the STPOWER portfolio address challenges such as rising AI server power consumption and the need for higher-performance power conversion beyond the limits of conventional silicon technologies...

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ST announces Zephyr 4.4.0 is adding support for the STM32C5, STM32H5E/F, STM32U3C5, as well as the X-NUCLEO-IKS5A1 daughter board, the EVKITST87M01-1 evaluation kit, and the ST B-DSI-MB1314 touch-sensitive display, among many other things, such as sensors and modems (ST87M01). It’s a testament to the collaboration between ST and the Zephyr community. Over the years, ST prevail drivers, optimize performance, and supports new features. And while we do have partners who use Zephyr and benefit from these contributions, this also stems from our desire to work with open-source projects that help democratize real-time operating systems and lower the barrier to entry.

The ST software ecosystem, encompassing the STM32Cube suite and tools like MEMS Studio, provides engineers with low-level device access and accessible machine learning capabilities. Through utilities such as NanoEdge AI Studio, the company facilitates edge AI development and optimizes hardware accessibility for a broad user base. For more insights, visit the ST Blog.

STM32Cube Ecosystem and the other ST software that grant developers low-level access to devices, such as MEMS Studio, which makes machine learning on sensors even more approachable. For many, tools like STM32CubeProgrammer help make the hardware more accessible, while ST’s software packages for its microcontrollers, microprocessors, sensors, and more provide drivers, middleware, example code, and more. Recently, utilities like NanoEdge AI Studio help programmers and software engineers work on neural networks and optimize their AI applications at the edge, thanks to features like synthetic data generation.

The Zephyr project provides a necessary, agnostic system for organizations managing diverse hardware, offering a unified abstraction layer that enhances portability and interoperability for complex, multi-vendor projects. By utilizing this open-source platform, developers can establish a flexible foundation for building proprietary subsystems and avoid vendor-specific lock-in. You can read the full analysis at ST’s official website.

The importance of the collaboration between ST and Zephyr

ST contributes to the Zephyr project and supports its low-level APIs. Concretely, it means we work with Zephyr to support numerous peripherals and interfaces, including USB modules, LCD-TFT display controllers, networking interfaces, and much more. Since the beginning of the Zephyr project, ST engineers have contributed to the Zephyr codebase and the support community. In certain instances, we even help with critical technologies, such as low-power modes, recognizing that our contribution will benefit more than just the engineers using our products. Another aspect of ST’s work on the Zephyr project is the significant effort that involves reviewing community contributions to the STM32 codebase. It may include new board support, bug fixes, and even complete drivers pushed and maintained by external contributors. Over time, these contributions have been responsible for a significant part of the STM32’s current status.

New MCU Support

The STM32N6 Discovery Kit with a CMOS sensor running a person detection application. Zephyr 4.4.0 is a good example of dedication to the project. Similar to frequent updates to STM32CubeProgrammer bringing new STM32 MCU support, this new version of Zephyr adds support for the STM32C5, STM32H5E/F, the STM32U3C5, and the STM32WBA2X. In some instances, like the STM32C5, this version adds support for DMA, I2C, SPI, ADC, timers, and watchdog. Since we just launched the STM32C5, Zephyr 4.4.0 is an inaugural release for the new series. For other devices in an existing series, the MCU support builds on what is already in place, enabling developers to leverage new part numbers.

New Middleware Features

Beyond the device itself, ST also brings updates to its drivers or middleware. For instance, among many improvements, v4.4.0 brings performance enhancements on STM32, adds RTIO and optimizes DMA in SPI STM32 drivers, and adds a stream API for ADC STM32 drivers. We also added the ability to inject ADC channels to enable immediate execution, overriding the regular sequence. Similarly, Zephyr 4.4.0 adds a portable API to read the one-time programmable non-volatile memory on STM32 MCUs. Usually, that means an ADC sensor can now access calibration data. We are also starting to make our I3C interfaces available on our STM32MP2 MPU, and we have moved our USB default stack to a newer and more robust version.

 

 

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At PCIM Europe 2026 in Nuremberg, Infineon Technologies AG showcases its comprehensive semiconductor portfolio for future-proof power infrastructure, AI data centers, robotics, and electromobility. The company presents a broad range of power system solutions spanning silicon (Si), silicon carbide (SiC), and gallium nitride (GaN) semiconductors, with support of software, tools, and cybersecurity expertise.

Infineon’s PCIM 2026 demo highlights:

• Making power infrastructure future-proof: As renewable energy continues to scale, robust power infrastructure is essential to support energy-intensive applications like AI data centers and advance factories. At PCIM, Infineon demonstrates its semiconductor technologies for efficient battery storage systems, uninterruptible power supplies, Solid-State Transformers (SST), and Solid-State Circuit Breakers (SSCB). Highlights include a demo stack for SSTs, along with SSCB components based on CoolSiC JFET technology, enabling fault isolation within microseconds and delivering high robustness for future DC grids.
• Powering AI from grid to core: Rapidly rising AI computing workloads are driving a sharp increase in data center energy demand and accelerating the shift toward new power architectures such as HVDC sidecars and DC microgrids. At PCIM, Infineon presents a comprehensive portfolio of Si, SiC, and GaN supporting this transformation from grid connection to processor core. Exhibits include power semiconductors, drivers, microcontrollers, and sensors for the latest power supply units, as well as solutions for battery backup units, intermediate bus converters, voltage regulation, and intelligent protection devices.
• Shaping the future of electromobility: Infineon is advancing electromobility as the global market leader in automotive semiconductors. PCIM highlights the link of this area, including solutions for traction inverters, DC-DC converters, on-board chargers, and battery management systems. Visitors can explore the company’s “One Inverter, One Infineon” system solution to improve drivetrain efficiency while optimizing space and cost. Additional demos showcase CoolSiC and CoolGaN power switches, the new EasyPACK S and CIPOS Prime module solutions, XENSIV sensors, and AURIX TC4xx microcontrollers.
• Empowering robotics: Robots are rapidly evolving toward physical AI systems that can sense, think, and act. At PCIM, Infineon will showcase semiconductor solutions supporting this evolution across industrial and domestic robots, humanoids, and drones. Demos include high‑efficiency motor control and power management solutions based on CoolGaN power semiconductors, PSOC Control C3 microcontrollers, and XENSIV sensors, enabling compact designs, precise control, and robust operation in future robotic applications.
• EU Cyber Resilience Act: Infineon highlights its commitment to security. At PCIM, experts will address upcoming regulatory requirements of the EU Cyber Resilience Act, illustrating how secured‑by‑design semiconductor solutions enable customers to meet compliance demands while strengthening product differentiation.

Infineon also contributes to the PCIM conference program and the various expo stages. An overview of all presentations by Infineon experts is available at www.infineon/pcim.

 

 

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Microcontrollers (MCUs) come in a wide array of sizes for every application, from power optimized 8-bit to 32-bit high-performance MCUs running a dedicated operating system. The amount of MCUs needed to achieve a specific application is a difficult question with no correct answer. Going too high on the spectrum creates a more expensive design, while going too low makes it difficult or impossible to implement, wasting development time.

One way to help select a product is by seeing the reference designs and demos that someone else has already made. This provides a benchmark, or point of reference, that can be used to figure out if an application is feasible and cost-effective.

As an example of this, consider this IoT irrigation demo. The demo runs on the PIC32CM-GC00 family of MCUs, which sports an ARM Cortex-M23 CPU at 72 MHz. An M23 class CPU is an entry-level device architecturally, but the max frequency of 72 MHz is higher than most, which allows this part to perform tasks that are too intensive for entry-level, but don’t require the complexity of a mid-range or high-performance CPU.

In this demo, MQTT networking for smart connectivity, a 320 × 480 display over SPI with 16-bit color, and a capacitive touch keypad for user interactions were implemented on this device, as shown in Figure 1.

Figure 1 The unmounted demo includes MQTT networking, SPI-enabled display, and capacitive touch keypad. Source: Microchip

The reason this demo is achievable on an entry-level device is because of the high CPU clock speed, ample memory, and hardware peripherals. A similar device with a lower CPU clock would struggle in this application under the computational demands of rendering graphics and the latency of transferring data from the MCU to the display controller; or, in other words, the time it takes for a graphics packet to be sent to the display. These performance hits wouldn’t be a hard design failure; instead, it would be a “soft” failure from a usability perspective, which substantially impacts the user experience and perception.

Another performance benefit for embedded designs in graphics is the display controller. Unlike a larger television or computer monitor, the display controller can offload some of the more intensive tasks, like refreshing the display or storing the image buffer. Then, the embedded system only needs to send new pixel data for the changed sections in memory, saving a large number of resources.

Selective refreshing is simple in concept, but when there are a lot of assets moving around, it becomes much more challenging to implement in an efficient manner. Rather than reinventing the wheel, this application uses the Legato graphics library to handle the rendering, and Microchip Graphics Suite to design the graphic user interface (GUI).

Microchip Graphics Suite is a visual editor that allows designers to place objects and set up assets for use at runtime. The demo control screen in Microchip Graphics Suite is shown in Figure 2. When done designing, it generates code that invokes Legato underneath to handle the rendering operations.

Figure 2 Here is the view of the main screen in Microchip Graphics Suite. Source: Microchip

Moving on to the next major piece of this demo, networking. By itself, networking on its own is a herculean task. I’ve written and debugged bare-metal networking code before, and it’s a pain with hundreds of edge cases and little idiosyncrasies that break things. Besides the base complexity of implementing the protocols, the application code must format, send, receive, and parse data on a regular cadence.

Rather than go through that process again, networking and MQTT for this design were implemented by using an add-on board with a networking coprocessor that handles the network management for the main MCU. This greatly reduces the overhead on the main MCU, and it also reduces development costs. Rather than spending engineering time and (my) sanity troubleshooting a network stack implementation to figure out why the networking is not working as expected, the add-on is already tested and is known to be working.

And, to verify that this device would fit the demo needs, I verified it before writing code by using the out-of-the-box (OOB) sample for the module. The OOB program uses a PC to send commands to the add-on board and print the responses. These are saved to a log file which can be cross-referenced later to verify the sequence of operations needed to communicate with the board. Once I am confident that the module will work for this demo, development of a simple networking driver can begin. The RNWF02 add-on board (EV72E72A) uses AT commands to communicate.

Figure 3 The RNWF02 add-on board employs AT commands for communications. Source: Microchip

While the RNWF02 board handles most of the networking complexities, the networking driver on the PIC32CM-GC00 MCU still needs to keep track of the various states of connectivity the hardware is in. For instance, the Wi-Fi connection could be completed, but the device is waiting to receive a DHCP assignment. Without DHCP, an MQTT connection cannot be completed. Another possibility is that the networking is fully functional, but the MQTT broker did not accept the connection.

Finally, there is one more piece to the networking puzzle, the server side. This isn’t the direct responsibility of the main MCU, but it’s still needed to verify the module works as expected. For testing MQTT, I used the Eclipse Mosquitto plug-in broker running on a local network Home Assistant device.

Home Assistant has a few things going for it; it’s open source (Apache 2.0) and it creates a nice, visual remote GUI for the user to interact with, without going through the same process of designing and implementing an interactive user interface (Figure 4). In an end-product, a customized app would likely be used instead, but this provides a good proxy.

Figure 4 The remote GUI is built around the open-source Apache 2.0 tool. Source: Source: Microchip

The last noteworthy element to discuss in this demo is the capacitive touch keypad. This uses the MCU’s built-in peripheral touch controller (PTC) in conjunction with the touch library to determine which keys are being pressed on the keypad. Ordinarily, using the touch library is very simple, with a call to touch_process() in the main loop and checking if the measurements are done.

The touch library handles sample timings inside of its own functional calls. But in this case, since graphic rendering can take a lot of time (milliseconds), even when optimized, the touch library may not run as often as it wants, which leads to poor touch performance and, by proxy, a bad user experience.

To solve this problem, the application calls the touch library from periodic interrupt and queues but doesn’t process any touch events that occurred. Then, when the main loop is hit again, the events are dequeued and processed. This ensures the device maintains a responsive touch interface, even under heavy CPU load.

The takeaway from this application is that high-performance entry-level devices can fill a niche where an application needs to perform an intensive operation, like graphics or networking, while not being complex enough to justify a more sophisticated CPU.

At the end of the day, the point of an irrigation controller is to switch valves on and off on a timer, which is trivial for almost any MCU to accomplish. But the other value-added functions make this too intensive for entry-level performance parts, and that’s where MCUs like PIC32CM-GC00 fit in nicely.

Robert Perkel is a senior application engineer for Microchip Technology. In this role, he develops technical content such as App Notes, contributed articles, and videos. He is also responsible for analyzing use-cases of peripherals and the development of code examples and demonstrations.

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