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RF, microwave and power component distributor RFMW of San Jose, CA, USA (a Division of Exponential Technology Group Inc) has announced a global distribution agreement with South Korea-based RFHIC Corp...

A welcome career transition (and employer-responsibility expansion) begs for a hardware-plus-software evolution. Hold his beer; this engineer’s got this.

As some of you may have already noticed (assuming you even care about such things), my relationship with EDN recently (and happily) re-deepened. After being a full-time as a (senior, eventually) technical editor from 1997 to 2011, I returned beginning a year later, this time as a content contributor. And now I’ve added associate editor to my EDN repertoire.

“Wait,” you might be asking, “isn’t Aalyia Shaukat the associate editor at EDN?” You’re part-right; for nearly four years, she was. And for a couple of recent months, she (somehow) worked a double shift of jobs. But she’s now the full-time editor-in-chief at Power Electronics News, where she’s already rockin’ the house with her talent abundance. And I’m grateful to follow in her EDN associate editor footsteps, along with continuing my own frequent content-contribution cadence.

What’s this all got to do with “de-commingling (or if you prefer simpler vocabulary, “separating”) LAN equipment”? An excellent question. Now that I’m more intimately interacting with the EDN website and other publication (and publisher, and corporate owner) resources and services, I needed to set up a standalone computer so that nothing attacking my home office LAN could make its way to the corporate network and other facilities, too. That said, I remained heavily broadband-reliant. And I wasn’t up for setting up a completely separate Comcast service connection just for a single (albeit also a singularly important) computer. What to do?

Just call me “guest”

That last part was actually the easiest part to solve, it turns out. My home LAN, as mentioned before, is based on a multi-node mesh implemented using multiple Google Nest Wifi routers, with the primary one connected to the cable modem in the furnace room.

One nifty nuance of the Google Nest Wifi system (shared by not only other Google LAN equipment generations and gear from other suppliers, mind you) is that you can set up a distinct “guest” network that by default (which I’ve left unchanged in my case) is packet-isolated from the main LAN beyond their shared WAN connection.

The computer I’m dedicating to my EDN associate editor work is one you’ve seen before; a Microsoft Surface Pro 7+ (SP7+):

along with my longstanding tech-gear companion, a Kensington Dock:

mated as so:

LAN-migrating the SP7+ was easy-peasy. I disconnected the wired Ethernet cable from the back of the Kensington Dock, switched the computer from my main “RockyMountainBri” wireless network to “RockyMountainBri-guest”, and…that was it. And since my Brother multifunction laser printer was right next to the computer, I didn’t even need to bother migrating the wireless network that the MFC was connected to, foregoing printing support for the rest of my LAN in the process. I just ran a USB cable from the Kensington Dock to it, and…I was done. Perhaps obviously, by the way, any real guests are no longer able to use my “guest” wireless network.

Split personality

How do I handle the fact that, still acting as a contributing editor along with my other contributor colleagues, I’m now in effect submitting content to myself for subsequent publication, now wearing my associate editor hat? My contributing editor workflow is unchanged, actually. The only thing that’s different is the email address I now send my stuff to.

It used to be that I’d submit content from my personal email account to Aalyia’s corporate email address. Now, instead, it’s my corporate email address that the goods go to. I’m still using one of my other systems for initial writing—typically but not always a Mac. But, to maintain “firewall” purity between my newly transformed associate editor work system and the rest, I exclusively receive corporate email (and don’t send or receive personal email) on the SP7+.

Going loc(al, not o)

And what about backing up and archiving all this content I’m now receiving? Regular readers may remember that I’ve long been a fan, along with a frequent implementer and upgrader, of network-attached storage (NAS) for such (and other) purposes. That said, unless I wanted to dedicate a NAS solely to my “guest” network and connect it exclusively over slow Wi-Fi, I was going to need to transition to some other solution.

Therein lies the admittedly and intentionally somewhat obscure title of this piece. Instead of network-attached storage, I wanted something locally tethered. It had to be at least dual drive configuration, with RAID 1 support so I didn’t lose everything if a hard drive died. And ideally it’d run hardware RAID to avoid bogging down the computer. Yes, I know, if the RAID controller fails, you’re dead in the water, too, which is why I also wanted something that was reasonably popular. That way, I could, if necessary, find a replacement to slot the HDDs into without too much trouble.

I figured I’d start my search using the term “DAS”, for direct-attached storage. Interface technologies I’d used in the past—Firewire, Thunderbolt, and eSATA among them—weren’t relevant to this particular hardware configuration, so I settled on USB 3.x, as fast a flavor as possible, over USB-C. My (perhaps imperfect) search yielded exactly one result, QNAP’s TR-002, which ironically is primarily intended to capacity-expand the company’s NASs but can also find use as a standalone storage peripheral.

Tomato, tomahto

At this point, I reset my lingo-options list, expanding beyond “DAS” to also include “enclosure”. That change helped a lot from a results-options list length standpoint. What I’ve ended up with is the Mercury Elite Pro Dual from a company I’ve mentioned multiple times before, Other World Computing (aka, OWC) and bought open-box (with 1-year warranty) for $167.50.

It’s hardware RAID-based, supporting four different operating modes (albeit only one at a time):

• RAID 0 “Drive Striping”
• RAID 1 “Drive Mirroring” (the mode I’m using)
• Span, and
• Independent Drives

Its interface to the computer is 10 GBps USB 3.2; perhaps obviously, I’m direct-connecting it to the SP7+ versus going through the Kensington Dock intermediary. It also embeds a three-port hub, a particularly attractive proposition given the SP7+’s dearth of integrated connections. And here’s a rarity (as I’ve written about before); the hub’s USB-C and dual USB-A ports are all 10 Gbps peak bandwidth-capable, too.

Why, you might be asking, did I go with HDDs instead of SSDs? I’ll turn around and ask you a question in response to yours: have you priced SSDs lately? That said, HDD price tags are also skyrocketing lately, although they still hold a tangible edge over solid-state alternatives especially at higher capacities. And in my case, I thankfully was able to repurpose a couple of spare 3TB HDDs I’d already bought in the “before times” and still had sitting around unused (I’ll have more to say here in an already-planned upcoming follow-up post).

Software completes the magic trick

The last, but not the least, question: how to integrate it with my computer for mirroring and broader backup purposes? I planned on consistently using the SP7+’s upgraded-by-me 1 TByte SSD as primary storage of in-process and completed associated editor work, so one-way mirroring (versus two-way syncing) that portion of the SSD to external storage would be fine.

But I wanted that mirroring to be file-by-file, not lumped together into some unified-file or otherwise nonstandard format (Apple’s Time Machine, for example) that would make it difficult to resurrect the contents if primary storage in the computer failed, say, or if I needed to physically pass the external storage device to someone else. And, of course, I’m also looking for cheaper solutions, so open source or another free source would be best.

I found my solution in a two-part open-source program suite, developed and maintained by the FreeFileSync project and supporting Linux, MacOS and Windows platforms. FreeFileSync itself does the sync-and-mirror heavy lifting for both files and the folders containing them. And the closely related RealTimeSync monitors directories for content changes, which then kick off FreeFileSync (or any other operation more broadly).

This discussion thread was very helpful when I was setting up RealTimeSync and FreeFileSync on my system. And ever since then, it’s run like a charm; the only time it pauses is when it detects an abnormally large number of changes (multiple directories-and-files moved at once) and wants my OK before it proceeds.

Oh, and by the way…since I’ve got plenty of empty capacity available, at least at this early stage in my associate editor career, I’m also using the OWC Mercury Elite Pro Dual more broadly as a successor to the NAS for my ongoing computer-wide backup purposes using Windows’ built-in File History and (deprecated but still functional) Backup and Restore facilities that I’ve mentioned before. With that, I’ll wrap up for today. I hope what I’ve shared will be of help to at least some of you in similar configuration situations either now or in the future. As always, please share your thoughts on what’s worked (or not) for you in the comments!

—Brian Dipert is the associate editor, as well as a contributing editor, at EDN.

Related Content

• The whole-house LAN: Achilles-heel alternatives, tradeoffs, and plans
• The Microsoft Surface Pro 5 succession: Selections, motivations, and initial impressions
• Beefing up backup
• USB 3: How did it end up being so messy?

The post De-commingling (?) LAN equipment: It’s all in what you call it appeared first on EDN.

Epiwafer and substrate maker IQE plc of Cardiff, Wales, UK has completed its fundraising, yielding total subscription proceeds of £81m...

Infineon Technologies AG expands its CoolGaN BDS 40 V G3 bidirectional switch (BDS) family with two new devices, the IGK048B041S and IGK120B041S. The new additions reduce PCB footprint by 82 percent and cut component count in half. For engineers designing within the strict spatial constraints of modern smartphones, notebooks, and wearables, this is a significant and quantifiable step forward. Targeting compact consumer devices, the new devices give power system designers greater flexibility to optimize efficiency and streamline designs without sacrificing performance.

“As consumer devices continue to shrink while power demands grow, engineers face increasing pressure to deliver more from less. The new CoolGaN BDS devices directly address this challenge,” said Johannes Schoiswohl, GaN Business Line Head at Infineon. “Each device integrates the function of two back-to-back silicon MOSFETs into a single component, reducing component count by half and simplifying PCB layouts. Design teams can leverage existing driver layout, avoiding costly redesigns and accelerating time to market. The result is a leaner and more cost-effective power path.”

The BDS, like other GaN devices, is compatible with 5 V gate drive. Offered in WLCSP chip-scale packages measuring 2.1 x 2.1 mm² and 1.7 x 1.2 mm², the IGK048B041S and IGK120B041S are engineered for the tight spatial constraints of smartphones, notebooks, and wearables. The larger GaN device achieves 4.2 mΩ RDD(on) while the smaller device delivers 9 mΩ RDD(on). The CoolGaN BDS devices further distinguish themselves through superior switching and leakage performance. Gate charge is up to approximately 40 percent lower than that of comparable competing devices. Lower gate charge translates directly to faster switching transitions, reduced switching losses, and better system efficiency in fast-charging applications. Additionally, Drain-Drain Leakage current is more than 85 percent lower than competing solutions, underscoring the inherent leakage advantages of GaN technology. Together, these characteristics reduce thermal rise, supporting long-term reliability and helping manufacturers meet increasingly stringent safety requirements.

Unlike silicon MOSFETs, which rely on a body diode that can allow unintended current flow, the CoolGaN BDS devices allow bidirectional voltage and current blocking. This true bidirectional blocking capability is essential for applications such as USB overvoltage protection in smartphones and portable devices, where preventing unwanted reverse current is critical to protecting sensitive downstream components. The devices are equally well-suited to load switching and power multiplexing functions in multi-rail power architectures, where precise control of current direction across multiple supply rails is required.

With the addition of these two devices, the Infineon CoolGaN BDS 40 V G3 family now comprises three devices: the IGK048B041S, IGK120B041S, and the IGK080B041S, addressing the full spectrum of mobile power switching requirements from compact wearables to high-performance notebooks.

Infineon has a strong portfolio with more than 40 new GaN product announcements in the last year and is a preferred partner for customers seeking high-quality GaN solutions. The company is on track with its implementation of scalable GaN manufacturing on 300-millimeter wafers, with first samples already being shipped to customers. 300 mm GaN enables higher production capacity and faster delivery of high-quality GaN products, which further strengthens Infineon’s position in the GaN market.

The post Infineon CoolGaN BDS Chips Splash Portable Power Footprint by 82% appeared first on ELE Times.

MathWorks, the leading developer of mathematical computing software, today announces new Hardware Support Packages that directly connect Model-Based Design and simulation to execution on Renesas‘ RH850/U2A microcontroller for automotive applications and the RA6T2 microcontroller for industrial controls. The new MATLAB and Simulink integrations enable engineering teams to move from simulation to running code on hardware with automatic build, flashing, and on-target execution while also accelerating development cycles, eliminating many manual integration steps.

“Our customers expect a straightforward path from simulation model to microcontroller, and the new integration with MATLAB and Simulink delivers exactly that,” said Brad Rex, Senior Director of System Solution Team, UX (User Experience) Group at Renesas. “By working with MathWorks, we’ve removed the need to assemble toolchains and device drivers by hand so teams can simulate and validate designs earlier, iterate faster, and reduce integration effort across ECU and industrial-control projects.“

The new support packages provide engineering teams with a consistent Model-Based Design workflow across both automotive and industrial programs, reducing integration effort and accelerating deployment. Renesas’ RA microcontroller platform focuses on industrial and robotics applications that require flexible connectivity, real-time responsiveness, and scalable embedded control. The integration with the RA family enables rapid prototyping of servo and variable-speed drive applications, with one-click deployment that streamlines hardware bring-up and on-bench validation for motion profiles and closed-loop tuning.

The automotive electronic control units widely uses he Renesas RH850/U2A microcontroller, which provides the deterministic performance and safety-critical features for EV motor control, latest driver-assistance systems (ADAS), and body electronics. Automotive engineers developing traction motor control for electric vehicles can deploy field-oriented control and regenerative braking algorithms directly from Simulink to RH850/U2A-based ECUs. This shortens the time from concept to vehicle-level testing, supports smoother torque delivery during rapid transients, and speeds calibration across drive cycles—without writing initialization code or custom build scripts.

“Our collaboration with Renesas strengthens the level of interoperability that engineers expect when using MATLAB and Simulink,” said Anuja Apte, India Product Marketing Manager, MathWorks. “By providing a direct path from Simulink models to optimized microcontroller deployment, we help engineering teams move from design to hardware more efficiently while staying integrated with the broader toolchains they rely on. This approach reflects the MathWorks Connections program, which brings partners and customers together to accelerate innovation and reduce time to market within a widely adopted engineering and scientific platform.”

For more information on the new hardware support packages in MATLAB and Simulink, visit the Renesas RH850 hardware support page and the Renesas RA hardware support page on the MathWorks website.

The post MathWorks Launches New Renesas Hardware Support Packages to Enable Rapid Prototyping for Automotive and Industrial Engineers appeared first on ELE Times.

The planet is facing a crisis in energy demand versus supply, and data centers are at the center of this dilemma due to the increasing demand from new data-intensive applications. This article will explore the causes of data center inefficiency and speculate on methods to improve efficiency. It will also acknowledge the U.S. Department of Energy’s analysis on energy efficiency, which provides a basis for this work.

Energy demand and where it’s being used

The announcement that Three Mile Island nuclear reactor was being recommissioned to power an AI data center might have been shocking news to some, but it’s no secret in the industry that the exploding demand for energy is outpacing our ability to deliver power to data centers. For the first time, power efficiency is now a higher priority to data center architects than performance of the individual components.

Semiconductor Research Corp. modeled this increase in energy demand in the context of the planet’s projected energy generation capacity, which includes the assumption that more nuclear power plants will be deployed. Figure 1 shows a daunting projection, and the potential for the lines of supply and demand to intersect around the year 2055 has the electronics industry rethinking its choices in how data centers can be designed.

Figure 1 The worldwide energy consumption trends show that we will eventually consume more energy than we produce. Source: Stanford University

Sadasivan Shankar at Stanford University broke down the places where we are spending that energy. In addition to AI, another culprit in energy demand is cryptocurrency. When combined, AI and crypto are consuming over 1.5% of the planet’s energy already. Some projections estimate that their data consumption will increase to 3% by 2030 and 4.4% by 2035 (see Figure 2). Note the scaling for the Y-axis in Figure 2: Applications such as cryptocoin mining require 18 orders of magnitude more energy than the base instructions on which the computers operate.

Figure 2 The energy demands for AI and cryptocurrency are a magnitude greater than that of other operations. Source: The U.S. Department of Energy

With this in mind, it makes sense to determine the efficiency of a data center by measuring the work accomplished for each watt that is spent. Figure 3 breaks down the power consumption per operation. It’s critical to note that almost every operation in the top two-thirds of the table refers to moving data around, while the bottom third of the table represents data processing.

Figure 3 Data centers consume different amounts of power for different functions. Source: Wolley Inc.

The memory, storage, and communications hierarchy is commonly shown as a pyramid, with processor registers at the top, various levels of cache followed by DRAM, then storage and communications at the bottom. This article will use this simplistic model, as shown later in Figure 5. The pyramid’s biggest issue is that it does not highlight how each resource is on a separate bus. In addition, moving information from one resource to another typically involves multiple movements on many buses, each of which consumes power and generates heat.

Figure 4 shows an example in which an application is read from the disk though the CPU across one channel—for instance, a PCIe—to be written to the memory over another channel (for example, a DDR), only to be read back to the CPU one cache line at a time to execute the application and store the temporary results back to the memory.

Figure 4 Here is how data movement demands high power. Source: IEEE

The application may read content across a communications channel, such as PCIe to a wide area network, then crunch that data to be written back to the disk. Even in this simple example, it’s obvious that data processing is an exceptionally minor outcome and that data movement is dominant. The percentage of data operated upon rather than moved around is close to zero as to be unmeasurable.

Why focus on memory?

Memory utilization is a focus area because there is a high potential to make substantial improvements in energy efficiency. Memory consumes as much power as many CPUs, at about 22% of server power. The increasing number of tiers of memory creates both the best and worst of trends.

The good news is that more power-efficient memories are being added closer to the processor. The bad news is that these near-memory tiers have limited capacity and require additional larger capacity, higher power memories to keep filling the datasets into the local memory. The power consumption of each tier adds to the total power footprint.

High bandwidth memory (HBM), for example, offers an interface around 1.5 pJ/bit, which compares favorably to a double data rate memory module at 15pJ/bit (see Figure 5). Unfortunately, these memories still burn significant power—for instance, 75 W or 100 W per HBM stack—and they are co-located with the high-power processor on the same substrate. This makes cooling extremely challenging compared to DDR modules, which are around 15 W each but located farther from the processor in areas that may be air-cooled.

Figure 5 Memory and accompanying storage consume considerable amounts of energy. Source: Monolithic Power Systems

Efficiency by tier

Speculation can improve system performance tremendously, but speculation always implies waste as well—even processor registers have implied waste. A system variable with a 32-bit integer that never assumes a value outside the range 1 to 10 has an implied waste factor of 87.5%. Processor caches have very high hit rates of 95% and higher, so one could invert that number to imply a 5% waste. DRAM access efficiency drops the further the memory is from the processor, with direct attached DDR memory at 27% waste and CXL-attached DDR at over 40% waste.

These numbers may not sound bad until one considers the activity inside each DRAM that allows cache line hit rates. The majority of processors operate with a 64-byte cache line. Consider how 64 bytes map to the internal structure of a DRAM. Each DRAM has an internal page buffer of 1 kB, and DRAMs are typically combined into ranks for 10 DRAMs energized per access (see Figure 6).

Figure 6 DRAMs are typically combined into ranks for 10 DRAMs energized per access. Source: Monolithic Power Systems

To fulfill a single cache line, a DRAM module is “activated” to read 1 kB from each DRAM into its sense amplifiers, or 10 kB across the width of the module. 64 bytes are read and sent to the processor. DRAM activation is destructive—the cells of the memory core are wiped out by the activation—so the cells must be rewritten from the sense amplifiers back into the core. The math for a single random access is 20 kB moved for 64 bytes of work, or 99.7% waste.

This factor of 0.3% efficiency is only against that movement of a 64-byte cache line. If that DRAM tier is operating at a 60% hit rate, efficiency drops to 0.18%. If only 1 byte from that cache line was actually needed, the waste factor increases to 99.98%. As you can see in this simple example, data center efficiency is rapidly approaching zero.

Another form of speculation that improves system performance is execution and access speculation, where a processor may pre-load code on both sides of a branch condition in case the branch is taken. Many SSDs do the same, pre-loading pages that may be accessed. These forms of speculation have 100% waste if the branch is not taken or the access is never made.

Total cost of ownership (TCO)

With electricity access becoming a bottleneck for data center expansion, architects are finally acknowledging that total cost of ownership (TCO) is a primary factor driving system design. While processor vendors focus strictly on performance, their customers are forced to determine whether they can power these machines and cool them. By some estimates, cooling a data center is currently consuming 43% of the cost of operating a data center, which is equivalent to the 43% required to run the machines themselves.

This expenditure is driving architects to measure efficiency not only as petaFLOPS/second but also petaFLOPS/watt-hour.

Improving memory energy efficiency

Improving the accuracy of speculative accesses is an obvious key to taming memory subsystem power consumption. Similar to telling a doctor “It hurts when I do this,” system architects should ask the question, “Is this speculative access successful often enough to pay for the energy consumed?”

For example, if a CXL memory module is in a memory pool and shared by multiple processors, what is the hit rate on any particular bank of DRAM? Should a page be left open, delaying precharge in case of another hit on that row of memory or be closed, issuing the precharge immediately under the assumption it will not be accessed?

Non-uniform memory access (NUMA) has been in server architectures for years to allow tightly coupled processors to share memory resources as demand shifts. However, multiple hops for each memory access can more than triple the power consumed, whereas moving the task to a processor closer to the memory resource can significantly reduce power (see Figure 7). Computational storage is a variation of task relocation that has had some success, though this success is limited by standards for the tasks executed on the devices.

Figure 7 For a server DRAM module, moving the task to a processor closer to the memory resource can significantly reduce power. Source: Monolithic Power Systems

Similarly, placing data in the appropriate tier of memory can have a significant impact on energy consumption. Figure 8 shows the temperature of the data, where hot data is accessed often, and cold data is accessed less often.

Figure 8 Map data based on how often it’s accessed to determine its temperature (where “hotter” data is accessed more often). Source: Monolithic Power Systems

Persistent memory is a system option that can be exploited for data reliability. Persistent memory is either based on a memory technology that does not lose its contents if the power fails (for example, MRAM) or uses an energy source to maintain data integrity by saving DRAM contents in a non-volatile memory (NVM), such as a flash-on power failure. Persistent memory can also be thought of as a significant way to reduce system power by eliminating the need for “checkpointing,” or saving intermediate results (see Figure 9). In many systems, checkpointing is responsible for 7% to 8% of the system traffic and therefore power.

Figure 9 Persistent memory can reduce checkpointing. Source: Monolithic Power Systems

Hybrid memory modules that combine storage and direct access memory on the same module are available to minimize system traffic as well. For example, flash memory mounted as an SSD can be coupled with DRAM, which is directly accessed by a cache line at a time. The efficiency of hybrid modules comes from the statistic of the typical 4-kB block moved from SSD to system memory; only 100 bytes on average are used, which results in an efficiency of only 2.5%.

Software has a huge impact on efficiency

Hardware cannot fix every challenge; software plays a significant role in taming this beast, too. Zooming in on the power consumed by data type, orders of magnitude more power are used for complex and large data types such as floating point, whereas integer math consumes far less power (see Figure 10). This may be as simple as programmers considering the range of values needed by variables in their software. For example, “for (i=0; i<10; i++)” does not need for i to use a 32-bit counter value.

Figure 10 Software plays a significant role in energy consumption. Source: The U.S. Department of Energy

The choice of variable types is sometimes the result of using the wrong programming language for the task (see Figure 11). Not all programming languages allow much flexibility in choosing the data types for variables, and these impacts are magnified tremendously by the matrix math employed by languages such as Python, a common tool for AI applications. Python has another energy-consuming characteristic: the programmer source is compiled to bytecode and then interpreted by a virtual machine as opposed to C programming, which compiles to processor native codes.

Figure 11 Programming languages can be ranked based on their energy consumption. Source: Wireunwired Research

You can’t fix what you can’t measure

Measuring runtime power is a key to tuning efficiency. The voltage regulators for memory modules—such as the MPQ8894, MPQ8895, and MPQ8896—are power management integrated circuits (PMICs) with an integrated system management interface to I2C, I3C, or SidebandBus. This system management interface allows the host system to interrogate the PMIC while the system is running. The current used by each voltage rail can be read from the PMIC to calculate the total power for the memory module while running test and measurement programs, or even while customer applications are running.

Triggers may be configured into the PMICs, and these devices can keep logs of any conditions that exceed the expected maximums. The host system may respond to the triggers by reading the telemetry registers and then acting on those conditions, such as by throttling applications that exceed system-imposed limits.

Choosing the right PMIC is a power-saving measure. With improved 4% power regulation efficiency when compared to competing solutions, this results in a total data center power reduction of 2%. For a typical 300 megawatt-hour installation, this would reduce power by 6 MWh and CO2 emissions by roughly 4 metric tons per year.

The power balancing act

Data centers are projected to keep increasing power demands until they become physically or financially impossible to expand. So, the total cost of ownership has become a focus for all datacenter architects as they balance the needs for performance from their customers with the reality of providing those services in a cost-effective manner.

Data center efficiency, as measured by the data processed vs. data moved around, is embarrassingly low. However, there are several ways to adjust efficiency, from cache management parameters to speculation priorities. Resource and job allocation over fabrics such as NUMA and CXL enable new classes of optimization.

The careful selection of energy efficient components such as voltage regulators can play a significant role in reducing the energy use of a data center. Every percentage of efficiency improvement leads to major reductions in CO2 emissions, a leading cause of pollution. Voltage regulators, for instance, take a holistic view of the system solution, providing high efficiency coupled with methods for measuring and fine tuning the solution to achieve optimal power savings.

Software plays a huge role in efficiency as well, from the low-level allocation of data types to the choice of programming languages for each task. In addition, measuring system efficiency at runtime helps data center operators monitor the health of the system and give insight into ways to improve or limit power as needed. Next, telemetry information helps system software to understand where energy is being used.

Most importantly, TCO analysis requires a change in mindset from operations per second to operations per watt-hour, a major shift forced on the industry by skyrocketing power demand. The use of high efficiency voltage regulators helps reduce data center energy usage, which lowers the cost of providing data services.

Bill Gervasi is principal memory solutions architect at Monolithic Power Systems.

Related Content

• Get a grip on your data center power efficiency
• Why Data Centers Must Become System‑Aware
• Space-Station Tech Pivots to Cool AI Data Centers
• Data Centers in Space: A Brilliant Idea or Delusional?
• Data center power meets rising energy demands amid AI boom

The post Taming the beast: Memory efficiency in an AI/crypto world appeared first on EDN.

Opened up a clock so I can make it a tiny guitar amp. Was not expecting what looks like a ghost got…excited…all over this RadioShack clocks innards. submitted by /u/mrmeatypop [link] [comments]

submitted by /u/1Davide [link] [comments]

submitted by /u/1Davide [link] [comments]

Toshiba is sampling its TXZ+ Entry-Class M4H microcontroller group for small-scale system control of consumer and industrial equipment. Powered by a 120-MHz Arm Cortex-M4 core with an FPU, the devices deliver the real-time performance needed for applications ranging from home appliances to factory automation.

M4H MCUs operate from a 2.7-V to 5.5-V supply, supporting 5-V powered equipment. A built-in high-speed oscillator provides ±1% accuracy across a –40°C to +105°C temperature range, eliminating the need for an external oscillator. Integrated peripherals include a 12-bit ADC, timers, UART, SPI, I²C, and DMA. The devices also feature an advanced programmable motor driver for brushless DC motor control.

Engineering samples are available for evaluation, along with starter kits, sample software, CMSIS-compliant drivers, and support for major IDEs.

TXZ+ Entry-Class M4H product page 

Toshiba Electronic Devices & Storage

The post Entry-level MCUs ease system control appeared first on EDN.

Two 3.3-kV SiC power modules from Wolfspeed target high-voltage energy infrastructure, including AI data centers, renewable energy systems, and grid equipment. The HAB900C33LM4 half-bridge baseplate module supports applications above 800 A, while the IBB020A33GM4 full-bridge baseplate-less module is rated for 100 A. Both modules accommodate 2-kV and higher DC-link architectures, allowing designers to reduce power stages and use simpler 2-level topologies.

Part of the LM platform, the HAB900C33LM4 half-bridge module is intended for converters used in solar, grid-scale energy storage, and wind-power systems. Wolfspeed states that it delivers up to 42% lower switching losses than comparable SiC products and more than 90% lower switching losses than IGBTs under the same test conditions. A member of the WolfPACK family, the IBB020A33GM4 baseplate-less device is designed for modular converter architectures, including solid-state transformers and series-stacked or parallel systems.

Both power modules use Gen 4 SiC technology and advanced packaging techniques, including sintered die attach, to enhance durability and power-cycling performance. Wolfspeed says the modules also maintain switching performance over temperature, helping reduce the size of magnetics and EMI filters while increasing system power density.

Samples of the HAB900C33LM4 and IBB020A33GM4 in industry-standard packages are available through Wolfspeed’s direct sales representatives.

Wolfspeed

The post SiC modules simplify high-voltage topologies appeared first on EDN.

AMD has introduced the Ryzen AI Halo developer platform alongside Ryzen AI Max PRO 400 Series processors to support next-generation agentic AI systems. Both platforms are designed to run AI workloads locally, reducing reliance on cloud infrastructure while supporting low-latency operation, real-time response, and large memory footprints. AMD says the platforms target AI-enabled PCs and workstation-class systems that can execute complex AI workflows, including autonomous agents, on a single machine.

The Ryzen AI Halo developer platform is powered by Ryzen AI Max+ 395 processors and provides up to 128 GB of unified system memory, allowing developers to run AI models with up to 200 billion parameters locally. Designed as a compact AI development system, it supports both Linux and Windows environments and works with frameworks including PyTorch, vLLM, llama.cpp, Ollama, ComfyUI, and LM Studio. AMD ROCm software optimization further supports local execution of large language models, diffusion models, and agent-based workflows.

Based on AMD’s Zen 5 architecture, Ryzen AI Max PRO 400 Series processors combine RDNA 3.5 graphics, an XDNA 2 NPU, up to 192 GB of system memory, and 160 GB of VRAM. The processors target commercial AI PCs, mobile workstations, and compact desktop systems handling AI, simulation, and visualization workloads.

Ryzen AI Halo systems will be available through Micro Center, with pre-orders starting in June 2026. AMD plans to expand the platform in the third quarter of 2026 with Ryzen AI Max PRO 400 Series processors.

Advanced Micro Devices 

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The MLX81119 RGB LED controller from Melexis integrates a 1-A DC/DC converter to reduce power dissipation in automotive lighting systems. The converter generates an optimized local LED supply voltage programmable from 2.5 V to 6 V.

Unlike external DC/DC converters, which add heat, components, and layout complexity, the MLX81119’s converter dynamically adjusts the LED supply voltage to match the active color mix and operating conditions. This helps minimize power losses and thermal stress. With lower power dissipation, reduced component count, and smaller space requirements, the MLX81119 is well-suited for space-constrained vehicle applications such as door panels, dashboards, and charge-port lighting.

The MLX81119 provides 18 low-side current sources configurable up to 60 mA with independent 16-bit PWM control. It supports up to six RGB LEDs per device for smooth color transitions and lighting animations. Built-in direct and indirect temperature sensing enables active compensation across all channels to maintain stable color points over the automotive temperature range.

Along with a 16-bit MCU and 32 KB of flash, the MLX81118 integrates a complete LIN system, including a transceiver and protocol handler compliant with LIN 2.x and SAE J2602. It also supports implementations up to ASIL B for functional safety-relevant interior and exterior lighting applications.

MLX81119 product page 

Melexis

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An automotive bipolar Hall-effect latch from Diodes, the AH3711Q provides high magnetic sensitivity with operate and release points of ±10 Gauss. It can be used for brushless DC motor control, rotational speed measurement, linear and incremental rotary encoders, and position sensing. Typical applications include tailgate opening and closing mechanisms, motorized sunroofs, and power windows.

The high sensitivity of the AH3711Q enables detection of weaker magnetic fields, allowing the use of smaller magnets to reduce system size and BOM cost. Increased magnetic margin also permits greater duty-cycle reduction, lowering power consumption and extending battery life.

Operating over a 3-V to 27-V range, the Hall-effect latch integrates a reverse-blocking diode and Zener clamp on the supply, while the output includes overcurrent limiting and a Zener clamp. A chopper-stabilized design minimizes switch-point drift across the full -40°C to +150°C temperature range. These features protect against 40-V load dumps, reverse polarity, and short circuits. High 8-kV HBM and 1-kV CDM ESD ratings further enhance robustness in harsh environments.

The AEC-Q100 qualified AH3711Q is priced at $0.20 in 2,000-piece quantities.

AH3711Q product page

Diodes Inc.

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Huawei’s new chip design and how it aims to bypass Moore’s Law amid a lack of access to the latest EUV lithography is now the talk of the tech town. At the heart of this semiconductor breakthrough is 3D stacking—which Huawei calls LogicFolding—alongside aggressive use of hybrid bonding technology. Huawei’s He Tingbo recently presented details of this 1.4 nm chip—to be released in 2031—at an industry event in Shanghai, China.

Read the full story at EDN’s sister publication, EE Times.

The post A closer look at Huawei’s chip design workaround without EUV appeared first on EDN.

DefTech Bharat successfully concluded its 2026 edition in Bengaluru, reaffirming its position as one of India’s emerging platforms for aerospace, defence, and space technology collaboration. Held from May 20–22, 2026, at the Karnataka Trade Promotion Organisation (KTPO), Whitefield, the exhibition and conference attracted strong participation from defence manufacturers, technology developers, government stakeholders, startups, research institutions, and international delegations.

According to the organisers, the exhibition featured over 200 exhibitors from India and more than 12 countries, showcasing advanced technologies and next-generation solutions across air, land, sea, cyber, and space domains. The event also saw participation from more than 15,000 business visitors, including procurement officials, defence personnel, OEMs, system integrators, engineers, and policymakers.

The co-located DEFTECH Conference brought together industry leaders, technology experts, and government representatives for strategic discussions on indigenous defence manufacturing, AI-enabled warfare systems, aerospace innovation, cybersecurity, advanced electronics, and C4ISR technologies. More than 20 conference sessions and technical seminars were organised during the three-day event, focusing on technology collaboration, innovation pathways, and future battlefield requirements.

A major highlight of DEFTECH Bharat 2026 was the extensive display of cutting-edge technologies including autonomous and unmanned systems, UAVs and counter-drone solutions, AI-driven surveillance platforms, defence electronics, rugged embedded systems, aerospace subsystems, secure communication technologies, radar and sensor systems, additive manufacturing, semiconductor solutions, cyber defence technologies, and advanced manufacturing equipment. Live demonstrations and interactive technology showcases generated strong interest among both domestic and international visitors.

The exhibition also served as a strong networking and business development platform, enabling direct interaction between OEMs, MSMEs, startups, R&D organisations, armed forces representatives, and global technology providers. Several exhibitors reported high-quality business enquiries and strategic partnership discussions during the event.

Building on the strong response to the 2026 edition, the organisers announced that the next edition of DEFTECH Bharat will be held from May 19–21, 2027, at the Bangalore International Exhibition Centre (BIEC), Bengaluru. The move to the larger BIEC venue comes in response to increasing exhibitor demand and rising visitor participation. The exhibition area for the 2027 edition is expected to expand significantly to accommodate a broader range of aerospace, defence, homeland security, and space technology exhibitors.

With India accelerating its focus on indigenous defence production and technology-led modernisation under the Atmanirbhar Bharat initiative, DEFTECH Bharat continues to evolve as an important industry platform connecting innovation, manufacturing, research, and strategic capability development for the future defence ecosystem.

The post DEFTECH Bharat 2026 Concludes Successfully, Sets Stage for Expanded 2027 Edition at BIEC appeared first on ELE Times.

Simple circuit ratios sensor capacitance to reference capacitor to measure micrometers.

It’s hard to imagine a simpler electromechanical sensor than the capacitance type, consisting of little more than two plates (or even just one if the sensed target is conductive) separated by a dielectric (e.g. air).  Sensor capacitance is approximately: C = 8.854pF S/d where S = area of the plates and d = their separation (both in meters).  C then becomes a sensitive readout of plate separation.

Wow the engineering world with your unique design: Design Ideas Submission Guide

Here’s a plausible example. With 38mm diameter circular plates and initial separation of 1mm, you get a nominal capacitance of C = 8.854pF * 0.0382 * pi / 4 / 0.001 = 10pF.  C would span 3.3pF at d = 3mm to 33pF at d = 0.3mm which, with a little math, can be converted into the distance between the plates.  But how to measure C?

For that, we’ll need an interface circuit.  The one in Figure 1 is a suitably simple match for the simplicity of the capacitive sensor itself, consisting of just 8 inexpensive off-the-shelf (OTS) parts.  Here’s how it works.

Figure 1 U1a and U1b cross-coupled Schmidt trigger timers form a ~1MHz RC multivibrator. For the example sensor dimensions and parts values, Output duty factor = x = Out / 5V = d/(d + 1mm). Therefore d = x/(1 – x)

U1a and U2a form an RC timer with a time constant equal to R1Csense while U1b and U2b do the same job for R2Cref.  Cross coupling them as shown in Figure 1 creates a square wave oscillator whose ~1MHz cycle on U1 pin 3 consists of dwelling at +V for Tref = 50ksec Cref = 500ns and at zero for Tsense = 50ksec Csense = 500ns / d where d, as earlier, is measured in mm. 

Thus, the Output duty factor “x” = Tref / (Tref + Tsense) = 500ns / (500ns + 500ns / d) = 1/(1 + 1/d) = d/(d + 1). Starting from x = d/(d + 1), a bit of rearranging yields x(d + 1) = d, then xd + x = d, x = d(1 – x), and finally d = x/(1 – x).  Figure 2 shows how this math performs when the Out signal is fed into a 12bit ADC.

Figure 2 This graph shows sensor performance when Out is connected to a 12bit ADC using +5V for its reference. The black curve (left axis) = plate separation (d) in millimeters, while the red curve (right axis) = ADC least significant bit (LSB) resolution in micrometers.  Note that the resolution is close to 0.1% (d/1000) over much of the range.

Details of circuit operation include the inherent matching and tracking of U1’s gates simply because they share the same chip, and of accurate duty factor digitization if the connected ADC uses +5V as its reference voltage.  Asterisked parts (R1, R2, and Cref) are precision types.  Stray wiring and layout capacitances should be scrupulously minimized.

If there’s a chance the sensor plates might come into contact and short out, then it’s a good idea to protect U2 with a series capacitor.  0.1uF (from the same bag as C1 and C2) will work well and be sufficiently larger than Csense such that its precision and stability (or lack of thereof) won’t matter.  I’d also put another one in series with Cref, although it’s not strictly necessary, just so things look more balanced.

If your application needs position sensing in two dimensions (e.g. an XY stage), the other halves of  U1 and U2 are ready and willing, which helps to keep things capaciously and suitably simple!

Stephen Woodward‘s relationship with EDN’s DI column goes back quite a long way. Over 200 submissions have been accepted since his first contribution back in 1974.  They have included best Design Idea of the year in 1974 and 2001.

Related Content

• Capacitor matchmaker
• CMOS flip-flop used “off label” implements precision capacitance sensor
• From gap to signal: Non-contact capacitive displacement sensors
• Simple circuit interfaces differential capacitance sensor
• The sensor parade at CES 2025

The post ~0.1% resolution capacitive position sensor appeared first on EDN.

Microchip Technology Inc of Chandler, AZ, USA has announced the availability of its new 3.3kV HV-D3 mSiC power modules, designed to simplify and accelerate the adoption of solid-state transformers (SSTs) in AI hyperscale data centers and other high-voltage power applications. The new modules integrate 3.3kV silicon carbide (SiC) mSiC MOSFETs and Schottky diodes in an industry-standard 62mm package, enabling efficient power delivery from the medium-voltage grid directly to the server rack...

New gallium nitride (GaN)-based power semiconductors from STMicroelectronics of Geneva, Switzerland are designed to improve efficiency and increase power density in high-voltage power supplies for high-demand applications that support electrification. The 700V PowerGaN devices in the STPOWER portfolio address challenges such as rising AI server power consumption and the need for higher-performance power conversion beyond the limits of conventional silicon technologies...

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