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The new step-down, synchronous DC-DC converters come in many configurations to save space and ease integration into automotive OEM designs.

Tape measures are right up there with uncooperative-coiling (and -uncoiling) extension cords and garden hoses on the list of “things guaranteed to raise my blood pressure”. They don’t work reliably (thanks to gravity) beyond my arm span unless there’s something flat underneath them for the entire distance they’re measuring. Metal ones don’t do well with curved surfaces, while fabric ones are even more gravity-vulnerable. Speaking of which, the only way to keep a fabric one neatly spooled when not in use is with a rubber band, which will inevitably slip off and leave a mess in whatever drawer you’re storing it in. And when metal ones auto-spool post-use, they inevitably slap, scratch, or otherwise maim your hand (or some other body part) enroute.

All of which explains why, when I saw Dremel’s HSLM-01 3-in-1 Digital Measurement Tool on sale at Woot! for $19.99 late last October, I jumped for joy and jumped on the deal. I ended up buying three of ‘em: one for my brother-in-law as a Christmas present, another for me, and the third one for teardown for all of you:

The labeling in this additional stock photo might be helpful in explaining what you just saw:

Here’s a more meaningful-info example of the base unit’s display in action:

The default laser configuration is claimed to work reliably for more than five dozen feet, with +/- 1/8-inch accuracy:

while the Wheel Adapter enables measuring curved surfaces:

and the Tape Adapter (yes, I didn’t completely escape tape, but at least it’s optional and still makes sense in some situations) is more accurate for assessing round-trip circumference (and yes, they spelled “circumference” wrong):

I mean…look how happy this guy is with his!

Apologies: I dilly-dally and digress. Let’s get to tearing down, shall we? Here’s our victim, beginning with the obligatory outer box shots:

And here’s what the inside stuff looks like:

Here’s part of the literature suite, along with the included two AAA batteries which I’ll put to good use elsewhere:

Technology licensed from Arm and STMicroelectronics? Now that’s intriguing! Hold that thought.

Here’s the remainder of the paper:

And here’s the laser measurer and its two-accessory posse:

This snapshot of the top of the device, as usual accompanied by a 0.75″ (19.1 mm) diameter U.S. penny for size comparison purposes:

is as good a time as any to conceptually explain how these devices work. Wikipedia more generally refers to them as laser rangefinders:

A laser rangefinder, also known as a laser telemeter, is a rangefinder that uses a laser beam to determine the distance to an object. The most common form of laser rangefinder operates on the time of flight principle by sending a laser pulse in a narrow beam towards the object and measuring the time taken by the pulse to be reflected off the target and returned to the sender. Due to the high speed of light, this technique is not appropriate for high precision sub-millimeter measurements, where triangulation and other techniques are often used. It is a type of scannerless lidar.

The basic principle employed, as noted in the previous paragraph, is known as “time of flight” (ToF), one of the three most common approaches (along with stereopsis, which is employed by the human visual system, and structured light, used by the original Microsoft Kinect) to discerning depth in computer vision and other applications. In the previous photo, the laser illumination emitter (Class 2 and <1mW) is at the right, with the image sensor receptor at left. Yes, I’m guessing that this explains the earlier STMicroelectronics licensing reveal. And the three metal contacts mate with matching pins you’ll soon see on the no-laser-necessary adapters.

The bottom is admittedly less exciting:

As are the textured and rubberized (for firm user grip) left and right sides (the two-hole structure at the bottom of the left side is presumably for a not-included “leash”):

I intentionally shot the front a bit off-center to eliminate reflections-of-self from bouncing off the glossy display and case finish:

The duller-finish backside presented no such reflectance concerns:

I have no idea what that white rectangular thing was inside the battery compartment, and I wasn’t brave enough to cut it open for a more thorough inspection (an RFID tracking tag, maybe, readers?):

This closeup of the back label does double-duty as a pictorial explanation of my initial disassembly step:

Screws underneath, just as I suspected!

You know what comes next…

Liftoff!

We can already see an overview of the laser transmitter function block (complete with a heatsink) at upper right and the receptor counterpart at upper left. Turns out, in fact, that the entire inner assembly lifts right out with no further unscrew, unglue, etc. effort at this point:

From an orientation standpoint, you’re now looking at the inside of the front portion of the outer case. Note the metal extensions of the three earlier noted topside metal contacts, which likely press against matching (flex? likely) contacts on the PCB itself. Again, hold that thought.

Now we can flip over and see the (even more bare) other side of the PCB for the first time:

This is a perspective you’ve already seen, this time absent the case, however:

Three more views from different angles:

And as you may have already guessed, the display isn’t attached to the PCB other than via the flex cable you see, so it’s easy to flip 180°:

Speaking of flipping, let’s turn the entire PCB back over to its back side, now unencumbered by the case that previously held it in place:

Again, some more views from different angles:

See those two screws? Removing them didn’t by itself get us any further along from a disassembly standpoint:

But unscrewing the two other ones up top did the trick:

Flipping the PCB back over and inserting a “wedge” (small flat head screwdriver) between the PCB and ToF subassembly popped the latter off straightaway:

Here’s the now-exposed underside of the ToF module:

and the seen-before frontside and end, this time absent the PCB:

Newly exposed, previously underneath the ToF module, is the system processor, a STMicrolectronics (surprise!…not, if you recall the earlier licensing literature…) STM32F051R8T7 based on an Arm Cortex-M0:

And also newly revealed is the laser at left which feeds the same-side ToF module optics, along with the image sensor at right which is fed by the optics in the other half of the module (keep in mind that in this orientation, the PCB is upside-down from its normal-operation configuration):

I almost stopped at this point. But those three metal contacts at the top rim of the base unit intrigued me:

There must be matching electrical circuitry in the adapters, right? I figured I might as well satisfy my curiosity and see. In no particular order, I started with my longstanding measurement-media nemesis, the Tape Adapter, first. Front view:

Top view:

Bottom view, revealing the previously foreshadowed pins:

Left and right sides, the latter giving our first glimpse at the end-of-tape tip:

And two more tip perspectives from the back:

Peeling off the label worked last time, so why not try again, right?

Revealed were two plastic tabs, which I unwisely-in-retrospect immediately forgot about (stay tuned). Because, after all, that seam along the top looked mighty enticing, right?

It admittedly was an effective move:

Here’s the inside of the top lid. That groove you see in the middle mates up with the end of the “spring” side of the spool, which you’ll see shortly:

And here’s the inside of the bottom bulk of the outer case. See what looks like an IC at the bottom of that circular hole in the center? Hmmm…

Now for the spool normally in-between those two. Here’s a top view first. That coiled metal spring normally fits completely inside the plastic piece, with its end fitting into the previously seen groove inside the top lid:

The bottom side. Hey, at least the tape isn’t flesh-mangling metal:

A side view, oriented as when it’s installed in the adapter and in use:

And by the way, about the spindle that fits into that round hole…it’s metallic. Again, hold that thought (and remember my earlier comment about using a rubber band to keep a fabric tape measure neat and tidy?):

Here’s the part where I elaborate on my earlier “forgot about the plastic tabs” comment. At first things were going fine:

But at this point I was stuck; I couldn’t muscle the inner assembly out any more. So, I jammed the earlier seen flat head screwdriver in one side and wedged it the rest of the way out:

Unfortunately, mangling one of the ICs on the PCB in the process:

Had I just popped both plastic tabs free, I would have been home free. Live and learn (once again hold that thought). Fortunately, I could still discern the package markings. The larger chip is also from STMicroelectronics (no surprise again!), another Arm Cortex-M0 based microcontroller, this time the STM32F030F4. And while at first, reflective of my earlier close-proximity magnetic-tip comment, I thought that the other IC (which we saw before at the bottom of that round hole) might be a Hall effect sensor, I was close-but-not-quite: it’s a NXP Semiconductors KMZ60 magnetoresistive angle sensor with integrated amplifier normally intended for angular control applications and brushless DC motors. In this case, the user’s muscle is the motor! Interesting, eh?

Now for the other, the Wheel Adapter. Front:

Top:

Bottom (pins again! And note that the mysterious white strip seen earlier was pressed into service as a prop-up device below the angled-top adapter):

Left and right sides:

And label-clad back:

I’m predictable, aren’t I?

Note to self: do NOT forget the two now-exposed plastic tabs this time:

That went much smoother this time:

But there are TWO mini-PCBs this time, one down by the contact pins and another up by the wheel, connected by a three-wire harness:

Unfortunately, in the process of removing the case piece, I somehow snapped off the connector mating this particular mini-PCB to the harness:

Let’s go back to the larger lower mini-PCB for a moment.  I won’t pretend to feign surprise once again, as the redundancy is likely getting tiring to the readers, but the main sliver of silicon here is yet another STMicroelectronics STM32F030F4 microcontroller:

The mini-PCB on the other end of the harness pops right out:

Kinda looks like a motor (in actuality, an Alps Alpine sensor), doesn’t it, but this time fed by the human-powered wheel versus a tape spool?

So, a conceptually similar approach to what we saw before with the other adapter, albeit with some implementation variation. I’ll close with a few shots of the now-separate male and female connector pair that I mangled earlier:

And now, passing through 2,000 words and fearful of the mangling that Aalyia might subject me to if I ramble on further, I’ll close, as-usual with an invitation for your thoughts in the comments!

—Brian Dipert is the Editor-in-Chief of the Edge AI and Vision Alliance, and a Senior Analyst at BDTI and Editor-in-Chief of InsideDSP, the company’s online newsletter.

Related Content

• Measuring powerful laser output takes a forceful approach
• Rotational (or linear) measurement using an optical mouse sensor
• Modeling and simulation of magnetoresistive sensor systems (Part 1 of 2)
• MEMS ultrasonic time-of-flight innovation: sensors advance user experiences
• 3D vision gives robots guidance

The post Looking inside a laser measurer appeared first on EDN.

Cadence has a mission to help solve technology’s toughest challenges to make a lasting, positive impact on our world, highlighting the company’s commitment to environmental stewardship and empowering employees to become ambassadors for sustainability both within and beyond the organization.

The launch of the Mission Sustainable program in 2023 marked an amplification of this commitment by mobilizing employees from every corner of the company to engage in sustainable development actively. This initiative underscores Cadence’s dedication to environmental care and its vision to cultivate a company-wide culture of sustainability champions.

Innovative Elements of Mission Sustainable

Cadence launched the Mission Sustainable program in 2023 with two key features: the “Live the Brand Sustainably” Quiz and the “Mission Sustainable Ideation Challenge.”

The Live the Brand Sustainably Quiz transformed learning into an exciting competition, deepening employee understanding of Cadence’s ESG efforts and spurring a spirited dialogue around sustainability. This educational contest has significantly bolstered internal engagement with the company’s sustainable vision.

The Mission Sustainable Ideation Challenge harnessed collective creativity by reaching out to our global team to devise innovative solutions in critical sustainability domains such as water conservation, waste reduction, and enhancing supply chain sustainability. Garnering over 150 ideas globally, the challenge culminated in a presentation before Cadence’s leadership, spotlighting the innovation engine driving the company.

A standout project by Indian software architects Gunjan Goel and Naina Dandona, titled “Climate Resilient Software Architecture,” clinched the challenge’s top honor, embodying the inventive spirit Cadence seeks to foster.

Nimish Modi, SVP and GM of Strategy and New Ventures and the executive champion of the program, highlights the foundational belief of Mission Sustainable: “Nurturing sustainability isn’t just a corporate responsibility; it’s a collective endeavor that requires the commitment and passion of every individual. At Cadence, our sustainability initiatives are about reducing our environmental footprint, innovating Cadence technology that delivers sustainability impact for our customers, and empowering our employees to become agents of positive change. Through meaningful engagement and collaboration, we are shaping a more sustainable future for our company and inspiring a broader culture of environmental stewardship.”

Charting a Course Towards Sustainable Excellence

The Mission Sustainable challenge has sparked engagement and participation throughout Cadence, encouraging collaboration towards achieving sustainability milestones. Cadence is forging ahead on its sustainability path, leveraging its employees’ diverse talents and innovative thinking, inviting all to be part of a greener, more responsible future.

Read more about Cadence’s environmental, social, and governance programs in the 2023 Cadence ESG Report.

The post Cadence Design Systems is empowering a sustainable future with Mission Sustainable Program appeared first on ELE Times.

Anritsu Corporation, a global leader in test and measurement solutions, is excited to unveil its groundbreaking advancements in field testing equipment – the Site Master MS2085A Cable and Antenna Analyzer and the MS2089A with Integrated Spectrum Analyzer. These latest entries to the Anritsu lineup are designed from the ground up to further cement Anritsu’s dominance in the installation and maintenance arena and to also address the multifaceted demands of the general-purpose market. They redefine industry standards for functionality, precision, and user-friendly operation, marking a transformative leap forward in field testing technology.

The Site Master MS2085A and MS2089A encapsulate the pinnacle of modern engineering, combining Anritsu’s extensive experience and commitment to customer-focused innovation. This dual offering merges the functions of cable and antenna analysis with spectrum analysis and monitoring in a seamless, integrated solution. It is tailored to support a wide spectrum of industries, including telecommunications, broadcasting, aerospace, satellite, and defense, facilitating a variety of applications from Distributed Antenna Systems (DAS) and satellite monitoring to interference analysis and routine installation and maintenance tasks.

Highlighted Features and Advantages:

• Multi-functional Capability: The Site Master’s integration of cable and antenna analysis alongside spectrum analysis equips professionals with a singular, versatile tool for a wide array of testing and analysis needs. It stands as a comprehensive solution for assessing antenna systems, diagnosing wireless networks, or conducting spectrum signal monitoring.
• Operational Efficiency: Merging multiple testing functions into one device, the Site Master significantly optimizes field testing workflows. This consolidation reduces the need for multiple instruments, streamlines testing processes, and allows for greater achievements in shorter timeframes – effectively enhancing productivity while minimizing operational costs.
• Accuracy and Dependability: Engineered for precision and built to withstand rigorous field conditions, the Site Master ensures consistent, reliable outcomes. Its superior measurement accuracy and robust construction instill confidence in every test result, allowing for precise, informed decisions under any circumstances.
• Advanced Features: With features like Real-Time Spectrum Analysis (RTSA), IQ capture and streaming, and PIM hunting, we’re not just meeting industry standards, we’re creating them.

Raymond Chan, Product Manager at Anritsu Corporation, expresses his enthusiasm: “We are thrilled to launch the Site Master MS2085A and MS2089A, signifying a monumental stride in field testing technology. These innovations underscore our dedication to advancing testing and measurement technologies that not only meet but exceed our customers’ evolving requirements across various sectors. They stand as a testament to Anritsu’s unwavering commitment to excellence, setting a new benchmark for field testing proficiency.”

The Site Master MS2085A and MS2089A Analyzers are now available globally. For detailed information on the products and their capabilities, please visit www.anritsu.com.

The post Anritsu Introduces Revolutionary Site Master MS2085A and MS2089A Analyzers: A New Era in Field Testing for Diverse Applications appeared first on ELE Times.

In the rapidly evolving semiconductor industry, keeping pace with Moore’s Law presents opportunities and challenges, particularly in system-on-chip (SoC) designs. Notably, the number of transistors in microprocessors soared to an unprecedented trillion.

Therefore, as modern applications demand increasing complexity and functionality, improving transistor usage efficiency without sacrificing energy efficiency has become a key goal. Thus, the network-on-chip (NoC) concept has been introduced, a solution designed to address the limitations of traditional bus-based systems by enabling efficient, scalable, and flexible on-chip data transmission.

Designing an NoC involves defining requirements, selecting an architecture, choosing a routing algorithm, planning the physical layout, and conducting verification to ensure performance and reliability. As the final checkpoint before a NoC can be deemed ready for deployment, a deadlock/livelock-free system can be built, increasing confidence in design verification.

In this article, we will dive deeper into a comprehensive methodology for formally verifying an NoC, showcasing the approaches and techniques that ensure our NoC designs are robust, efficient, and ready to meet the challenges of modern computing environments.

Emergence of network-on-chip

NoCs have revolutionized data communications within SoCs by organizing chip components into networks that facilitate the simultaneous transmission of data through multiple paths.

The network consists of various elements, including routers, links, and network interfaces, which facilitate communication between processing elements (PEs) such as CPU cores, memory blocks, and other specialized IP cores. Communication occurs through packet-switched data transmission where data is divided into packets and routed through the network to its destination.

One overview of the complexity of SoC design emphasizes the integration of multiple IP blocks and highlights the need for automated NoC solutions across different SoC categories, from basic to advanced. It advocates using NoCs in SoC designs to effectively achieve optimal data transfer and performance.

At the heart of NoC architecture are several key components:

1. Links: Bundles of wires that transmit signals.
2. Switches/routers: Devices routing packets from input to output channels based on a routing algorithm.
3. Channels: Logical connections facilitating communication between routers or switches.
4. Nodes: Routers or switches within the network.
5. Messages and packets: Units of transfer within the network, with messages being divided into multiple packets for transmission.
6. Flits: Flow control units within the network, dividing packets for efficient routing.

Architectural design and flow control

NoC topology plays a crucial role in optimizing data flow, with Mesh, Ring, Torus, and Butterfly topologies offering various advantages (Figure 1). Flow control mechanisms, such as circuit switching and wormhole flow control, ensure efficient data transmission and minimize congestion and latency.

Figure 1 The topology of an NoC plays an important role in optimizing data flow, as shown with Mesh and Ring (top left and right) and Torus and Butterfly (bottom left and right). Source: Axiomise

Role of routing algorithms in NoC efficiency

As we delve into the complexity of NoC design, one integral aspect that deserves attention is the routing algorithm, the brains behind the NoC that determines how packets move through the complex network from source to destination. They must be efficient, scalable, and versatile enough to adapt to different communication needs and network conditions.

Some of the common routing algorithms for network-on-chip include:

1. XY routing algorithm: This is a deterministic routing algorithm usually used in grid-structured NoCs. It first routes to the destination columns along the X-axis and then to the destination rows along the Y-axis. It has the advantages of simplicity and predictability, but it may not be the shortest path and does not accommodate link failures.
2. Parity routing algorithm: This algorithm aims to reduce network congestion and increase fault tolerance of the network. It avoids congestion by choosing different paths (based on the parity of the source and destination) in different situations.
3. Adaptive routing algorithms: These algorithms dynamically change routing decisions based on the current state of the network (for example, link congestion). They are more flexible than XY routing algorithms and can optimize paths based on network conditions, but they are more complex to implement.
4. Shortest path routing algorithms: These algorithms find the shortest path from the source node to the destination node. They are less commonly used in NoC design because calculating the path in real-time can be costly, but they can also be used for path pre-computation or heuristic adjustment.

Advantages of NoCs

1. Scalability: As chip designs become more complex and incorporate more components, NoCs provide a scalable solution to manage interconnects efficiently. They facilitate the addition of new components without significantly impacting the existing communication infrastructure.
2. Parallelism: NoCs enable parallel data transfers, which can significantly increase the throughput of the system. Multiple data packets can traverse the network simultaneously along different paths, reducing data congestion and improving performance.
3. Power consumption: By providing shorter and more direct paths for data transfer, NoCs can reduce the chip’s overall power consumption. Efficient routing and switching mechanisms further contribute to power savings.
4. Improved performance: The ability to manage data traffic efficiently and minimize bottlenecks through routing algorithms enhances the overall performance of the SoC. NoCs can adapt to the varying bandwidth requirements of different IP blocks, providing optimized data transfer rates.
5. Quality of service (QoS): NoCs can support QoS features, ensuring that critical data transfers are given priority over less urgent communications. This is crucial for applications requiring high reliability and real-time processing.
6. Flexibility and customization: The flexibility and customization of the NoC architecture is largely due to its ability to employ a variety of routing algorithms based on specific design requirements and application scenarios.
7. Choice of routing algorithm: Routing algorithms in an NoC determine the network path of a packet from its source to its destination. The choice of routing algorithm can significantly impact the performance, efficiency, and fault recovery of the network.

NoC verification challenges

Designing an NoC and ensuring it works per specification is a formidable challenge. Power, performance, and area (PPA) optimizations—along with functional safety, security, and deadlock and livelock detection—add a significant chunk of extra verification work to functional verification, which is mostly centred on routing, data transport, data integrity, protocol verification, arbitration, and starvation checking.

Deadlocks and livelocks can cause a chip respin. For modern-day AI/ML chips, it can cost $25 million in some cases. Constrained random simulation techniques are not adequate for NoC verification. Moreover, simulation or emulation cannot provide any guarantees of correctness. So, formal methods rooted in proof-centric program reasoning are the only way of ensuring bug absence.

Formal verification to the rescue

Industrial-grade formal verification (FV) relies on using formal property verification (FPV) to perform program reasoning, whereby a requirement expressed using the formal syntax of System Verilog Assertions (SVA) is checked against the design model via an intelligent state-space search algorithm to conclude whether the intended requirement holds on all reachable states of the design.

The program reasoning effort terminates with either a proof or a disproof, generating counter-example waveforms. No stimulus is generated by human engineers, and the formal verification technology automatically generates almost an infinite set of stimuli only limited by the size of inputs. This aspect of verifying designs via proof without any human-driven stimulus and with almost an infinite set of stimuli is at the heart of formal verification.

It gives us the ability to pick corner-case issues in the design as well as pick nasty deadlocks and livelocks lurking in the design. Deep interactions in state space are examined quickly, revealing control-intensive issues in the design due to concurrent arbitration and routing traffic in the NoC.

With NoCs featuring numerous interconnected components operating in tandem, simulating the entire range of possible states and behaviors using constrained-random simulation becomes computationally burdensome and impractical. It is due to the intense effort needed for driving stimuli into the NoC that is needed to unravel the state-space interaction, which is not easily possible. This limitation undermines the reliability and precision of simulation outcomes.

Compelling advantages of NoC architectures tout the benefits of integrating FV into the design and verification process using easy-to-understand finite state machine notations and using protocol checkers developed for FV in chip and system integration testing increases confidence and aids error detection and isolation.

The effectiveness of this approach and the challenges of verifying complex systems with large state spaces are emphasized when compared to traditional system simulation successes.

An NoC formal verification methodology

In the complex process of chip design verification, achieving simplicity and efficiency amid complexity is the key. This journey is guided through syntactic and semantic simplification and innovative abstraction techniques.

In addition to these basic strategies, using invariants and an internal assumption assurance process further accelerates proof times, leveraging microarchitectural insights to bridge the gap between testbench and design under test (DUT). This complex verification dance is refined through case splitting and scenario reduction, breaking down complex interactions into manageable checks to ensure comprehensive coverage without overwhelming the verification process.

Symmetry reduction and structural decomposition address verification challenges arising from the complex behavior of large designs. These methods, along with inference-rule reduction and initial-value abstraction (IVA), provide a path that effectively covers every possible scenario, ensuring that even the most daunting designs can be confidently verified.

Rate flow and hopping techniques provide innovative solutions to manage the flow of messages and the complexity introduced by deep sequential states. Finally, black-box and cut-pointing techniques are employed to simplify the verification environment further, eliminating internal logic not directly subject to scrutiny and focusing verification efforts where they are most needed.

Through these sophisticated techniques, the goal of a thorough and efficient verification process becomes a tangible reality, demonstrating the state-of-the-art of modern chip design and verification methods.

Safeguarding NoCs against deadlocks

When setting up NoCs, it’s important for channels to be independent, but it’s not easy to ensure of this. Dependencies between channels can lead to troublesome deadlocks, where the entire system halts even if just one component fails.

Formal verification also contributes to fault tolerance, crucial in NoCs where numerous components communicate. When a component fails, it’s important to understand how close the system is to a permanent deadlock.

Formal verification exhaustively explores all possible system states, offering the best means to ensure fault tolerance. With the right approach, weaknesses of an NoC can be identified and addressed. Catching them early on can save the expensive respin.

Optimizing routing rules to suit the needs is common and critical for performance, but it can be tricky and hard to thoroughly test in simulation. Hundreds of new test cases may emerge just by introducing one new routing rule.

So, modelling all the optimizations in formal verification is crucial. If done properly, it can catch corner case bugs quickly or prove that optimizations behave as expected, preventing unexpected issues.

In the next section, we describe at a high level how some bugs can be caught with formal verification.

Formal verification case studies

Message dependence caused deadlock

A bug originated from a flaw in the flow control mechanism where both request and response packets shared the same FIFO. In this scenario, when multiple source ports initiate requests, the flow control method leads to a deadlock. For instance, when source port 0 sends a request reqs0, consisting of header flit h0req, body b0req, and tail t0req, it gets moved successfully.

Subsequently, the response resps0 made of (h1resp, b1resp, t1resp) intended also for source port 0 arrive, it causes no issue. However, when a subsequent request reqs2 from source port 2 with header flit h2req, body b2req, and tail t2req entered the FIFO, only its header and body move forward, but the tail is blocked from being sampled in the FIFO as the response’s header h2resp has blocked the tail t2req because they arrive in the same clock cycle.

Consequently, source port 2 was left waiting for the tail t2, and found itself blocked by the response header, resulting in a deadlock. Meanwhile, source port 1, also waiting for a response, would never get one, further exacerbating the deadlock situation. This deadlock scenario paralyzed the entire NoC grid, highlighting the critical flaw in the flow control mechanism.

Figure 2 Dependence between request and response causes deadlock. Source: Axiomise

Routing error caused deadlock

In the context of the previously mentioned flow control method, each source port awaits a response after sending a request. However, a deadlock arises due to a flaw in the routing function. When a request is mistakenly routed to an incorrect target port, triggering the assertion of the “wrong_dest” signal, the packet is discarded. Consequently, the source port remains in a state of deadlock, unable to proceed with further requests while awaiting a response that will never arrive.

Figure 3 A deadlock in the flow is caused by a routing error and is unable to proceed. Source: Axiomise

Redundant logic revealing PPA issues

Certain design choices in the routing algorithm, such as prohibiting-specific turns, lead to situations where several FIFOs never have push asserted, and some arbiters handle less than two requestors.

This has been identified during the verification process, revealing that these components—and consequently, millions of gates—are going unused in the design but still occupy chip area and, when clocked, would burn power while not contributing to any performance. Eliminating these superfluous gates significantly reduced manufacturing costs and improved design efficiency.

The case for formal verification in NoC

An NoC-based fabric is essential for any modern high-performance computing or AI/ML machine. NoCs enhance performance by efficient routing to avoid congestion. While NoCs are designed to be efficient at data transmission via routing, they often encounter deadlocks and livelocks in addition to the usual functional correctness challenges between source and destination nodes.

With a range of topologies possible for routing, directing simulation sequences to cover all possible source/destination pairs is almost impossible for dynamic simulation. Detecting deadlocks, starvation and livelocks is nearly impossible for any simulation or even emulation-based verification.

Formal methods drive an almost infinite amount of stimulus to cover all necessary pairs encountered in any topology. With the power of exhaustive proofs, we can establish conclusively that there isn’t a deadlock or a livelock or starvation with formal.

Editor’s Note: Axiomise published a whitepaper in 2022, summarizing a range of practically efficient formal verification techniques used for verifying high-performance NoCs.

Zifei Huang is a formal verification engineer at Axiomise, focusing on NoC and RISC-V architectures.

Adeel Liaquat is an engineering manager at Axiomise, specializing in formal verification methodologies.

Ashish Darbari is founder and CEO of Axiomise, a company offering training, consulting, services, and verification IP to various semiconductor firms.

Related Content

• Introduction to Formal Verification
• What is the future for Network-on-Chip?
• Interconnect (NoC) verification in SoC design
• How formal verification saves time in digital IP design
• Specifications: The hidden bargain for formal verification

The post Why verification matters in network-on-chip (NoC) design appeared first on EDN.

The SAMD21RT MCU is offered in 64-pin ceramic and plastic packages with a 10 mm × 10 mm footprint

Space exploration is experiencing a resurgence with exciting new missions like the highly anticipated Artemis II mission, the recent successful lunar landing missions such as JAXA SLIM and Chandaaryan-3, and New Space deployments in Low Earth Orbit (LEO). Designers require electronic components that meet stringent radiation and reliability standards to operate in the harsh environments found in space. Microchip Technology  today announces the SAMD21RT, a radiation-tolerant (RT) Arm Cortex-M0+ based 32-bit microcontroller (MCU) in a 64-pin ceramic and plastic package with 128 KB Flash and 16 KB SRAM.

Designed for space-constrained applications where size and weight are of critical importance, the SAMD21RT is available in a small footprint of 10 mm × 10 mm. Running at up to 48 MHz, the SAMD21RT delivers high-performance processing for harsh environments. The device integrates analog functions including an Analog-to-Digital Converter (ADC) with up to 20 channels, a Digital-to-Analog Converter (DAC) and analog comparators.

The SAMD21RT device builds on Microchip’s existing family of SAMD21 MCUs, which is widely used in industrial and automotive markets. It is also based on Commercial-Off-The-Shelf (COTS) devices, which significantly simplifies the design process when transitioning to a radiation-tolerant device as the design remains pinout compatible. Microchip offers a comprehensive system solution for space applications with many devices that can be designed around the SAMD21RT MCU including FPGAs, power and discrete devices, memory products, communication interfaces and oscillators providing a broad range of options across qualification levels.

To withstand harsh environments including radiation and extreme temperatures, the SAMD21RT can operate in temperatures ranging from −40°C to 125°C and provides a high level of radiation tolerance with a Total Ionizing Dose (TID) capability up to 50 krad and Single Event Latch-up (SEL) immunity up to 78 MeV.cm²/mg.

“The advantage of working with Microchip is that we have the history, knowledge and capability to do the design and testing in house for our radiation-tolerant and radiation-hardened devices,” said Bob Vampola, vice president of Microchip’s aerospace and defense business unit. “We continue to bring newer technologies like Ethernet, AI and ML, which have evolved in the commercial and industrial markets, and improve them with radiation performance to meet the needs of space missions. We also continue to provide higher computing performance and integration of newer technologies into smaller packages, reducing weight and size.”

The low-power SAMD21RT features idle and standby sleep modes and sleepwalking peripherals. Other peripherals include a 12-channel Direct Memory Access Controller (DMAC), a 12-channel event system, various Timer/Counters for Control (TCC), a 32-bit Real Time Counter (RTC), a Watchdog Timer (WDT) and a USB 2.0 interface. Communication options include Serial Communication (SERCOM), I2C, SPI and LIN.

With tens of thousands of parts in orbit, Microchip has been a significant part of space exploration history and is critical to the missions of today and tomorrow. Its products are on the way to the moon as part of the Artemis program and are contributing to the success of the Space Launch System, Orion Spacecraft, Lunar Gateway, Lunar Lander and next-generation spacesuits. To learn more about Microchip’s space heritage, visit the space applications page on the company’s website.

Development Tools

The SAMD21RT 32-bit MCU is supported by the SAM D21 Curiosity Nano Evaluation Kit, MPLAB® X Integrated Development Environment (IDE) and MPLAB PICkit 5 in-circuit debugger/programmer.

Pricing and Availability

The SAMD21RT 32-bit MCU is available in limited sampling upon request. For additional information, contact a Microchip sales representative.

Resources

High-res images available through Flickr or editorial contact (feel free to publish):

• Application image: flickr.com/photos/microchiptechnology/53641199810/sizes/l

The post Microchip Expands its Radiation-Tolerant Microcontroller Portfolio with the 32-bit SAMD21RT Arm Cortex-M0+ Based MCU for the Aerospace and Defense Market appeared first on ELE Times.

Authors: Akshat JAIN, STMicroelectronics India, Fabrizio Di FRANCO, STMicroelectronics, Italy, Martin DENDA, Rene WUTTE, STMicroelectronics Austria, Bruno TISSERAND, STMicroelectronics, France

Wireless power is going to introduce significant innovations in kitchens, making them smarter, sleeker and more space-efficient. Appliances from simple low-power juicers to blenders or kettles, and others that require up to 2.2 kW of power will benefit by eliminating power cords thanks to the new standard “Ki Cordless Kitchen” that is set to be released by the Wireless Power Consortium. The key driver of rapid adoption is interoperability. All certified Ki transmitters and appliances will follow defined safety protocols and work with each other, regardless of the brand, device type, or version of Ki they use.

The Ki transmitter can also be considered a smart induction cooktop that will not only power Ki receivers but also operate standard induction utensils like heating a pan. Ki enables smart communication between transmitters and appliances based on Near Field Communication (NFC) providing auxiliary power, bi-directional data paths, advanced control features, authentication and protections (FOD) and it is essential for interoperability. The block diagram of the Ki Cordless Kitchen concept block diagram is highlighted in Figure 1.

Figure 1: Ki Cordless Kitchen concept block diagram

STMicroelectronics, a global semiconductor leader serving customers across the wide spectrum of electronics applications, has been participating in the Ki Cordless Kitchen standard since the beginning and is ready with the Ki Cordless Kitchen power transmitter reference design i.e. STEVAL-KITXCB. The reference design consists of a power inverter board, auxiliary power supply board, an NFC board, inverter microcontroller board, a power coil, NFC antenna and GUI display board as shown in Figure 2. Thanks to the modular design approach, it is easy for users to test and debug the various sections involved.

Figure 2: Ki Cordless Kitchen evaluation kit (STEVAL-KITXCB)

The main power board comprises an inverter stage based on half-bridge topology. The IGBTs during power transfer switch between 26 to 74 kHz. The power inverter board is connected to a power coil and is digitally controlled by the STM32G474RET6 microcontroller, which specifically addresses the needs of digital power conversion applications thanks to the High-resolution timer peripheral and a rich and advanced integrated analog. The NFC communication between the Ki transmitter and Ki receiver is managed by ST25R3916, a high-performance NFC universal device which is mounted on a dedicated daughter card. The NFC antenna is connected to the NFC daughter card. The auxiliary power supply is managed by an off-line flyback circuitry based on VIPer318, high voltage converter ensuring compactness and very low standby consumption to generate 24V DC. The interconnection between the main power inverter board and the daughter cards of the evaluation kit is shown in Figure 3. The inverter stage is based on STGWA50IH65DF trench gate field-stop 650 V IH series IGBT, featuring very low Vcesat and Eoff to ensure high efficiency at high switching frequency and supported by the robust half-bridge gate driver L6491D, provided with high driving current source and sink capability.

Figure 3: Ki Cordless Kitchen transmitter reference design (STEVAL-KITXCB) – Block Diagram

The Ki Kitchen standard protocol is managed by a dedicated STM32L476VGT64 microcontroller mounted on an NFC daughter card and it communicates over UART with the STM32G474RET6 microcontroller, which is managing power inverter stage. During startup when the Ki receiver/appliance is brought on top of induction hub the Ki transmitter will supply the initial energy to power the User interface of the appliance through NFC and establish a  communication carrier as shown in Figure 4. And when the Ki receiver/appliance is switched ON (requesting power from the Ki transmitter) from its user interface, then the auxiliary power transfer from NFC stops, and the power inverter of the Ki transmitter transmits the power including auxiliary power to the Ki receiver via the principle of induction.

Figure 4: NFC Communication – Idle state and power transfer state

To prevent interference between NFC and wireless induction power transfer during the power transfer state, the wireless induction power transfer is switched completely off during the mains crossing and NFC becomes active as shown in Figure 4.

Ki receiver vs Induction Utensil (Pan/Pot)

The standard induction utensils are made of ferromagnetic materials. The bottom of an induction utensil (pan/pot) can be treated as an induction coil with one winding and low load resistance where received power is dissipated. So, the power transmitter coil and utensil can be considered a transformer in which the induction utensil acts as a shorted secondary (load). An alternating current is made to flow through the transmitter resonant power coil, which leads to the generation of an oscillating magnetic field. The magnetic field induces an electric current inside the induction utensil.

The Ki receiver mainly consists of a resonant power coil, resonant capacitor, NFC circuitry and Ki receiver/appliance circuitry. For the Ki transmitter the power coil is fixed but for the Ki receivers, the size of the power coil varies depending on the power requirements. To maximize the energy transfer, the Ki receiver must be tuned to the transmitter’s resonant frequency. Now, there will be two resonance points: one of the Ki transmitter and the other of the Ki receiver. To have better efficiency, the transmitter needs to operate at a second resonant frequency, but that doesn’t guarantee the maximum power required by the Ki receiver. To transmit the desired power the Ki transmitter needs to shift to the first resonant frequency. The resonant shift is managed by the STM32G474RET6 microcontroller control algorithm.

To shorten the development time and let customers evaluate products in the final application, STMicroelectronics offers a reference design (STEVAL-KITXCB) for the transmitter and is working on the reference design for the different types of receivers. The hardware design files and firmware source code are available with developer-friendly license terms. For more details, please contact the STMicroelectronics sales office.

The post Wireless Power in the Kitchen appeared first on ELE Times.

Google's sixth-generation tensor processing unit (TPU) stole the company's I/O developer conference stage with its higher-than-ever computing performance.

The differential Hall-based angle sensor features intrinsic stray field robustness for automotive designs.

A generally accepted fact about relays and solenoids is that after they’re driven into the actuated state, only half as much coil voltage and therefore only one fourth as much coil power, are required to reliably sustain it. Consequently, any solenoid or relay driver that continuously applies the full initial actuation voltage to merely sustain is wastefully squandering four times as much power as the job requires.

The simplest and cheapest (partial) solution to this problem is shown in Figure 1.

 Figure 1 Basic driver circuit where C1 actuates, current-halving R1 sustains, then C1 discharges through R1 during Toff.

Wow the engineering world with your unique design: Design Ideas Submission Guide

But as is often true of “simple and cheap,” Figure 1’s solution suffers from some costs and complications.

1. While R1 successfully cuts sustaining current by half, it dissipates just as much power as the coil as it does so. Consequently, total sustaining power is ½ rather than ¼ of actuating power, so only half of the theoretical power savings are actually realized.
2. When the driver is turned off, a long recovery delay must be imposed prior to the next actuation pulse to allow C1 enough time to discharge through R1. Otherwise, the next actuation pulse will have inadequate amplitude and may fail. This effect is aggravated by the fact that, during actuation, C1 charges through the parallel combination of R1 and Rm, but during Toff it discharges through R1 alone. This makes recovery take twice as long as actuation.

Figure 2 presents a better performing, albeit less simple and cheap, solution that’s the subject of this Design Idea.

Figure 2 Q1 and Q2 cooperate with C to double VL for actuation, Q2 and D2 sustain, then Q3 rapidly discharges C through R to quickly recover for the next cycle.

Actuation begins with a positive pulse at the input, turning Q1 on which drives the bottom end of the coil to -VL and turns on Q2 which pulls the top end of the coil to +VL. Thus, 2VL appears across the coil, insuring reliable actuation. As C charging completes, Schottky diode D2 takes over conduction from Q1. This cuts the sustaining voltage to ½ the actuation value, and therefore drops sustaining power to ¼.

At the end of the cycle when the incoming signal returns to V0, Q3 turns on, initiating a rapid discharge of C through D2 and R. In fact, recovery can easily be arranged to complete in less time than the relay or solenoid needs to drop out. Then no explicit inter-cycle delay is necessary and recovery time is therefore effectively zero!

Moral: You get what you pay for!

But what happens if even doubling the VL logic rail still doesn’t make enough voltage to drive the coil and a higher supply rail is needed? 

Figure 3 addresses that issue with some trickery described in an earlier Design Idea: Driving CMOS totem poles with logic signals, AC coupling, and grounded gates.

 

Figure 3 Level shifting Q4, R1, and R2 are added to accommodate ++V > VL.

 Stephen Woodward’s relationship with EDN’s DI column goes back quite a long way. Over 100 submissions have been accepted since his first contribution back in 1974.

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• Simple solenoid driver is adaptable and efficient

The post Relay and solenoid driver circuit doubles supply voltage to conserve sustaining power appeared first on EDN.

КПІшники перемогли на хакатоні з кібербезпеки medialab пн, 05/20/2024 - 16:08

At a time when scalable high-bandwidth and low-latency connectivity is becoming critical for artificial intelligence (AI) clusters, the new 400G PCIe Gen 5.0 Ethernet adapter chips aim to resolve connectivity bottlenecks in AI data centers.

Broadcom claims its 400G PCIe Gen 5.0 chips are the first Ethernet adapters built with 5-nm process technology. “We recognize the significance of fostering a power-efficient and highly connected data center for AI ecosystem,” said Jas Tremblay, VP and GM of the Data Center Solutions Group at Broadcom.

The 400G PCIe Gen 5.0 Ethernet adapters deliver higher rack density by driving passive copper cables up to five meters. Moreover, these Ethernet adapters employ low-latency congestion control technology and innovative telemetry features while equipped with a third-generation RDMA over Converged Ethernet (RoCE) pipeline.

These Ethernet adapters are built on Broadcom’s sixth-generation hardened network interface card (NIC) architecture. Their software is designed to be vendor agnostic; it supports a broad ecosystem of CPUs, GPUs, PCIe and Ethernet switches using open PCIe and Ethernet standards.

Ethernet adapter chips must resolve connectivity bottlenecks as cluster sizes grow rapidly in AI data centers. Source: Broadcom

According to Patrick Moorhead, chief analyst at Moor Insights and Strategy, as the industry races to deliver generative AI at scale, the immense volumes of data that must be processed to train large language models (LLMs) require even larger server clusters. He added that Ethernet presents a compelling case as the networking technology of choice for next-generation AI workloads.

AI-centric applications are reshaping the data center networking landscape, and Broadcom’s new 400G PCIe Gen 5.0 Ethernet adapters highlight the crucial importance of devices operating in the high-bandwidth, high-stress network environment that characterizes AI infrastructure.

Related Content

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The post Ethernet adapter chips aim to bolster AI data center networking appeared first on EDN.

Хроніка життя КПІ під час оборони Києва у лютому — квітні 2022 року medialab пн, 05/20/2024 - 11:36

Семінар з національної безпеки та оборони medialab пн, 05/20/2024 - 11:35

Наука та дослідження КПІ — на світовому рівні medialab нд, 05/19/2024 - 23:06

When a CMOS inverter switches logic states, power is consumed due to its charging and discharging currents. Learn how to simulate these currents in LTspice.

My grandparents got this pinball machine in the mid 60s. There was a mechanical spinner that would register and record a highlighted letter if you hit a certain thing when it was lit up. It used a mechanical spinning device that broke, so my grandfather built the circuit board as a sort of logic puzzle after taking apart the mechanical device and figuring out what it needed. don’t know anything about electronics, but I thought y’all might be interested submitted by /u/MarchogGwyrdd [link] [comments]