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Sivers Semiconductors AB of Kista, Sweden (which supplies RF beam-former ICs and lasers for AI data-center, SATCOM, defense and telecom applications) and SemiNex Corp of Danvers, MA, USA – which designs and makes indium phosphide (InP) lasers diodes, DFB lasers, semiconductor optical amplifiers (SOAs) and external-cavity lasers – have announced a program for next-generation InP light sources for AI data-center interconnects...

Applied Materials, Inc. today announced that the University of California, Berkeley will join the company’s EPIC Center in Silicon Valley as a research collaborator. Working side by side with Applied’s scientists and engineers, UC Berkeley faculty and students will pursue high-impact research programs to accelerate the material and process innovations that are foundational to AI computing.

“The EPIC Center is designed to bring together the best minds from industry and academia in a high-velocity, manufacturing relevant environment to dramatically accelerate the development and commercialization of next-generation semiconductor technologies,” said Dr. Prabu Raja, President of the Semiconductor Products Group at Applied Materials. “Few institutions have shaped modern chipmaking as profoundly as UC Berkeley. Expanding our research collaboration at the EPIC Center strengthens the lab-to-fab innovation pipeline and gives us a powerful platform for developing the semiconductor talent the industry will depend on for decades to come.”

Research universities generate many of the ideas that become tomorrow’s semiconductor materials and process technologies, yet those ideas advance fastest when researchers can test them on the same equipment used by global manufacturers. Applied’s EPIC Center gives university researchers access to industry-scale tools, enabling rapid iteration, earlier validation and a smoother handoff from discovery to deployment.

UC Berkeley brings a history of translating foundational research into commercial semiconductor technology. UC Berkeley engineers built the first research laboratory at a university dedicated to prototyping integrated circuits in 1962. In the decades that followed, the institution produced breakthroughs the entire industry now runs on – among them the SPICE circuit simulator and the FinFET, the three-dimensional transistor that is now the basis of leading-edge logic manufacturing worldwide. That heritage of moving inventions out of the lab and into high-volume production is precisely what the EPIC Center is built to accelerate.

“Pioneering innovations by UC Berkeley researchers have enabled advancements in semiconductor chip technology, resulting in the exponential growth of computing that has ushered in the AI era,” said Mark Asta, dean of UC Berkeley’s College of Engineering. “Applied Materials’ new EPIC Center in the heart of Silicon Valley aims to speed the translation of university inventions into commercial products by providing early access to cutting-edge, industrial-scale semiconductor process equipment and technologies. I look forward to advancing research and supporting new engineering talent through this R&D collaboration with Applied Materials.”

Applied and UC Berkeley already share strong ties through semiconductor research collaborations and shared laboratory space, including work connected to the Berkeley Emerging Technologies Research (BETR) Center and the Center for Information Technology Research in the Interest of Society (CITRIS). A large network of UC Berkeley alumni works at Applied as engineers, scientists and managers, and Applied recruits from the campus each year. Both organizations are rooted in the same Silicon Valley ecosystem, allowing ideas, people and equipment to move easily between campus and industry.

Applied’s new EPIC (Equipment and Process Innovation and Commercialization) Center in Silicon Valley represents the largest ever U.S. investment in advanced semiconductor equipment R&D. The center is designed from the ground up to dramatically reduce the time it takes to commercialize breakthrough technologies from early-stage research to full-scale manufacturing. The facility is on track to become operational in 2026.

 

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BAE Systems Inc says that its FAST Labs research, development and production organization of Nashua, NH, USA has completed Phase 1 of the US Defense Advanced Research Projects Agency’s (DARPA) program Technologies for Heat Removal in Electronics at the Device Scale (THREADS) and has been awarded continued support to move into Phase 2...

PayU, India’s leading diversified fintech platform, today announced the launch of Accessible Payments Checkout, India’s first RBI-compliant payment checkout designed for people who are blind or visually impaired. The launch marks a significant step towards making digital payments more accessible and inclusive. As the country celebrates Independence Day, the launch reinforces the importance of ensuring that everyone can participate in the digital economy with greater independence.

With this launch, PayU becomes the first payment gateway in India to comply with the Reserve Bank of India’s October 2024 accessibility mandate (BIS IS 17802). The enhanced checkout introduces a range of features designed to improve discoverability, navigation, and interaction for users with visual and cognitive accessibility needs, making the online payment journey more seamless and intuitive.

The solution reflects PayU’s continued commitment to building inclusive financial technology and enabling every user to access digital payments with confidence and ease.

The new PayU Accessibility Checkout includes four key features:

• Full-Screen-Reader Optimisation: PayU’s Accessibility Checkout is engineered to work seamlessly with screen readers, ensuring easy navigation of the entire payment journey for the visually impaired and blind without any sighted assistance. From choosing the payment method like Net banking, UPI, QR, NEFT, etc. to payment amount confirmation and transaction completion, every element on the checkout page is clearly and transparently announced via voice commands to the user, ensuring they know where exactly they are in their payment journey.
• Adaptive User Profiles: This feature allows users to customize their checkout environments–adjusting cursor size, button dimensions, and navigation aids to fit their requirements. Their preferences can be saved, switched between or reset at any point. The checkout adapts as the user wants, delivering complete control in the hands of the user.
• Visual Inclusivity Modes: To aid users with conditions such as low vision, colour blindness, or light sensitivity, a wide variety of visual modes are offered by PayU’s Accessibility Checkout. From high contrast to greyscale mode to colour inversion to saturation adjustment options, the checkout offers support to the visually impaired users who rely on colour and contrast adaptations to use digital platforms.
• Text Resizing: The Accessibility Checkout supports text scaling of up to 200% of the standard size, without overlapping or hiding any content. This feature ensures all elements on the checkout is transparently seen and read by the users with visual impairments.

“True financial inclusion is only possible when every individual can access and use digital payments independently. At PayU, accessibility is not an afterthought – it’s a core design principle. With the launch of our Accessibility Checkout, we’re helping merchants deliver payment experiences that are inclusive by design while enabling millions of users with diverse accessibility needs to participate more confidently in India’s digital economy. This is an important step towards supporting the RBI’s accessibility vision and building digital infrastructure that works for everyone,” said Manas Mishra, Chief Product Officer, PayU and Wibmo.

Prashant Ranjan Verma, General Secretary, National Association for the Blind, Delhi, said, “I appreciate PayU’s efforts to make digital payments more accessible for everyone, including people who are blind or have low vision. I was able to complete a UPI payment independently using PayU’s accessibility-first checkout with VoiceOver. I hope PayU continues to strengthen accessibility so that more people with visual impairments can transact confidently and independently.”

PayU’s Accessibility Checkout does not require merchants to change their existing integrations. Accessibility is embedded as a design feature allowing merchants using PayU to automatically offer a compliant and accessibility-first payments checkout experience to their customers with disabilities.

The post PayU Launches India’s First RBI-Compliant Accessible Payments Checkout for Blind and Visually Impaired Users appeared first on ELE Times.

AI-driven demand underpins logic foundry and memory fab capacity constraints, leading to cost increases. Add tariffs to the mix, and Google and its competitors (not to mention end users) pay the price.

Last year’s Made By Google fall product launch event happened midday on August 20, moderated by Jimmy Fallon. Although I found value in the devices, software and services Google unveiled there, the un-traditional Tonight Show-styled format wasn’t particularly to my liking, a negative opinion shared by a notable number of others whose coverage I subsequently perused.

This year’s event, earlier today (August 12) as I write this, was once again celebrity-moderated, this time by Trevor Noah. But this time it took place in the evening, with the announcements notably preceding it; a flurry of blog posts had already hit Google’s website at 8 am MT, where I am. Feel free to draw your own conclusions as to the judged effectiveness (or, perhaps more accurate, lack thereof) of last year’s event And begging the question of why Google bothered doing this year’s event at all, save I suppose for the chance to see “live” demos, “softball” interviews and other such questionable-value content.

That said, the products themselves once again were notable, both in an absolute sense and relative to their prior-generation predecessors.

Befitting my engineering-dominated readership, I’ll as usual start out my coverage with the application processor, the Tensor G6, the intelligence nexus of the Pixel 11 smartphone series.

Power/performance balance (and profit) optimization

When I published last year’s event coverage, little was known at the time about the latest-generation Tensor G5 SoC save for its 3 nm TSMC fabrication source (a notable departure from Google’s longstanding foundry partnership with Samsung) and its eight-core CPU cluster mix: “one “prime” core, five mid-level ones, and two efficiency ones.” Beyond that, all Google was saying at the time was that, versus its Tensor G4 predecessor, it delivered the following updates.

• An up to 60% more powerful TPU
• A 34% faster on average CPU, and
• New security hardware

One year later, thanks to intensive developer engagement with the platform, we know much more about the Tensor G5 than we did before.

• CPU (8 total cores): 1x Arm Cortex-X4 at 3.78 GHz, 5x Arm Cortex-A725 at 3.05 GHz, 2x Arm Cortex-A520 at 2.25 GHz
• GPU: Imagination Technologies PowerVR (DXT-48-1536)

And now on “Day Zero” of the Tensor G6 era, what’s Google saying about it? Predictably, not much beyond another year’s worth of nebulous hand waving in comparison to the Tensor G5:

Tensor G6 features an upgraded CPU for 25% faster web browsing and 15% quicker app launches. Packing 50% more TPU compute and paired with the latest Gemini Nano model, Google Tensor G6 processes on-device AI tasks up to 3.5 times faster while using up to 3.5 times less energy.

But thanks to a leak sourced from embargoed media hands-on time with the Pixel 11 family, the following additional (and more specific) Tensor G6 specs, referencing Arm’s C-series cores, are also presumably accurate.

The Tensor G6 sports a seven-core configuration, with one prime “C1 Ultra” core clocked at 4.1GHz, four performance “C1 Pro” cores clocked at 3.4GHz, and two efficiency “C1 Pro” cores clocked at 2.65GHz. The GPU appears to be a PowerVR C-series variant with six compute units clocked at 1.3GHz.

One other silicon-related nuance also bears mention. Although, as previously mentioned, Google switched from Samsung to TSMC as its foundry source for the Tensor G5 last year, it stuck with Samsung’s Exynos cellular subsystem. This year, reportedly (although I haven’t yet seen definitive confirmation), this too has changed; Google’s supposedly now leveraging MediaTek M90 5G cellular IP.

Smartphone evolutionary modesty

Aside from the new colorways, you’d understandably likely be hard-pressed to discern a visual difference between Google’s latest handsets—the baseline Pixel 11, high-end Pixel 11 Pro and Pro XL, and book-style Pixel 11 Fold—and their 10th generation predecessors. Backs are once again all-glass. Displays are a bit brighter, and more scratch-resistant in the “Pro” variants. Camera bars are a bit more svelte (along with overall Fold thinness), and for “Pro” versions, embed a multicolor notification LED assembly surrounding the flash and branded “HiLight”. Particularly clever readers may have already noted the enhanced scratch-resistance association, since the notifications can only be seen when the phone is screen-down on a flat surface.

That all said, to the overall “supply constraints” theme of this writeup, I’ll point out that the Pixel 11 storage options now start at 256 GBytes; the entry-level 128 GByte variant of the Pixel 10 that I recently acquired isn’t offered this time around. In Google’s defense, Apple did the same thing a year ago with the iPhone 17 versus its iPhone 16 precursor, although in that earlier case the 2x capacity multiplier came for the same intro price as the 128 GByte prior-gen device.

This time the 256 GByte Pixel 11 price thankfully at least matches that of the year-ago 256 GByte Pixel 10, versus with an accompanying price increase as other smartphone suppliers are doing nowadays. Further to Google’s defense, note that a year ago any bill-of-materials cost increases were predominantly due to tariff impacts. Now, in contrast, supply constraints are additionally being felt to fuller effect. It’ll be curious to see how Apple handles both memory and TSMC foundry cost increases at its likely next-month announcement event; for one thing, the company will reportedly delay the launch of its baseline iPhone 18 until sometime next year.

In closing, at least for this section, one more memory-related twist bears mention. A year ago, I wrote, “Google also didn’t “hide” tariff costs by cutting RAM capacities (which would counterbalance its burgeoning AI ambitions, anyway)”. Well, this year they did. The lowest (256 GByte) storage capacity variants of the Pixel 11 Pro and Pro XL also have less RAM—12 GBytes vs 16 GBytes—than both their higher-capacity this-year siblings and same-capacity Pixel 10 predecessors, in the latter case with no accompanying generational price break. Admittedly, Google’s working hard on optimizing memory requirements for its on-device models, but still…

Watches and trackers

Last year’s Pixel Watch 4 was a notable update to its predecessor(s), as I wrote about at the time (although I’m still fiscally quite content with a recent update from my long-in-the-tooth first-generation wearable to “only” the Pixel Watch 3, more discussion of which I’ll save for another post another day). This year’s Pixel Watch 5 advancements are also more modest, notably including slight (~12%) CPU performance and battery capacity upticks along with an on-device AI-intended RAM upgrade from 2 GBytes to 3 GBytes, the latter leading to—you guessed it—an associated $50 price tag increment.

I’m not entirely sure why Google included a set of earbuds in its launch suite promo photo shown earlier this piece, as aside from a new Pixel Buds 2 (two years old) colorway option and pending firmware-delivered feature updates to both them and the Pixel Buds 2a (introduced a year ago), nothing’s new. Conversely, the most brand-new device released this week was the Pixel Tag, unsurprisingly supportive of Google’s Find My Device network and conceptually similar to (and a competitor of) Apple’s also-UWB-enhanced second-generation AirTag.

Hopefully, this wireless-connectivity enhancement suggests that we’ll be seeing broader support for UWB in both Google’s and other Android licensees’ handsets in the future. My biggest surprise here is that, unlike Motorola and other tracker manufacturers, Google didn’t also adopt an AirTag-clone form factor that would enable it to slot into the already sizeable and still steadily expanding AirTag ecosystem of luggage tags, stealth security setups and the like.

That’s what I’ve got for you today, folks. As always, please sound off with your thoughts in the comments!

—Brian Dipert is the associate editor, as well as a contributing editor, at EDN.

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The post Made by Google 2026: This limited silicon-supply situation really sucks appeared first on EDN.

NoMIS Power has developed a 6.5-kV large-die SiC MOSFET that has demonstrated over 8 kV of blocking voltage, 90-mΩ on-resistance, and 55-A drain current. Based on the planar SiC technology used in its 3.3-kV devices, the 6.5-kV MOSFET extends the technology into the high-voltage class and provides a foundation for the company’s planned 10-kV MOSFETs and 20-kV SiC IGBTs.

NoMIS is sampling the 6.5-kV SiC MOSFET to U.S.-based customers, with standard-production devices scheduled for Q4 2026. The company plans to expand the 6.5-kV portfolio with additional on-resistance variants, small-die MOSFETs, hybrid junction-barrier Schottky FETs (JBSFETs), and standalone diodes for applications including HVDC power transmission, solid-state transformers, pulsed-power systems, rail traction, and megawatt-scale EV charging

The 6.5-kV devices build on the company’s 3.3-kV SiC MOSFET family, which is already in production, while 10-kV and higher-voltage MOSFETs, diodes, JBSFETs, and SiC IGBTs are in development.

For more information, visit the NoMIS Power Semiconductors and Modules webpage.

NoMIS Power

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NEO.AI is a memory platform from NEO Semiconductor that overcomes SRAM and DRAM scaling limitations in AI memory systems. As part of the platform launch, NEO Semiconductor is introducing its X-SRAM technology for on-chip memory in GPUs and AI processors and reporting its latest progress on 3D X-DRAM, a high-capacity memory technology for HBM.

By replacing conventional six-transistor SRAM with a two-transistor architecture, X-SRAM enables up to 5 times higher memory density to support 1–2 GB of on-chip memory, according to NEO. The technology maintains SRAM-class performance and is compatible with advanced nanosheet CMOS processes. It also provides a path toward future monolithic 3D X-SRAM implementations.

Built on 3D NAND manufacturing processes, 3D X-DRAM delivers up to 10 times higher memory capacity than conventional DRAM, according to NEO. Successful proof-of-concept validation demonstrates its potential as a scalable and manufacturable solution for next-generation HBM.

For more information, visit the NEO X-SRAM webpage.

NEO Semiconductor 

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The KTS1630 5-A eFuse from Kinetic Technologies protects sensitive electronics against overcurrent, short circuits, and thermal faults. It is designed for consumer and industrial systems operating from 5-V and 12-V power rails, helping improve system safety and reliability. By detecting overcurrent conditions typically within 100 ns, the device can isolate faults before they can damage downstream circuitry.

An integrated MOSFET with a typical on-resistance of 31 mΩ from VIN to VOUT helps reduce conduction losses while supporting operation across a 4.5-V to 18-V input range, with a 20-V absolute maximum rating at VIN. The KTS1630’s adjustable 1-A to 5-A current limit allows designers to set the protection threshold for specific loads rather than relying on a fixed current-limit threshold. The eFuse also includes a dedicated control output for an external reverse-blocking MOSFET that prevents reverse current when the input supply is removed or the output voltage exceeds VIN.

A programmable output slew rate controls inrush current during startup, helping prevent input-supply droop, connector stress, and unintended system resets when large capacitive loads are connected.

Supplied in 10-pin, 3×3-mm VDFN packages, the eFuse is available in both auto-retry and latched-off versions.

KTS1630 product page 

Kinetic Technologies  

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A high-speed USB-to-UART bridge, MaxLinear’s Carmel MxL81434 supports console access and infrastructure management in AI data centers and hyperscale cloud environments. The highly integrated device includes USB 2.0 High-Speed (480 Mbps) connectivity, four independent UART channels operating at up to 15 Mbps each, an I2C master, and 32 GPIOs for server and rack-scale management designs.

Carmel extends MaxLinear’s USB-to-UART portfolio, increasing the maximum UART data rate to 15 Mbps and doubling the transmit and receive FIFO size. The 1024-byte FIFOs help sustain high throughput and reduce host processor overhead, while the integrated I2C master and 32 GPIOs consolidate management, monitoring, and debugging functions. Low-latency console connectivity supports faster system bring-up, recovery, diagnostics, and provisioning.

The USB-to-UART bridge provides ±15-kV HBM ESD protection for demanding server and data center environments.

Samples of the Carmel MxL81434 are expected to be available Q4 2026.

MaxLinear

The post Four-channel USB-UART IC boosts server management appeared first on EDN.

ROHM is offering the RTD-EVK-G2 evaluation kit, based on its second-generation terahertz-wave oscillation device. Built using resonant tunneling diodes (RTDs), the device delivers up to 40 µW of output power, four times that of the first-generation product. The kit enables companies and research institutes to evaluate terahertz-wave oscillation and detection for applications such as nondestructive testing, medical imaging, high-resolution radar sensing, material identification, and high-speed wireless communications.

Unlike conventional terahertz systems, which are costly and require large equipment, the RTD-EVK-G2 includes a sample device, cable, and evaluation board for evaluation in space-constrained settings. The terahertz device maintains the same 0.5×0.5-mm chip size and 4.0×4.3-mm PLCC package as the first-generation component. Compared with other terahertz generation methods, the RTD approach generates less heat and consumes less power.

Sales of the RTD-EVK-G2 kit are scheduled to begin in August 2026 at $3,300 per set. Contact a sales representative or visit the Rohm contact page for more information. Purchase of the evaluation kit requires signing a non-disclosure agreement with Rohm.

Rohm Semiconductor 

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This circuit enables you to generate remote control PWM test signals with a (very) generic (and cheap) chip.

A recent Design Idea illustrated the application of an interesting chip (the LTC6992) to remote control (RC) PWM test signal generation. Being familiar with neither the application nor the chip, and despite being a (very) old dog, I decided to try to learn a new trick or two.  So I took a trip Through the Looking Glass into the LTC6992 datasheet.  Here’s what I found there.

Wow the engineering world with your unique design: Design Ideas Submission Guide

Firstly, the LTC6992 is a very capable and consequently rather complex device.  Inevitably its datasheet is similarly complex and, frankly, more than a little confusing.  Which, of course, might be due to that old dog factor!  But moving along…

Secondly, it’s not inexpensive: ~$6 in singles, plus it needs an external precision regulator that adds another buck.

But worsetly (??? Ed.), it happens that the RC PWM application involves rather low, only 5% to 10%, PWM duty cycle numbers.  When you combine that with the LTC6992 datasheet’s specification (on page 4) of +/-3% typical duty cycle error, it becomes clear the LTC6992 is unlikely to be very happy (or accurate) in this application.

So I decided to work toward a Design Idea that would be more familiar (and friendly?), not needful of (too many) extra external components, (mainly) more accurate, and hopefully a bit cheaper.  Figure 1 shows what my labors achieved.

Figure 1 This Design Idea leverages a LMC555 as a variable duty cycle (1ms to 2ms = 5% to 10%), constant frequency (20ms = 50Hz) PWM oscillator.  Timing is ratiometric and therefore independent of V+ so no external voltage regulator is needed.

How it works is (roughly) sketched in Figure 2’s timing diagrams.

Figure 2 The PWM oscillation cycle alternates between the Threshold pin for the duration of the 1ms to 2ms ON halfcycle is adjusted by R1, and the Trigger pin for the 18ms to 19ms OFF halfcycle. C2 > C1 to compensate for D1 forward drop.

PWM duty cycle = (R2 + R1+)/(R1 + R2 + R3) = 5% to 10%.
Oscillation frequency = 1/(loge(3)C1(R1 + R2 + R3)) = 50Hz independently of R1 setting

D1 recharges C2 during the PWM on interval.  Z1 limits the output amplitude to TTL-safe levels. And given that LMC555s can be had for about a dollar in singles, I’d say the hoped-for price point box was also checked.

Stephen Woodward‘s relationship with EDN’s DI column goes back quite a long way. Over 200 submissions have been accepted since his first contribution back in 1974.  They have included best Design Idea of the year in 1974 and 2001.

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The post Cheap and cheerful LMC555 RC PWM pulse generator appeared first on EDN.

For second-quarter 2026, epitaxial deposition and process equipment maker Veeco Instruments Inc of Plainview, NY, USA has reported revenue of $193.5m, up 22% on $158.3m last quarter and 16.5% on $166.1m a year ago, and exceeding the $170–190m guidance...

The rapid expansion of artificial intelligence is creating an unprecedented demand for computing power, data centres, advanced networking, electricity and high-performance chips. However, the enormous capital required to build AI infrastructure has become a major challenge for AI companies and cloud providers. Addressing this funding gap, NVIDIA has announced partnerships with major global investment firms to establish independent financing platforms designed to mobilise more than $500 billion in third-party capital for AI infrastructure over time.

The initiative brings together NVIDIA with Apollo Global Management, BlackRock, Blackstone, Brookfield, Goldman Sachs and KKR. Rather than NVIDIA providing the entire $500 billion itself, the initiative is designed to attract capital from institutional investors through dedicated financing platforms. The capital can then support the development and deployment of AI computing infrastructure, including GPUs, servers, data centres, networking systems and related power infrastructure.

The chipmaker on 10 August announced partnerships with Apollo, BlackRock, Blackstone, Brookfield, Goldman Sachs and KKR to create independent financing platforms for AI compute infrastructure. The platforms are expected to mobilise more than $500 billion in third-party capital over time for the development of AI infrastructure.

Nevertheless, the NVIDIA’s collaboration marks a landmark step in the financing of AI infrastructure. By mobilizing as much as $500 billion from third-party sources, the firm and financial partners intend to accelerate the build-out of infrastructure for the next iteration of AI innovation. The effort could fundamentally reposition the notion of AI compute from a technologically motivated expenditure into a substantial asset class with unprecedented interconnectivity between semiconductor design, data centres, power and institutional capital.

The post NVIDIA Mobilises $500 Billion for Next-Generation AI Infrastructure appeared first on ELE Times.

Photonic application-specific integrated circuit (PASIC) chip designer and manufacturer OpenLight of Goleta, Santa Barbara, CA, USA (which launched as an independent company in 2022, introducing the first open silicon photonics platform with heterogeneously integrated III-V lasers, modulators, amplifiers and detectors) and specialty analog foundry Tower Semiconductor Ltd of Migdal Haemek, Israel have announced the availability of OpenLight’s photonic process design kit (PDK) for Tower’s PH18DA indium phosphide (InP)-on-silicon photonics platform in Cadence’s electronic design automation (EDA) tools...

AI has transformed the semiconductor industry’s pressure points. The conversation is no longer focused solely on designing faster chips. Instead, manufacturers are racing to ensure every part of the supply chain—from silicon wafer production to advanced packaging to global logistics—can support an unprecedented wave of demand.

This shift means evaluating more than process nodes and transistor density. For electronics engineers, supply chain resilience, packaging availability, and manufacturing capacity increasingly influence component selection, product schedules, and long-term design decisions.

AI changing wafer demand

The scale of that demand became clear in the second quarter of 2026, when global silicon wafer shipments reached a record 3,573 million square inches, up 7.4% year over year. AI servers, high-bandwidth memory (HBM), advanced logic, automotive electronics, and industrial semiconductors are all contributing to this wafer demand.

The current cycle differs significantly from previous semiconductor rebounds. After demand being shifted from smartphones or PCs, AI infrastructure is driving simultaneous growth across advanced logic, memory, and power devices.

According to SEMI, AI infrastructure continues to drive demand for leading-edge logic and memory devices, while the rapid expansion of hyperscale data centers is also increasing demand for power management ICs. As industrial markets recover and inventory levels normalize, semiconductor demand is becoming more balanced across multiple end-use sectors.

The impact extends well beyond cloud infrastructure. Consumer devices, such as smartphones and tablets, continue relying on advanced logic and memory, while automotive electronics for ADAS controllers, battery management systems, and zonal computing platforms are consuming larger volumes of semiconductors. Networking switches, 5G base stations, industrial PLCs and robotics controllers are also increasing silicon content, sustaining demand across multiple process nodes rather than only the most advanced technologies.

The broader demand profile has made supply planning more complex for design engineers. While AI accelerators rely on advanced process nodes, many supporting components—including power management ICs (PMICs), microcontrollers (MCUs), connectivity chips, and analog devices—continue to be manufactured on mature nodes. Modern electronic systems depend on both, making balanced capacity expansion critical across the semiconductor ecosystem.

300 mm fabs remain a priority

Silicon remains the primary raw material for manufacturing chips. After being refined into wafers, its electrical properties can be precisely engineered through controlled doping, making it the foundation of the transistors used in AI processors, memory devices, automotive electronics, and countless other semiconductor applications.

The semiconductor industry’s expansion continues to center on 300-mm wafer production because larger wafers enable manufacturers to produce more chips per fabrication cycle, improving throughput and reducing the cost per die. Those efficiencies make 300-mm fabs the preferred choice for advanced logic, memory, and other high-volume semiconductor devices.

That strategy is evident from the recent investments. GlobalWafers is preparing the next phase of expansion at its advanced 300-mm wafer facility in Sherman, Texas, in response to growing customer demand for domestically produced silicon wafers. The plant is the first advanced 300-mm silicon wafer facility built in the United States in over two decades, underscoring broader efforts to strengthen domestic semiconductor supply chains.

Simultaneously, foundries such as TSMC continue expanding advanced fabrication capacity to support AI processors, high-performance computing, and automotive semiconductor demand, highlighting the industry’s broader push to scale leading-edge manufacturing.

For electronics engineers, continued investment in 300-mm manufacturing should improve long-term wafer availability. However, securing leading-edge devices will also increasingly depend on how quickly packaging, testing, and logistics infrastructure expand alongside wafer production.

Logistics becoming the next constraint

Higher wafer output does not automatically translate into higher semiconductor availability. Modern semiconductor manufacturing depends on tightly synchronized movement of raw wafers, specialty gases, ultrapure chemicals, photomasks, lithography equipment, and finished devices across multiple continents. A disruption affecting any stage can slow production despite available fab capacity.

Transportation also introduces reliability challenges. Vibration during shipping can generate electrostatic charge through tribocharging, increasing the risk of electrostatic discharge (ESD) for sensitive semiconductor components if they are not properly protected. As wafer volumes continue rising, ESD-safe packaging and handling become increasingly important to ensure that devices arrive ready for assembly and deployment.

Advanced packaging has become another pressure point. AI processors increasingly rely on chiplets, 2.5D integration, HBM stacks, and sophisticated substrate technologies. Even if wafer fabrication keeps pace, shortages in packaging capacity or substrate availability can delay final product shipments.

Engineers designing products with leading-edge processors should evaluate supply chains beyond wafer availability. Long lead times for advanced substrates or packaging services can delay board assembly completion, even when silicon is available. As a result, packaging partners, OSAT capacity, substrate suppliers, and logistics resilience have become critical considerations alongside device specifications and performance.

Building resilience in future designs

Recent supply chain disruptions have encouraged semiconductor manufacturers to diversify production geographically while increasing regional investments in wafer fabrication, materials, and packaging. Government-backed semiconductor initiatives across North America, Europe, and Asia are helping expand domestic manufacturing ecosystems. These efforts reduce dependence on single-region supply chains while improving resilience against geopolitical and transportation risks.

The implications extend into product architecture. Selecting components with multiple qualified manufacturing sources and maintaining flexibility across process nodes can reduce exposure to future capacity constraints.

The record wafer shipment figures suggest upstream silicon availability is improving. However, transforming those wafers into finished electronic systems increasingly depends on synchronized investments across fabrication, advanced packaging, materials handling, and global logistics.

Keeping pace with growing AI demand will require more than expanding silicon wafer manufacturing. Engineers must also account for packaging capacity, logistics resilience, and supplier readiness throughout the design process.

Emily Newton is editor-in-chief of revolutionized.com.

 

 

 

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• Will 2024 be the year of advanced packaging?
• Wafer supply deals herald the upcoming SiC boom
• One-stop advanced packaging solutions for chiplets

The post Record high wafer shipments. Can fabs keep pace? appeared first on EDN.

L&T Technology Services, a global leader in Engineering Intelligence Solutions & ER&D Consulting Services, today announced the launch of AgenticIQ, an end-to-end Agentic AI platform purpose-built for engineering and manufacturing organizations. Designed to help enterprises move beyond isolated AI pilots, AgenticIQ enables autonomous, multi-agent workflows across engineering, product development, manufacturing, industrial operations and customer experience, accelerating the adoption of Engineering Intelligence at scale.

As enterprises increase investments in AI, many initiatives continue to struggle to move beyond proof-of-concepts into production. Disconnected engineering systems, manual processes and highly regulated environments often prevent organizations from scaling autonomous AI while maintaining governance, security and operational reliability.

Built on LTTS’ portfolio of Engineering Intelligence solutions, AgenticIQ transforms proven engineering capabilities into specialized, reusable AI agents through a planning-first architecture that is embedded directly into engineering and production workflows and designed to operate within enterprise governance boundaries. The platform helps safeguard critical data, intellectual property and regulatory compliance while laying the foundation for LTTS’ next-generation Engineering Intelligence solutions and an Agentic-led engineering delivery model, enabling faster development and deployment of AI-powered solutions.

Designed for customer-centric engineering and R&D-intensive environments, AgenticIQ supports industries including automotive, industrial manufacturing, medical devices and healthcare, semiconductor, plant engineering and high-tech. Its cloud-agnostic architecture enables organizations to build once and deploy anywhere across cloud and on-premises environments, helping enterprises scale trusted AI while retaining control of proprietary engineering knowledge, workflows and intellectual property.

Amit Chadha, Chief Executive Officer & Managing Director, L&T Technology Services, said, “The next phase of Engineering Intelligence will be defined by how effectively autonomous AI agents collaborate to solve complex industry challenges across engineering, production and customer experience. Over the years, LTTS has built AI-powered engineering solutions that address domain-specific business problems across industries. With AgenticIQ, we are transforming these proven capabilities into reusable AI agents on a unified Agentic AI platform that enables enterprises to rapidly build, orchestrate and deploy next-generation agentic solutions at scale.”

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ASMPT, the world’s leading provider of integrated hardware and software solutions for semiconductor and electronics manufacturing, today announced that Bassel Haddad has assumed the roles of Group Chief Executive Officer and Executive Director. The leadership transition, first announced in July, took effect today. Bassel Haddad succeeds Robin Ng, who retires after more than 20 years with ASMPT, including six years as Group CEO and Executive Director.

John Lok, Chairman of the Board of ASMPT, said: “We are pleased to welcome Bassel Haddad as Group CEO. He assumes leadership of ASMPT with a clear corporate strategy, strong technology capabilities and an experienced global team already in place. Bassel’s deep industry expertise, business leadership and track record of driving innovation and customer success make him the right leader to guide ASMPT through its next phase of growth and deliver solutions to increasingly complex customer requirements.”

“It is an honour to lead ASMPT, a company with a remarkable legacy and a strong foundation for future growth,” said Bassel Haddad, Group Chief Executive Officer of ASMPT. “We have an exceptional opportunity to accelerate and shape the industry’s evolution from traditional Moore´s Law scaling to the “more than Moore” era. I look forward to partnering with the Board of Directors and our talented global team to accelerate innovation, deepen our customer partnerships, and create lasting value for our employees, customers, and shareholders.”

As semiconductor architectures become more complex, assembly and advanced packaging have become central to delivering system-level performance and manufacturing scalability. Bassel Haddad’s broad experience leading technology development, operations and global businesses positions ASMPT to extend its technology leadership and customer focus.

Bassel Haddad assumes leadership following ASMPT’s recently reported first-half 2026 results. Group revenue from continuing operations increased 42.5% year on year to US$1.14 billion, while Advanced Packaging delivered record half-year revenue. The performance reflected demand across multiple advanced packaging solutions, including Thermo-Compression Bonding, high-precision SMT and Photonics, alongside growth in mainstream applications.

Before joining ASMPT, Bassel Haddad was Senior Vice President and General Manager of Foundry Solutions and Technology Platforms at SkyWater Technology, where he led business strategy, go-to-market activities and profit-and-loss accountability for its foundry and advanced technology services. He previously led SkyWater’s Advanced Packaging business, with responsibility spanning technology development, engineering, marketing and fab operations. Earlier, Bassel spent 14 years at Intel Corporation in senior leadership roles across product, technology and business management, including edge computing, artificial intelligence and product architecture. He holds bachelor’s and master’s degrees in electrical engineering from the Technion – Israel Institute of Technology.

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The MXO Series oscilloscopes from Rohde & Schwarz are now supported by Chroma’s Power Conversion Device Automated Test System Model 8000 (ATS 8000). This integration helps address increasingly complex testing requirements in high-power and high-channel-count applications, including power systems used in AI data center infrastructure. As a result, power electronics engineers using the ATS 8000 platform for automated testing and integration can benefit from the advanced capabilities of next-generation MXO oscilloscopes for real-time waveform capture.

The growth of AI infrastructure is driving power demand in data centers and related systems. This is pushing power supply vendors to develop higher-power and higher-density designs, including systems built for the latest HVDC (High-Voltage Direct Current) power architectures. Engineers power conversion devices and power supplies rely on automated test platforms such as Chroma’s ATS 8000 to carry out automated tasks including waveform capture, debugging and calibration during power system development.

The ATS 8000 is designed for automated testing of various power conversion devices and power supplies. Chroma has now added support for the MXO Series digital oscilloscopes from Rohde & Schwarz as one of several available hardware options that can be integrated into the system. In automated power testing applications, oscilloscopes play a critical role in capturing transient behavior and dynamic waveforms in real time.

High accuracy for high-voltage testing environments

Based on MXO-EP processing ASIC technology developed by Rohde & Schwarz, the next-generation MXO Series offers waveform capture rates of up to 4.5 million acquisitions per second. This helps reduce measurement blind spots and provides a more accurate real-time representation of the signal behavior. With advanced digital triggering, adjustable sensitivity and exceptionally low trigger jitter, the MXO can detect even very small signal anomalies with pixel-level trigger accuracy. In HD mode, the oscilloscopes support up to 18-bit resolution and input sensitivity as low as 0.5 mV/div.

High channel count for high-density power delivery

To meet the power demands of high-density power delivery in AI-driven data centers, a single power rack often needs to support multiple power modules, as well as battery backup units (BBU) and capacitor backup units (CBU) in series or parallel  setups. These requirements can create complex measurement challenges involving more than eight channels. The MXO Series includes models with up to eight channels and supports multi-instrument synchronization through the Rohde & Schwarz ScopeSync architecture, allowing several instruments to operate in a primary-secondary setup with up to 24 synchronized channels. This capability supports debugging work and helps align manual checks with automated test results.

Flexible test platform for real-world applications and production line environments

Thanks to Chroma’s PowerPro 5 control software, engineers can adapt the test systems to specific use cases and run external programs written in C# or Python as part of the test flow. This makes it possible to add custom analysis steps, such as decoding control frames from serial communication buses or applying product-specific calibration routines, meeting engineers’ flexibility requirements in both real-world applications and production-line environments.

Evan Tsai, Product Manager for ATS 8000 Software Solutions from Chroma said: “Drawing on many years of experience in automated testing, we consider efficiency and flexibility to be extremely important in the AI-driven era. The addition of support for the Rohde & Schwarz MXO Series oscilloscopes expands the ATS 8000 platform in response to new demands in advanced power testing. Looking ahead, Chroma will continue to develop automated testing technologies that provide power supply manufacturers worldwide with more comprehensive, precise and reliable measurement solutions, jointly paving the way for highly efficient AI-driven energy systems.”

Jithu Abraham, Director Product Management Oscilloscopes at Rohde & Schwarz said: “Power electronics engineers developing complex power systems used in AI data center infrastructure need measurement tools that can capture fast signal behavior and support complex multi-channel setups. By adding our MXO Series to Chroma’s well-established ATS 8000 platform, these users can now access next-generation oscilloscope technology within their existing automated test workflows.”

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Soctera of Ithaca, NY USA has closed a $4m in seed funding round backed by Anorak Ventures and Multiball Capital, with additional participation from 9Yards Capital, Mana Ventures, and Red Bear Ventures. The firm will use the funding to develop its thermally optimized III-nitride millimeter-wave power amplifiers...

Analog and mixed-signal design at sub-5 nm nodes has reached a threshold where deterministic corner-based signoff and brute-force Monte Carlo can no longer simultaneously satisfy convergence speed, tail-yield condense, and engineering interpretability.

This paper examines QUINSIM’s Analog Uncertainty-Aware Design (AUAD) platform—a physics-informed, surrogate-driven uncertainty quantification engine that wraps existing SPICE and TCAD simulators as black boxes.

We characterize the mathematical architecture (sparse polynomial chaos expansion, R-Vine copula process modeling, Sobol variance decomposition, and efficient global optimization), quantify performance across six canonical analog verification benchmarks (SRAM, LNA/VCO, SAR ADC, automotive power IC, TCAD/GAA nanosheet, and timing closure), and analyze the structural transformation AUAD imposes on analog design economics, organizational workflows, and EDA ecosystem dynamics.

We conclude that AUAD is not an incremental acceleration of existing flows; it constitutes a new design epistemology in which uncertainty is a first-class object—characterized, propagated, decomposed, and optimized—rather than a late-cycle verification penalty.

Analog variability crisis at advanced nodes

Analog and mixed-signal design at sub-5 nm nodes has entered a regime where the statistical toolkit inherited from the 1990s—Gaussian corner models and brute-force Monte Carlo—can no longer simultaneously satisfy industrial signoff requirements. Three overlapping crises converge: non-Gaussian process physics, exponentially expensive tail convergence, and opacity of failure attribution. Together they constitute the analog variability crisis, a condition in which the standard toolkit cannot adequately address tail-yield confidence at acceptable engineering cost.

The physics of non-Gaussian variation

Classical statistical IC design rests on a Gaussian assumption inherited from diffusion-dominated transistor physics of the 1980s. In that regime, bulk MOSFET threshold voltage Vth was well-approximated as normally distributed, making a standard deviation σ extracted from wafer data a sufficient design lever. At sub-10 nm nodes, this approximation breaks down for fundamental physical reasons.

Random discrete dopant (RDD) fluctuations produce heavy-tailed, skewed Vth distributions whose kurtosis significantly exceeds the Gaussian value of three. Line-edge roughness (LER) in EUV-patterned FinFET fins creates systematic spatial correlations between adjacent devices that no single-transistor Gaussian model can express. FDSOI back-gate coupling creates strong nonlinear co-dependence between Vth and DVT0W parameters that Gaussian copulas severely underestimate.

The consequence is stark: every PDK σ value that rests on a Gaussian marginal is a physically incorrect model for the circuit’s actual failure space. Corner models compound the problem by treating process parameters as independently varying—an assumption falsified by the correlated etch and deposition physics of modern advanced nodes. A corner labeled “SS” (slow-slow) is a specification convenience, not a probabilistic claim about the failure boundary.

The convergence economics of deep-tail analysis

Monte Carlo convergence follows the 1/√ N law: to halve the estimation error on a yield metric, four times as many simulations are required. For SRAM static noise margin (SNM) qualification at 5σ—the product-level target for leading-edge memory—direct Monte Carlo requires on the order of 107 SPICE evaluations.

At a conservative 3 seconds per simulation on modern hardware, this translates to approximately 347 days of wall-clock compute per circuit per operating corner. Modern SRAM products span multiple corners, temperatures, and supply voltages, multiplying this burden by a factor of 10–50.

The attribution gap

Perhaps the least-discussed failure of conventional flows is epistemic. Monte Carlo can answer “what is the yield?” but not “which parameters are responsible, and by how much?” Answering the latter requires a highly-designed factorial experiment or auxiliary regression—both expensive and approximate.

In a 57-parameter FinFET PDK, attributing yield loss to a specific root cause without attributing yield loss to a specific root cause without analytical sensitivity tools means teams spend weeks on iterative knob-turning that is effectively uninformed trial and error.

This attribution gap directly inflates design cycle time. When the nominal design fails Monte Carlo signoff without variance decomposition, the team must rely on engineering intuition and costly re-simulation campaigns to identify root causes—a process that can consume months at advanced nodes.

Figure 1 In simulation budget comparison, see QUINSIM sPCE (~350 calls) vs. direct Monte Carlo (~10,000 shown; 107 for full 5σ) for a 57-parameter 5 nm FinFET SRAM SNM characterization. Source: QUINSIM

Why corners cannot patch the gap

For uncorrelated Gaussian parameters, an SS corner is geometrically remote from the actual 6σ failure hyperplane in a high-dimensional parameter space. For non-Gaussian parameters with nonlinear correlations, the SS corner may not even represent the worst-case direction—the actual failure mode may lie in a cross-parameter interaction that no PVT corner captures.

AUAD: Architecture and mathematical foundations

QUINSIM’s Analog Uncertainty-Aware Design platform is structured as a four-stage pipeline that treats the existing SPICE or TCAD simulator as an opaque black box—preserving compatibility with Cadence Spectre, Synopsys HSPICE, Mentor Eldo, and Synopsys Sentaurus without modification. As shown in Figure 2, uncertainty inputs are characterized from foundry data; adaptive sampling builds a sparse surrogate; sensitivity and yield surfaces are extracted analytically; and robust optimization acts directly on the uncertainty-aware objective.

Figure 2 In AUAD four-stage pipeline, each stage is analytically connected to the next: foundry data flows through copula characterization into sPCE training, then into zero-cost Sobol decomposition, and finally into EGO-based robust optimization—all without a single additional SPICE call beyond the initial adaptive sample set. Source: QUINSIM

Stage 1: Non-Gaussian joint distribution characterization

Real foundry measurement data for parameters such as Vth, Tox, Leff, and inter-device mismatch do not conform to Gaussian distributions. QUINSIM fits marginals using non-parametric kernel density estimation (KDE) or parametric heavy-tail distributions (Student-t, skew-normal). Joint dependence between parameters is captured using R-vine copulas—pair-copula constructions that model arbitrary bivariate relationships in a recursive tree structure, capturing nonlinear co-dependence that Gaussian or elliptical copulas systematically miss.

The Rosenblatt transformation maps correlated, non-Gaussian samples into independent uniform (then Gaussian) space where Polynomial Chaos Expansion is analytically valid. This is the technical key that makes sPCE applicable to real foundry data with correlated, non-Gaussian parameters, a capability absent from conventional Gaussian-input PCE tools.

Stage 2: Sparse polynomial chaos expansion surrogate

The circuit performance metric Y (SNM, ENOB, NF, efficiency…) is approximated as a polynomial functional of standardised process inputs Z:

Physical sparsity—circuits respond strongly to a small subset of parameters even in 50+ dimensional PDK spaces—combined with active-learning sample placement concentrates 100–500 simulator calls in the regions that maximally reduce surrogate error. The trained surrogate then evaluates in microseconds, enabling post-hoc Monte Carlo with 106–108 samples at negligible additional cost.

Stage 3: Analytical Sobol sensitivity and yield surface extraction

Global sensitivity indices—Sobol first-order and total-effect—are computed analytically from the PCE coefficients at zero additional simulation cost:

Figure 3 Example Sobol-derived metric importance ranking across six performance dimensions (efficiency, output swing, peak current, power factor, THD, EMI) for a power converter design. PF and Eff dominate the variance budget, immediately directing robust design effort to the parameters that matter most. The ranking costs zero additional simulations. Source: QUINSIM

Stage 4: Efficient global optimization (EGO)

With the surrogate trained and sensitivity indices computed, QUINSIM applies efficient global optimization (EGO) to maximize yield over the design parameter space. EGO uses a Kriging (Gaussian process) meta-model of the yield surface together with an expected improvement (EI) acquisition function: EI(x) = E[max(f(x) − f*, 0)]. This Bayesian optimization approach locates yield-maximizing design parameters in fewer than 200 evaluations for 50+ dimensional spaces—unachievable with classical gradient-based methods when the yield surface is non-convex or multimodal.

Benchmark use cases: Demonstrating AUAD impact

QUINSIM has constructed six canonical AUAD benchmarks spanning memory, RF, data conversion, automotive power electronics, and device-level TCAD calibration. These demonstrators collectively define the platform’s technical scope and establish its performance claims against reference instances from published literature and ICCAD benchmarks.

Figure 4 In this 6T SRAM bit-cell schematic at 5-nm FinFET, static noise margin (SNM) and write-margin jointly depend on all six transistors’ Vth, Tox, Leff, and mismatch. QUINSIM’s sPCE characterizes the full 5σ SNM failure surface from 350 adaptive Spectre calls, versus 107 for direct Monte Carlo. Source: QUINSIM

SRAM bit-cell: 5σ SNM in 350 simulations

The canonical AUAD challenge is SNM qualification for 5 nm 6T/8T SRAM. QUINSIM constructs a 57 parameter sPCE surrogate using 350 adaptive Spectre calls, recovers the full SNM probability density function including the 5σ tail, identifies three dominant failure drivers analytically (Tox, Vth_PMOS, Leff), and completes in under 4 hours on standard workstation hardware. The Sobol decomposition reveals Tox alone accounts for 38% of SNM variance—enabling targeted process control recommendations to the foundry that would be invisible to any Monte Carlo approach.

RF LNA/VCO: Capturing bimodal failure distributions

In 28/22 nm FDSOI, QUINSIM employs a Student-t copula to model the Vth–DVT0W co-dependence from back-gate coupling. The result is accurate prediction of a bimodal noise-figure distribution—an artifact of nonlinear coupling that Gaussian-assumption tools miss entirely. QUINSIMʼs design centering identifies a 15% yield improvement and locates the real 6σ worst-case operating point. Multimodal output distributions imply correlated input failure modes that only copula-based process models can resolve.

Figure 5 In FDSOI LNA and the resulting bimodal noise-figure distribution, the back-gate voltage VBG creates nonlinear Vth–DVT0W dependence. QUINSIM’s Student-t copula reveals a second failure mode (Mode 2) that a Gaussian process model misses, a production-impact failure invisible to conventional statistical signoff. Source: QUINSIM

High-speed SAR ADC: 150-parameter ENOB characterization

ENOB degradation in a SAR ADC arises from a correlated combination of capacitor mismatch, comparator offset, jitter, and reference noise. QUINSIMʼs structured high-dimensional sPCE handles 150 correlated parameters from 600 adaptive simulations, delivering the full ENOB probability density function and per-specification tail failure probability in 8 hours.

An equivalent Monte Carlo campaign spanning this 150-parameter space to 6σ confidence would require 3–4 weeks. The surrogate’s full distributional output also exposes ENOB distribution shape—skew, kurtosis, multi-mode structure—that pass/fail counting cannot reveal.

Automotive power IC: Joint process-temperature surrogates

Automotive-grade ICs (AEC-Q100 Grade 0) must operate from −40°C to +175°C. QUINSIM extends the uncertain parameter space to treat temperature as a continuous uncertain dimension, building joint process-temperature surrogates that deliver 100× cost reduction relative to a conventional Monte Carlo × PVT sweep. This is particularly relevant for SiC power stages, gate drivers, current sensors, and high voltage control loops, where tail-yield and reliability must be jointly evaluated across the full operating envelope, not at isolated corners.

TCAD/GAA nanosheet: Bayesian process calibration in 48 hours

TCAD calibration for a new process node currently requires 2–4 weeks of manual deterministic iteration to fit compact model parameters (BSIM-CMG, PSP) to measured I-V characteristics. QUINSIMʼs Bayesian calibration engine applies active learning to TCAD simulation scheduling, fits a posterior distribution over the full set of physical model parameters rather than a point estimate, and propagates that posterior uncertainty through the compact model extraction chain into a UQ-aware PDK (UQ-PDK). The result: 48-hour calibration cycles with honest uncertainty bounds on every PDK parameter.

Capabilities unlocked by AUAD

Beyond benchmark-level performance numbers, AUAD unlocks capabilities that are qualitatively unavailable within the Monte Carlo paradigm regardless of the compute budget applied.

Analytical variance budget decomposition

For a 57-parameter PDK space, conventional Monte Carlo can determine that yield is 97.2%—but not which parameters explain the 2.8% failure variance. QUINSIMʼs Sobol decomposition provides a ranked list of first-order and total-effect indices for every process parameter, computed analytically from sPCE coefficients at zero simulation cost. This transforms failure analysis from “simulate more” to “fix these three parameters in this priority order.”

Full probability density output instead of pass/fail counting

Surrogate-based UQ produces the full PDF of any circuit metric as a live design object. For a SAR ADC, this means designers see not just “mean ENOB = 11.2 bits, σ = 0.15 bits” but the complete distributional shape—whether it’s symmetric, heavy-tailed, or bimodal. This changes specification verification from a Gaussian-approximation exercise to a physics-honest probability assessment.

Robust design centering and optimization via EGO

EGO-based robust optimization acts on the yield surface, not the nominal performance surface. A design point that is optimal in nominal performance may sit on a steep yield cliff; a slightly sub-optimal nominal design may command a wide, flat yield basin. AUAD makes this trade-off visible and optimizable: in the FDSOI LNA benchmark, EGO-guided centering recovered 15% yield improvement that was invisible to nominal optimization. In timing-closure benchmarks, robust optimization produced higher shipping frequency with tighter but better-justified margins than guard-banding.

Partner-ready traceability and auditability

QUINSIMʼs analytical UQ framework produces structured, reproducible outputs: specific PCE coefficients, Sobol index tables, yield surface plots, failure-mode rankings—all derived from a documented mathematical procedure. For foundry partnerships, IP qualification packages, and AEC-Q100 automotive compliance dossiers, auditability of the statistical analysis is increasingly a contractual requirement. AUADʼs analytical traceability directly satisfies this requirement in a way that a random-seed-dependent Monte Carlo run cannot.

The irreversible transformation of analog IC design

AUAD is not a feature addition to existing EDA flows. It constitutes a structural transformation of how analog design decisions are made, justified, and communicated. Once a design team inhabits an environment where uncertainty is analytically characterized and continuously actionable, the prior workflow—simulate, margin, and iterate—becomes evidently inferior and institutionally difficult to defend.

From “simulate and margin” to “characterize, rank, optimize, explain”

The existing design-verification loop treats Monte Carlo as a late-stage checksum applied after nominal design completion. When the gate fails, the team iterates blindly without analytical guidance. In an AUAD workflow, the uncertainty model is active from the first design iteration: parameters are characterized from foundry data, the surrogate is trained after 100–500 simulation calls, and Sobol rankings immediately direct design effort. The loop compresses from months to days not because the simulator runs faster, but because engineering judgment is guided by quantitative attribution rather than intuition.

Figure 6 In traditional simulation-centric design loop (red) vs. AUAD design loop (blue/green), the structural difference is that AUAD delivers actionable attribution at every stage. Where the traditional loop requires months of blind re-simulation on signoff failure, AUAD’s Sobol-guided EGO reaches tape-out readiness in days. Source: QUINSIM

Economic consequences for design organizations

The commercial implications of a 1000× simulation reduction extend beyond throughput. Fewer SPICE simulations mean fewer licensed EDA seat-hours consumed, directly reducing the variable cost of advanced-node verification.

Faster yield diagnosis compresses design cycles currently measured in 18-24 months for leading-edge analog. Better yield prediction reduces unnecessary margin padding, and in volume production, even 1–2% yield recovery at advanced nodes translates to tens of millions of dollars in recaptured wafer value per year. QUINSIM positions these not as incremental improvements but as step-function changes in the economics of analog design.

EDA ecosystem dynamics: The intelligence layer

QUINSIMʼs black-box simulator wrapper positions it as an intelligence layer on top of, not in competition with, the SPICE simulation cores of Cadence, Synopsys, and Siemens EDA. Incumbents can embed the UQ engine as a differentiated variation-analysis module without displacing their core circuit simulation products. The roadmap QUINSIM publishes explicitly names a “Cloud SaaS, UQ-PDK marketplace” and positions the platform as an acquisition target in the €100–200M range—a signal of deliberate ecosystem positioning rather than standalone scaling.

Foundries and IP providers face an analogous opportunity. A UQ-PDK that exposes calibrated non-Gaussian marginals, copula dependence models, and Bayesian parameter posteriors is qualitatively richer than a conventional σ-table, enabling customers to achieve better first-silicon yield with fewer iterations—a tangible competitive differentiator in a market where design starts are competed on tool quality.

The transformation is irreversible

The historical pattern in EDA adoption suggests that once a design team experiences analytical yield attribution—knowing which parameters are responsible for yield loss and by how much, derivable in hours—returning to uninformed Monte Carlo iteration is institutionally unacceptable. The same dynamic played out when formal verification replaced simulation-only digital signoff, and when place-and-route tools supplanted manual floorplanning.

AUAD represents the analog equivalent of that transition: a shift from a compute-intensive empirical paradigm to a mathematically structured, interpretable, and continuously optimizable uncertainty framework.

The chips shipping in 2029 and beyond will be designed by teams who characterize, rank, optimize, and explain the uncertainty in their analog blocks from the first simulation run. Those teams will converge faster, yield higher, and signoff with tail-probability confidence that today’s Monte Carlo paradigm can not match. QUINSIM AUAD is the platform enabling this transition today.

Christophe Bianchi is CEO and founder of QUINSIM.

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