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Editor’s Note: This Design Idea (DI) offers another alternative to the “To press ON or hold OFF? This does both for AC voltages” that was originally inspired by Nick Cornford’s DI: “To press ON or hold OFF? This does both.”

Figure 1 gives a simple circuit for the PUSH ON, PUSH OFF function with only a few inexpensive components. In this design, the output is connected to the input of the gadget when you press the push button (PB) once. For the next push, the output is disconnected.

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This is an attractive alternative to bulkier ON/OFF switches for DC circuits. The circuit has a fairly simple explanation. U1 is a counter.

Figure 1 A Flip ON Flop OFF circuit for DC voltages. The gadget is connected to the output terminals of the PB. With an adequate heat sink for MOSFET Q1, the output current can go up to 50 A.

During power on, R2/C2 resets the counter to zero. When you push PB momentarily once, a pulse is generated and shaped by a Schmidt trigger inverter U2 (A & C), which counter U1 counts. Hence, the LSB (Q1) output of U1 becomes HIGH, making MOSFET Q1 conduct. At this point, the output gets the input DC voltage.

When you push PB momentarily again, another pulse is generated and counted by U1. Hence, its LSB (Q1) output goes LOW and MOSFET Q1 stops conducting and output is disconnected from input. This action continues, making output ON and OFF for each push of PB.

Jayapal Ramalingam has over three decades of experience in designing electronics systems for power & process industries and is presently a freelance automation consultant.

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To advance its growth strategy, gallium nitride (GaN) power IC and silicon carbide (SiC) technology firm Navitas Semiconductor Corp of Torrance, CA, USA has announced corporate governance enhancements that are said to reflect the board of directors’ ongoing commitment to stockholder engagement and value creation for stakeholders...

FPGA-based prototyping solutions provider S2C has teamed up with RISC-V processor IP supplier Andes Technology to enhance prototyping capabilities for system-on-chip (SoC) designs. This collaboration aims to bolster capacity and flexibility for modeling, prototyping, and software development work carried out around Andes’ RISC-V cores.

The partnership is built around S2C’s recently launched Prodigy S8-100 FPGA prototyping platform, which is based on AMD’s Versal Premium VP1902 adaptive SoC. “Versal Premium VP1902 adaptive SoC is the industry’s largest FPGA-based adaptive SoC,” said Mike Rather, senior product line manager at AMD. “That empowers engineers to push the boundaries of technology.”

Figure 1 The VP1902 adaptive SoC bolsters prototyping platform’s capacity with a larger FPGA. Source: AMD

Capacity limitations are a common challenge in FPGA prototyping, which restricts SoC developers’ ability to integrate multiple RISC-V cores along with subsystems like network-on-chip (NoC), DDR, PCIe controllers, and more. Prodigy S8-100 prototyping addresses these challenges by offering a single FPGA version with up to 100 million logic gates.

“The large-capacity FPGA-based prototyping allows early customizations, ultimately accelerating their time-to-market with Andes-based RISC-V SoCs,” said Emerson Hsiao, president of Andes Technology USA.

Figure 2 The new FPGA prototyping platform further boosts capacity with larger configurations. Source: S2C

As shown in the above figure, Prodigy S8-100 also includes larger configurations with two or even four VP1902 adaptive SoCs, which scales capacity to up to 400 million logic gates per system. That enables full SoC validation in hardware, significantly reducing development cycles, optimizing performance modeling, and accelerating software development before production silicon becomes available.

Next, the new prototyping platform encompasses S2C’s extensive library of nearly 100 daughter cards, which support applications ranging from networking, storage, and multimedia to generic IOs. This facilitates efficient interface modeling and simulation without sacrificing FPGA logic resources.

S2C’s new FPGA prototyping platform will be demonstrated live at the Andes RISC-V Con, which will be held on April 29, 2025, at the DoubleTree by Hilton Hotel in San Jose, California.

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Стипендії від компанії "ІКНЕТ" для студентів ФЕА Інформація КП пт, 04/25/2025 - 10:00

SiCPAK power modules from Navitas use advanced epoxy-resin potting to achieve 5× lower thermal resistance shift for extended system lifetime. Based on trench-assisted planar SiC MOSFETs, the modules deliver efficient high-temperature performance for EV DC fast chargers, solar inverters, industrial motor drives, energy storage systems, and uninterruptible power supplies.

The 1200-V SiCPAKs are designed to resist high humidity and prevent moisture ingress, maintaining stable thermal performance under power and temperature cycling. In thermal shock testing (–40°C to +125°C, 1000 cycles), the modules showed a 5× smaller increase in thermal resistance compared to those with silicone-gel potting. Additionally, while silicone-gel modules failed isolation tests, the epoxy-resin potted SiCPAKs retained acceptable isolation levels.

Featuring built-in NTC thermistors, the 1200-V power modules are offered with on-resistance ratings from 4.6 mΩ to 18.5 mΩ in half-bridge, full-bridge, and 3L-T-NPC circuit configurations. They also maintain pin compatibility with industry-standard press-fit modules.

The 1200-V SiCPAK modules are now available for mass production. Datasheets can be found here.

Navitas Semiconductor 

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📰 Газета "Київський політехнік" № 17-18 за 2025 (.pdf) Інформація КП чт, 04/24/2025 - 22:00

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To support the rapid growth of electric vehicles, Infineon has introduced a new generation of energy-efficient silicon IGBTs and reverse-conducting IGBTs (RC-IGBTs). The 3rd generation Electric Drive Train (EDT3) IGBTs target both 400-V and 800-V systems, while the RC-IGBTs are optimized for 800-V architectures. These devices boost drivetrain efficiency and are well-suited for automotive applications.

EDT3 chipsets support collector-emitter voltages of up to 750 V and 1200 V, with a maximum virtual junction temperature of +185°C. They offer high output current, making them useful for main inverters in battery-electric, plug-in hybrid, and range-extended EVs. Their compact, optimized design enables smaller modules, helping automakers build more efficient and reliable powertrains that can extend driving range and lower emissions.

The 1200-V RC-IGBT enhances performance by integrating IGBT and diode functions on a single die, achieving higher current density than discrete chipset solutions. This integration reduces assembly effort and chip size, offering a scalable, cost-effective option for powertrain systems.

All of the devices are offered with customized chip layouts, including on-chip temperature and current sensors. Additionally, metallization options for sintering, soldering, and bonding are available on request.

The EDT3 and RC-IGBT devices are now sampling. For more information, click here.

Infineon Technologies 

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Powered by a 32-MHz Arm Cortex-M23 processor, the Renesas RAOE2 group of entry-level MCUs offers low power consumption and an extended temperature range. The devices have a feature set that is optimized for cost-sensitive applications such as battery-operated consumer electronics, small appliances, industrial control systems, and building automation.

RAOE2 MCUs consume 2.8 mA in active mode and 0.89 mA in sleep mode. An integrated high-speed on-chip oscillator supports fast wakeup, allowing the device to remain in software standby mode longer—where power consumption drops to just 0.25 µA. With ±1.0% precision, the oscillator also improves baud rate accuracy and maintains stability across a temperature range of -40°C to +125°C.

The MCUs operate from 1.6 V to 5.5 V, eliminating the need for a level shifter or regulator in 5-V systems. They offer up to 128 KB of code flash and 16 KB of SRAM, along with integrated timers, serial communication interfaces, analog functions, and safety features. Security functions include a unique ID, true random number generator (TRNG), AES libraries, and flash read protection.

RAOE2 MCUs are available now in a variety of packages, including a 5×5-mm, 32-lead QFN.

RAOE2 product page

Renesas Electronics 

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Low-current PMICs in AKM’s AP4413 series enable efficient battery charging in devices that typically use disposable batteries, including remote controls, IoT sensors, and Bluetooth trackers. With current consumption as low as 52 nA, they have minimal impact on a system’s power budget—critical for energy harvesting applications.

The series comprises four variants with voltage thresholds tailored to common rechargeable battery types. Each device integrates voltage monitoring to prevent deep discharge, enabling quick startup or recovery. An inline capacitor allows the AP4413 to maintain operation even when the battery is fully discharged, while recharging it simultaneously.

System configuration example.

The AP4413 PMICs are in mass production and come in 3.0×3.0×0.37-mm HXQFN packages.

AP4413 product page

Asahi Kasei Microdevices 

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Cadence has announced the first DDR5 12.8-Gbps MRDIMM Gen2 memory IP subsystem, featuring a PHY and controller fabricated on TSMC’s N3 (3-nm) process. The design was hardware-validated with Gen2 MRDIMMs populated with DDR5 6400-Mbps DRAM chips, achieving a 12.8-Gbps data rate—doubling the bandwidth of the DRAM devices. The solution addresses growing memory bandwidth demands driven by AI workloads in enterprise and cloud data center applications.

Based on a silicon-proven architecture, the DDR5 IP subsystem provides ultra-low latency encryption and advanced RAS features. It is designed to enable the next-generation of SoCs and chiplets, offering flexible integration options, as well as precise tuning of power and performance.

Combined with Micron’s 1γ-based DRAM and Montage Technology’s memory buffers, Cadence’s DDR5 MRDIMM IP delivers a high-performance memory subsystem with doubled bandwidth. The PHY and controller have been validated using Cadence’s DDR Verification IP (VIP), enabling rapid IP and SoC verification closure. Cadence reports multiple ongoing engagements with leading customers in AI, HPC, and data center markets.

For more information, visit the DDR5 MRDIMM PHY and controller page.

Cadence

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The Northeast Microelectronics Coalition (NEMC) Hub has announced $1,432,373 in awards to 19 startups and small businesses through its Powering Regional Opportunities for Prototyping Microelectronics (PROPEL) Operations Program, which helps companies to reach commercial readiness by reducing day-to-day costs that include software licensing, employee training, securing patents and cybersecurity services, hence accelerating the transition of technologies from laboratories to fabrication facilities and preparing for new commercial investments...

Інфраструктура для енергетичної стійкості та цифрової освіти kpi чт, 04/24/2025 - 19:26

На війні загинув випускник ІАТ Антон Забродський kpi чт, 04/24/2025 - 19:15

A new quantum-safe root-of-trust solution enables ASICs and FPGAs to comply with post-quantum cryptography (PQC) standards set out in regulations like the NSA’s CNSA 2.0. PQPlatform-TrustSys, built around the PQC-first design philosophy, aims to help manufacturers comply with cybersecurity regulations with minimal integration time and effort.

It facilitates robust key management by tracking the key’s origin and permission, including key revocation, an essential and often overlooked part of securing any large-scale cryptographic deployment. Moreover, root-of-trust enforces restrictions on critical operations and maintains security even if the host system is compromised.

Next, key origin and permission attributes are extended to cryptographic accelerators connected to a private peripheral bus. PQPlatform-TrustSys, launched by London, UK-based PQShield, has been unveiled after the company achieved FIPS 140-3 certification through the Cryptographic Module Verification Program (CMVP), which is designed to evaluate cryptographic modules and provide agencies and organizations with a metric for security products.

PQShield, a supplier of PQC solutions, has also built its own silicon test chip to prove this can all be delivered ‘first time right’. Its PQC solutions are developed around three pillars: ultra-fast, ultra-secure, and ultra-small.

PQShield’s security products are built around three basic tenets: ultra-fast, ultra-secure, and ultra-small.

The PKfail vulnerability has thrust multiple security issues within the secure boot and secure update domains, which play a fundamental role in protection against malware. Inevitably, ASICs and FPGAs will need to ensure secure boot and secure update while meeting both existing and new regulatory requirements with clear timelines set out by NIST.

Industry watchers believe that we have a five-to-10-year window to migrate to the PQC world. So, the availability of a quantum-safe root-of-trust solution bodes well for preparing ASICs and FPGAs to function securely in the quantum era.

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ROHM has announced the availability of OEM quantities of new 4-in-1 and 6-in-1 silicon carbide (SiC) molded modules in the HSDIP20 package optimized for PFC(power factor correction) and LLC (inductor-inductor-capacitor) converters in on-board chargers (OBC) for xEV electric vehicles. The lineup includes six models rated at 750V (BSTxxx1P4K01) and seven products rated at 1200V (BSTxxx2P4K01). All basic circuits required for power conversion in various high-power applications are integrated into a compact module package, reducing the design workload for manufacturers and enabling the miniaturization of power conversion circuits in OBCs and other applications...

Almost every wall power supply has no indicator showing whether current is consumed by the load or not.

Wow the engineering world with your unique design: Design Ideas Submission Guide

It seems that this was a shortcoming that was not only noticed by me: I once saw the solution given in Figure 1.

Figure 1 Wall power supply indicator solution showing whether or not a current is being consumed by the load or not.

The thing is that the circuit was not functional—there were only places for the transistor, LED, and resistors on the board, not the elements themselves. It’s easy to say why: the voltage drop base-emitter (Vbe) is about 0.7 V, or 15% from the output voltage of this 5-V device. A monitor like this (Figure 1) would only be tolerable with a 12-V device or higher (24 V).

The circuit in Figure 2 is exceptionally good for low voltages, around 3 to 9 V, and for currents exceeding ~50 mA.

Figure 2 Current monitor circuit for a wall power supply that is good for voltages from 3 to 9 V and currents exceeding 50 mA.

It provides not only the opportunity to monitor its output current in a more efficient (30x) way, the bi-color LED allows it to estimate the value of the current and indicates the on-state of the device. Of course, the LEDs might be separate as well.

As for Q1, Q2: any low-power PNP with a reasonably high B will do, e.g., BC560.

—Peter Demchenko studied math at the University of Vilnius and has worked in software development.

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The post Current monitor appeared first on EDN.

Average of specific signal components

Sometimes, you only want to analyze those signal components that meet certain criteria or occur at certain times within an acquisition. This is not too difficult for a single acquisition, but what if you want to obtain the average of those selected measurement events? Here is where seemingly unrelated features of the oscilloscope can work together to get the desired data.

Consider an application where a device produces periodic RF pulse bursts, as shown in Figure 1.

Figure 1 The device under test produces periodic RF pulse bursts; the test goal is to acquire and average bursts with specific amplitudes. Source Arthur Pini

The goal of the test is to acquire and average only those bursts with a specific amplitude. In this case, those with a nominal value of 300 millivolts (mV) peak-to-peak. This desired measurement can be accomplished using the oscilloscope’s Pass/Fail testing capability to qualify the signal. Pass/Fail testing allows the user to test the waveform based on parametric measurements, like amplitude, and pass or fail the measured waveform based on it meeting preset limits. Alternatively, it can be tested by comparing the waveform to a mask template to determine if the waveform is within or outside of the mask. Based on the test results, many actions can be taken, from stopping the acquisition, storing the acquired waveform to memory or file, sounding an audible alarm, or emitting a pulse.

Selective averaging uses Pass/Fail testing to isolate the desired pulse bursts based on their amplitude or conformance to a mask template. Signals meeting the Pass/Fail criteria are stored in internal memory. The averager is set to use that storage memory as its source so that qualified signals transferred to the memory are added to the average.

Setting up Pass/Fail testing

Testing is based on the peak-to-peak amplitude, which uses measurement parameter P1. The measurement setup accepts or passes a pulse burst having a nominal peak-to-peak amplitude of 300 mV within a range of ±50 mV of nominal. The test limits are set up in test condition Q1 (Figure 2).

Figure 2 The initial setup to capture and average only pulses with amplitudes of 300 ± 50 mV. Source: Arthur Pini

The oscilloscope’s timebase is set to capture individual pulse bursts, in this case, 100 ns per division. This is important as only individual bursts should be added to the average. A single burst has been acquired, and its peak-to-peak amplitude is 334 mV, as read in parameter P1. The Pass/Fail test setup Q1 tests for the signal amplitude within ±50 mV of the nominal 300 mV amplitude. These limits are user-adjustable to acquire pulse bursts of any amplitude.

A single acquisition is made, acquiring a 338 mV pulse, which appears in the top display grid. This meets the Pass/Fail test criteria, and the signal is stored in memory M1 (Figure 3).

Figure 3 Acquiring a signal that meets the acceptance criteria adds a copy of the signal in memory M1 (center grid) and adds it to the averager contents (lower grid). Source: Arthur Pini

The memory contents are added to the average, showing a waveform count of 1. The Actions tab of the Pass/Fail setup shows that if the acquired signal passes the acceptance criteria, it is transferred into memory. The waveform store operation (i.e., what trace is stored in what memory) is set up separately in the Save Waveform operation under the File pulldown menu.

What happens if the acquired pulse doesn’t meet the test criteria? This is shown in Figure 4.

Figure 4 Acquiring a 247 mV burst results in a failed Q1 condition. In this case, the signal is not stored to M1 and is not added to the average. Source Arthur Pini

The acquired waveform has a peak-to-peak amplitude of 247 mV, outside the test limit. This results in a failure of the Q1 test (shown in red). The test action does not occur, and the low amplitude signal is not added to the average.

Using mask templates

Selective averaging can also be based on mask testing. Masks can be created based on an acquired waveform, or custom masks can be created using software utilities from the oscilloscope manufacturer and downloaded to the oscilloscope. This example uses a mask based on the acquired signal (Figure 5).

Figure 5 A mask, based on the nominal amplitude signal, is created in the oscilloscope. The acquired signal passes if all waveform samples are within the mask. Source Arthur Pini

The mask is created by adding incremental differences both horizontally and vertically about the source waveform. All points must be inside the mask for the acquired signal to pass. As in the previous case, if the signal passes, it is stored in memory and added to the average (Figure 6).

Figure 6 If the acquired signal is fully inside the mask, it is transferred to memory M1 and added to the average. Source Arthur Pini

If the acquired signal has points outside the mask, the test fails, and the signal is not transferred to memory or the average (Figure 7).

Figure 7 An example of a mask test failure with the circled points outside the mask. This waveform is not added to the average. Source Arthur Pini

Selective averaging with a gating signal

This technique can also be applied to signals on a multiplexed bus with a gating signal, such as a chip select, available (Figure 8). 

Figure 8 Pass/Fail testing can be employed to select only those signals that are time-coincident with a gating signal, such as a chip select signal. Source: Arthur Pini

The gating signal or chip select is acquired on a separate acquisition channel. In the example, channel 3 (C3) was used. The gating signal is positive when the desired signal is available. To add only those signals that coincide with the gating signal, pass/fail testing verifies the presence of a positive gating signal. Testing that the maximum value of C3 is greater than 100 mV verifies that the gate signal is in a high state, and the test is passed. The oscilloscope is set to store C1 in memory M1 under a passed condition, which is added to the average (Figure 9).

Figure 9 The average based on waveforms coincident with the gate positive gate signal state. Source: Arthur Pini

Isolating test signals

If the segments of the analyzed signal are close together and cannot be separated using the standard timebase (1,2,5 step) scales, a horizontal (zoom) expansion of the acquired signal can be used to select the desired signal segment part. The variable zoom scale provides very fine horizontal steps. The zoom trace can be used instead of the acquired channel, and the average source is the zoom trace.

Selective averaging

Selective averaging, based on Pass/Fail testing, is an example of linked features in an oscilloscope that complement each other and offer the user a broader range of measurements. Averaging was the selected analysis tool, but it could have been replaced with the fast Fourier transform (FFT) or a histogram. The oscilloscope used in this example was a Teledyne LeCroy HDO 6034B.

Arthur Pini is a technical support specialist and electrical engineer with over 50 years of experience in electronics test and measurement.

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For its fiscal second-quarter 2025 (to end-February), LED chip and component maker SemiLEDs Corp of Hsinchu, Taiwan has reported revenue of $10.87m, up from just $1.26m last quarter and $0.89m a year ago...

As we near the halfway mark of this decade, the pace of technological advancement continues to surge like never before. These advancements aren’t just changing how we work and live—they’re redefining what’s possible. Based on emerging research and industry forecasts, here are the most significant developments poised to reshape our world in the coming years.

The Sustainability Revolution Goes Mainstream

Technological progress is now being driven by a deep commitment to environmental responsibility. Cutting-edge solutions like carbon-neutral data centers, self-healing materials, and AI-powered energy optimization systems are moving from experimental to essential. The next wave of innovation will blur the line between ecological preservation and technological advancement, creating a new standard for responsible development.

AI Transforms from Assistant to Architect

Artificial intelligence is undergoing its most profound evolution yet. Beyond automating tasks, next-generation AI systems will design solutions, predict market shifts before they occur, and even contribute to scientific breakthroughs. This shift will create new opportunities in fields ranging from pharmaceutical research to urban planning, fundamentally altering how we approach complex challenges.

Urban Ecosystems Come Alive

Cities are evolving into responsive, intelligent organisms. Through a combination of advanced IoT networks, distributed computing, and real-time analytics, metropolitan areas will dynamically adapt to their inhabitants’ needs. Imagine streetlights that adjust based on pedestrian flow, or waste systems that predict and prevent overflow—these are no longer futuristic concepts but imminent realities.

Technology Disappears into Experience

The most profound tech innovations will be the ones we don’t notice. Frictionless interfaces, anticipatory systems, and biologically inspired designs will make technology feel increasingly natural and intuitive. This invisible revolution will prioritize human needs over technical specifications, creating experiences that adapt to us rather than requiring us to adapt to them.

Security Becomes Proactive and Predictive

In our hyperconnected world, cybersecurity is evolving from defense to anticipation. Emerging technologies like behavioral biometrics and quantum-resistant cryptography will create systems that identify threats before they materialize. This paradigm shift will redefine trust in the digital age, enabling safer innovation across all sectors.

Charting the Course Forward

These converging trends reveal a future where technology serves as both catalyst and compass—driving progress while helping us navigate its implications. For businesses and individuals alike, success will depend on understanding these transformations and adapting with intention.

The coming years promise extraordinary possibilities, but they demand equally extraordinary vision. Those who can anticipate these shifts and harness their potential will shape not just their own future, but the future of our interconnected world.

The post Navigating the Future: Key Tech Trends Shaping 2025 and Beyond appeared first on ELE Times.