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In response to growing demand from AI data centers and the shift towards solid-state power protection, Infineon Technologies AG of Munich, Germany is expanding its CoolSiC JFET portfolio with new devices, package options and configurations, aiming to support high-performance power distribution and protection systems...

The demand for higher power densities in increasingly space-constrained environments continues to grow, whether in on-board chargers for electric vehicles or power supplies for AI data centers. At the recent PCIM Europe 2026 (Power Electronics, Intelligent Motion, Renewable Energy and Energy Management) Expo & Conference in Nuremberg, Germany (9–11 June), Munich-based Infineon Technologies AG hence introduced EasyPACK S, a compact power module and packaging concept specifically designed to meet these requirements. With a package height of only 5.6mm and a footprint of about 33mm x 36mm, EasyPACK S is said to enable significant system miniaturization while ensuring reliable thermal performance and reduced electromagnetic interference. The first modules available in the new package integrate Infineon’s CoolSiC MOSFETs 1200V G2 as well as IGBT4 and IGBT7 1200V technology...

Infineon Technologies AG of Munich, Germany has begun sampling silicon carbide (SiC) bidirectional switches (BDS) built on rugged 750V CoolSiC G2 technology. A vertically integrated dual-die with common drain design in a top-side-cooled Q-DPAK package integrates two power switches into one to simplify design and enable the evolution of legacy topologies. The 750V CoolSiC BDS is said to deliver the reliability margin that modern grids and energy systems demand, resulting in the lowest total cost of ownership during the application lifetime...

With power conversion architectures in automotive and industrial applications evolving rapidly (placing new demands on switching topologies, thermal management, and system integration), Infineon Technologies AG of Munich, Germany has made available samples of the H-DPAK, a new addition to its top-side-cooling package family, housing integrated half-bridge (HB) devices in 750V CoolSiC G2 technology...

Екскурсія на Броварський завод котельного обладнання: як теоретичні знання трансформувати в практичні рішення Інформація КП пт, 06/26/2026 - 16:00

Sometimes, getting true stress levels can be tricky because things happen that are sneaky.

Stress analysis is often required to confirm that a designed product will perform properly in hazardous environments. Rather than trying to ascertain a “mean time between failures” (MTBF) or a “mean time to repair” (MTTR), the required assumption can also be that failure is simply unacceptable, no matter what, with the further assumption that repairs will simply not take place. For example, when spacecraft are sent out, they usually had better just work…period.

Among the tools that can be brought to bear toward that end, we have MIL-STD-975M (NASA), in which derating guidelines are given for all kinds of electronic parts. If your components all operate within stress limits as defined in that document, it will be assumed that your product will function as required after having been launched.

Sometimes though, getting true stress levels can be a bit tricky because sneaky things can happen, as in the following case study. It exemplifies the following lesson: when doing a stress analysis on the components that have been incorporated into a product, don’t overlook the possibilities of transient conditions. Your design might not be as safe and secure as you think.

Imagine we have a half-bridge switch mode inverter. We can make a very simple SPICE model for it and see what happens when the circuit is first energized.

Figure 1 A simple SPICE model for an also-simple circuit shows what happens when it is first energized.

L1 and R3 are a crude model of the primary winding of a loaded inverter transformer. We look at the voltage excursion that capacitor C1 undergoes when the circuit is first energized and see that the voltage there follows an under-damped wave shape.

Even though the final value of the C1 voltage is headed for half the rail voltage (minus just a little bit of that half to account for switching losses), there is a momentary voltage excursion that goes to a positive peak which is well above that final settling point.

Excerpting from MIL-STD-975M, we find the following.

Figure 2 These excerpts from MIL-STD-975M are relevant to the example half-bridge switch mode inverter circuit.

Taking one particular CLR81, 220 µF capacitor whose nominal voltage rating is 75 volts, if we apply the derating requirement of 0.4, we have an allowable maximum voltage of 75 x 0.4 = 30 volts.

If we are so blithe as to say that C1 will have 14 volts across itself, we will find a stress level of 46.7%, but what we really have is a peak excursion during power-on rising to 21.451 volts, which means a stress level on C1 of 71.5%. We will still be okay, but we will have significantly less of a safety factor to the maximum stress level than we might have originally thought.

Sneaky stuff like this could result in you overlooking an over-stress condition. It is therefore important to consider every circumstance, from stead-state service to any kind of transients to which your designed product’s components may (or maybe more accurately, will?) be subjected.

John Dunn is an electronics consultant and a graduate of The Polytechnic Institute of Brooklyn (BSEE) and of New York University (MSEE).

Related Content

• Semiconductor Reliability and Quality Assurance–Failure Mode, Mechanism and Analysis (FMMEA)
• Design for reliability: You have the tools
• Electronic Components Derating – Made Easy
• Connector voltage stress, Part 1 and Part 2

The post Stress analysis appeared first on EDN.

New episodes highlight how the latest electronics are enabling sustainable design across industries

DigiKey, the global distribution leader of electronic components and automation products, announces the release of the second season of its Sustainable Futures video series, which examines how advanced electronics, from infrastructure to intelligence, are enabling cleaner energy, smarter systems, and more sustainable design across industries. DigiKey releases the second season of its Sustainable Futures video series, which explores the components and technologies behind efficient power systems. 

Sustainable Futures, sponsored by Harwin and Analog Devices, highlights the components and technologies behind efficient power systems, intelligent infrastructure, and reliable performance in demanding environments. From high-performance signal processing and energy management to rugged interconnects and advanced materials, these solutions enable engineers to design systems that are more efficient, scalable, and resilient. The series also explores how these technologies support real-time decision-making, improve system reliability, and help bring sustainable innovations from concept to deployment.

“In season two of Sustainable Futures, we examine how advanced electronics are driving cleaner energy, smarter infrastructure, and meaningful real-world impact,” said Ken Paxton, director, advanced semiconductor for DigiKey. “The team at DigiKey is encouraged by the work our partner organizations are doing to shape the technologies that will help build a sustainable future for all.” 

“Sustainability is a journey, and as expectations evolve, companies are increasingly expected to reflect the values of their customers and partners,” said Ryan Smart, vice president of product for Harwin. “Harwin is proud to provide leading-edge interconnect technology that supports more efficient, reliable, and sustainable solutions across a wide range of applications.”

“The modernization of the power grid is among the most demanding engineering challenges of our time, requiring breakthroughs in power conversion, real‑time sensing, and system‑level intelligence,” said David Andeen, senior director, business development & marketing for Analog Devices. “Analog Devices is proud to contribute to this transformation through our high‑performance power solutions.”

Episode 1: “Intelligence That Drives Efficiency” – This episode examines how renewable energy generation, smart grid infrastructure, and intelligence at the edge work together to create more efficient, resilient, and adaptive energy systems. Analog Devices’ technology enables innovation at every stage, providing system-level intelligence for measurement, control, and real-time optimization. 

Episode 2: “Building the Backbone of Electrification” – This episode looks at how EV charging infrastructure and material innovations contribute to sustainable transportation and energy systems. Harwin highlights how high-reliability interconnects and eco-friendly materials enable safe, durable, and efficient solutions that can be deployed at scale.

Episode 3: “Shaping What Comes Next” – The final episode looks ahead to the future of sustainable electronics, where AI, advanced materials, and sustainable manufacturing converge. It connects hardware, intelligence, and collaboration into a unified vision for how the industry can scale sustainable innovation over the next decade. 

The post DigiKey Releases Season Two of Sustainable Futures Video Series appeared first on ELE Times.

Arrow Electronics and STMicroelectronics (ST) unveil a new industrial Autonomous Mobile Robot (AMR) reference platform to shorten the path from concept to deployment for professional service robots.

Autonomous mobile robots are rapidly transforming factories, laboratories, warehouses, and logistics centers. These robots must safely navigate dynamic environments, localize accurately indoors, manage energy efficiently, and integrate advanced perception and artificial intelligence, while meeting demanding reliability and time-to-market requirements. Many robotics original equipment manufacturers (OEMs) and integrators struggle to assemble, validate, and industrialize these complex subsystems independently.

“This solution brings together the performance, flexibility, and pre-validated integration robotics customers need to move faster from development to deployment, while giving them a scalable foundation that can address a broad range of industrial and commercial robotics applications,” said Shelby Schnurrenberger, vice president of supplier management, global semiconductor, Arrow Electronics.

“ST’s broad industrial portfolio is a natural fit for autonomous mobile robot applications, where reliability, performance, and scalability are essential. By combining our technologies with Arrow’s engineering services, we are helping customers turn innovative robotic concepts into industrial-ready solutions. Together, we can accelerate the development of the next generation of AMRs for the market,” said Allan Lagasca, application director of robotics segment strategic program (SSP), smart industrials segment leader, STMicroelectronics.

To address this challenge, Arrow and eInfochips worked with ST to deliver a fully functional AMR kit built on a complete ST bill of materials, tightly integrated with an NVIDIA Jetson Orin Nano–based compute platform and NVIDIA ROS 2 software stack. Arrow and eInfochips contribute their proven Rover mechanical platform and system integration expertise, while ST provides a comprehensive portfolio of industrial-grade components and reference designs.

The new AMR reference kit combines the following features:

• Robust power and battery management for 24V operation, with a pre-validated path to 48V architectures
• STM32-based real-time controller board, acting as a powerful interface between the NVIDIA platform and the robot’s sensors and actuators
• Advanced motion control, including dual BLDC motor drives based on STSPIN32 and STDRIVE devices for precise, smooth navigation
• Rich sensing for perception and safety, using ST MEMS IMUs, magnetometers, and environmental sensors, complemented by lidar and vision inputs for SLAM-based mapping and navigation
• Industrial ROS 2 software integration, enabling mapping, localization, and autonomous navigation with standard tools such as Cartographer, NAV2, and RViz ROS 2

 The new platform offers a robust, pretested system-level design that significantly reduces development risk, integration effort, and time to market. Robot manufacturers and system integrators can start from a working, realistic AMR including chassis, electronics, and software—and then rely on engineering services from Arrow and eInfochips to customize mechanics, features, and cost-optimized designs, while ST provides a one-stop, complete bill-of-materials solution with long-term product support. This cooperation enables the AMR ecosystem to move faster from prototype to production, helping customers deliver safer, smarter, and more efficient mobile robots for industrial and commercial environments worldwide.

The post Arrow Electronics and STMicroelectronics to Accelerate Industrial AMR Development appeared first on ELE Times.

Wireless technology company Baylin Technologies Inc of North York, Ontario, Canada (which provides passive and active RF and satellite communications products and services) says that its Advantech Wireless subsidiary has recently received purchase orders totalling over CDN$9m for its Genesis C-band and Ku-band solid-state power amplifiers (SSPAs) ranging from 200W to 500W...

⚡️ Реєстрацію на Sikorsky CTF 2026 відкрито! kpi пт, 06/26/2026 - 09:16

Vishay Intertechnology, Inc. introduces a new Automotive Grade phototransistor optocoupler to deliver signal transmission with high galvanic isolation for electric vehicles (EV), including emerging 800 V battery architectures, and industrial automation systems. The Vishay Semiconductors VOLA617A combines an isolation voltage of 5000 VRMS with a VIORM of 1414 Vpeak and VIOTM of 8000 Vpeak in a 4-pin LSOP low-profile package.

The device released today is ideal for grid-connected on-board chargers (OBC), DC/DC converters, battery management systems (BMS), isolated wake-up signals, and any system control with galvanic and noise isolation. While most automotive optocouplers can not be used for battery voltages exceeding 500 V, this limits them to traditional 400 V EV platforms. VOLA617A isolates DC voltages up to 1000 V and enables its use in next-generation high-voltage EV architectures.

The VOLA617A consists of an infrared-emitting diode, optically coupled to a silicon planar phototransistor detector in a low-profile package with creepage and clearance distances of ≥ 8 mm. The device is available in four current transfer ratio (CTR) ranges and features a high 80 V collector-emitter voltage rating, allowing for more design flexibility.

The optocoupler operates over a wide -40 °C to +125 °C temperature range with a junction temperature capability up to +145 °C while providing low coupling capacitance of 0.5 pF and high common mode transient immunity. Exceeding requirements for Automotive Grade performance and reliability, the VOLA617A’s robust package provides an extra safety margin by meeting dual AEC-Q102 qualification standards. The device is RoHS-compliant, halogen-free, and Vishay Green.

The post Vishay Intertechnology Automotive Grade Phototransistor Optocoupler Delivers High Isolation Voltage Ratings for 800 V EV Batteries appeared first on ELE Times.

 The DSA504RT delivers high-performance timing and integration at a cost-efficient price point

Spacecraft timing systems must provide highly stable, precise signals for navigation, communications, and scientific instruments, even when GNSS signals are weak or unavailable. Designers often rely on multiple oscillators and buffers to supply precise frequencies to various subsystems, adding size, mass, and complexity. Microchip Technology announces the space-grade DSA504RT, a radiation-tolerant, six-output programmable clock generator for addressing the complex timing needs of aerospace and defense applications. 

The DSA504RT streamlines timing architecture by generating multiple clean, phase-aligned frequencies from a single master source. Additionally, this solution reduces the need for multiple discrete oscillators, lowers overall component count, and improves system failure in time (FIT) rate. It also reduces power consumption and mass, as well as simplifies distribution networks to keep all subsystems synchronized even in the harshest environments and during GNSS outages or disruptions.

Analog Phase-Locked Loop (APLL) features spread spectrum capability, two fractional and two integer dividers, and six highly configurable output buffers, each of which can be configured as a differential driver (LVPECL, LVDS, or HCSL) or as a pair of single-ended CMOS outputs. The DSA504RT delivers ultra-low jitter performance as low as  200 femtoseconds (12kHz–20MHz) and is compliant with PCIe Gen 1-7 standards. This level of integration allows engineers to replace multiple crystals, oscillators, and buffers with a single device, improving design reliability, reducing Bill of Materials cost, and design complexity.

“This Microchip clock generation device is a game-changer for space applications. It can offer a comprehensive clock tree solution, producing three different clock families and up to six different frequencies, each buffered on a variety of selectable output drive types,” said Maamoun Abou Seido, appointed vice president of Microchip’s timing communications group. “Replacing numerous oscillators, buffers, and synthesizers, the DSA504RT saves board space and reduces part count to improve the system’s Failures in Time (FIT) rate in these high-reliability applications.”

The DSA504RT, offered in QFN28 and CQFP32 packages, serves as a companion device for complex aerospace and defense systems. It enables high integration of clock architectures within a single chip, distributing precise timing references to subsystems built around radiation-tolerant or radiation-hardened FPGAs and MCUs.

The post Spacecraft Timing Architecture: Microchip’s Radiation-Tolerant, Low-Power, Low-Jitter Six-Output Clock Generator appeared first on ELE Times.

VL53L9 is the first direct Time-of-Flight (dToF) 3D LiDAR all-in-one module in ST’s portfolio, offering a resolution of 2.3K zones, a wide field of view, on-chip processing, 100 frames per second, and a sensing range from 5 centimeters to 9 meters. It meets the evolving needs of customers and partners across diverse industries, including robotics, industrial automation, smart buildings, AR/VR, and healthcare.

The global semiconductor leader serving customers across the spectrum of electronic applications announces the launch of the VL53L9, a compact direct Time-of-Flight 3D LiDAR all-in-one module that sets a new benchmark in high-resolution sensing. The VL53L9 combines state-of-the-art features in a compact and cost-effective package, delivering AI-ready output data for low-compute edge AI systems on small microcontrollers (MCUs) and high-performance sensing across a wide range of applications across robotics, industrial automation, smart buildings, AR/VR, and healthcare.

“VL53L9 demonstrates how far Time-of-Flight sensing has evolved, combining high-resolution depth data, up to 100 frames per second, and a fully integrated architecture in a single compact module. By simplifying integration and reducing system complexity, we enable customers to accelerate the development of applications such as robotics, smart infrastructure, and healthcare monitoring,” said Alexandre Balmefrezol, Executive Vice President and General Manager of the Imaging Sub-Group at STMicroelectronics. “This launch reflects our strategy to move beyond standalone sensors and deliver integrated sensing systems that support real-world edge AI.”

“3D sensing demand accelerates across robotics, industrial automation, XR, and intelligent consumer devices. Time-of-Flight technology is expanding beyond smartphones into applications requiring compact, affordable, and precise depth perception, from navigation and people monitoring to gesture recognition and safety. Higher resolution multizone dToF modules are now emerging as key enablers for this next wave of 3D sensing adoption(1),” said Anas Chalak, Market & Technology Analyst at Yole Group.

 

ST FlightSense VL53L9 is designed for multiple industry use cases:

• Robotics: enhances small-object detection, SLAM (Simultaneous Localization and Mapping), and obstacle avoidance for autonomous navigation.
• Industrial automation: accurate volume measurement in tanks and bins, improving operational efficiency and inventory management.
• Smart buildings and homes: reliable human presence detection and people counting while preserving user privacy.
• AR/VR and consumer electronics: advanced gesture recognition, body tracking, and finger skeleton for immersive user experiences.
• Healthcare: fall detection and monitoring solutions for eldercare and patient safety.

Technical Information

Enhancing 3D sensing with precision and efficiency

The VL53L9 offers the 2,268 resolution zones (54×42) with a wide 54°x42° field of view, enabling detailed 3D depth mapping and precise detection of small objects, contours, and edges. Leveraging ST’s proprietary stacked BSI SPAD sensor technology and innovative metasurface optical elements (MOE), the module delivers fast and accurate ranging from less than 5 cm up to 9 meters with up to 1% accuracy and a frame rate of 100 frames per second.

All-in-one sensing data for edge AI and easy integration

The VL53L9’s dual-scan flood illumination replaces traditional dot scanning, reducing motion artifacts, eliminating dead zones, improving small-object detection, and capturing complementary 2D infrared and 3D depth images. In contrast to competition, this greatly simplifies post-processing and enables a broad range of edge AI use cases to run efficiently on small MCUs with low compute requirements. The all-in-one module further integrates on-chip dToF processing, a dedicated power management IC, and is fully calibration-free, simplifying integration and reducing system cost and complexity.

Compact form factor

Measuring just 12.8 mm x 6.1 mm x 4.6 mm, the VL53L9 is a reflowable, single-component module compatible with a wide range of cover glass materials. It supports dual-power-supply operation (1.2 V and 3.3 V) and outputs data via MIPI or I3C interfaces, ensuring compatibility with diverse CPU architectures. The module is certified as Class 1 laser safe, providing reliable and secure operation for end users.

For more information, visit the VL53L9 product page: https://www.st.com/vl53l9cx

The post STMicroelectronics Unveils New Compact Time-of-Flight 3D LiDAR Module for Compact Edge AI Systems appeared first on ELE Times.

I wanted a "real" quantum random number generator, something where every bit is an actual physical quantum event. First attempt was a 1970s Canon FD 55mm f1.2 with a thoriated rear element. It's pretty radioactive (the Geiger counter make scary noises). But radioactive decay gives you when an atom popped, which is timing-random, not the which-path coin flip I was after. The build that actually worked is optical: attenuate a light source down to single photons, fire them at a 50:50 UV beam splitter, and read which way each photon went with two detectors. Through → bit 0. Bounce → bit 1. The detectors are two Hamamatsu PMT modules a friend gave me, pulled out of a dead lab instrument. I tore it down, yanked the dichroic mirror, and dropped in a UV 50:50 splitter. For a fluorescent source I ended up using 3D-printer filament — it's faintly fluorescent at the right wavelength and doubles as a light-tight cover. All the detection and conditioning runs on a Red Pitaya (FPGA + fast ADCs): Op-amp + transistor LED current sink, reed-relay LED gate, PMT gain via dividers, all driven by the Red Pitaya's slow DACs so I could sweep everything in software instead of hand-twiddling pots. VHDL threshold + edge detection on the 14-bit ADC, a coincidence veto (kills double-fires / cosmic rays), and a symmetric "global blank" after every event — that last one matters, because per-channel dead time secretly biases the stream. A timestamped debug FIFO that was a chunk of fabric to build but caught a bunch of detector-memory artifacts I'd otherwise have shipped. The hard part genuinely wasn't generating random-looking bits, but it was proving they were real random bits from the optical system and not other noise sources. Most of the project ended up being diagnostics... Payoff demo is a Quantum Magic 8-Ball: hit a button, it pulls fresh quantum bits and gives you one answer (and, if you're an Everettian, every other answer somewhere in the multiverse). Full build log with schematics, scope shots, and the FPGA stuff: https://dnhkng.github.io/posts/building-the-beam-universe-splitter/ Happy to answer questions on the analog front end or the FPGA fabric — the analog side is honestly my weakest area, so I'd welcome the critique. TL;DR, and just want to play with the Quantum Magic 8-Ball? -> https://quantumlever.stream/oracle submitted by /u/Reddactor [link] [comments]

Від ідеї до дії: енергоефективність по-данськи Інформація КП чт, 06/25/2026 - 15:50

Hello r/electronics, In this post, I want to share my project that I’ve been working on in the past few months. It’s a custom-built lab bench power supply. Such a project is common in the DIY community, so what makes this one different? The custom-designed SMPS board that I engineered from scratch isn’t your typical “let’s put this power supply module into a case” approach. So let’s dive into the working principles, design decisions, and in-depth test results. The Forwarder 1kW is the SMPS board that I designed and used in this project. It’s based on a hard-switch, half bridge topology. The full features of this power supply are as follow: 1000W maximum continuous output capacity. Configurable from 50V/20A up to 400V/2.5A. CC/CV mode with mode signal and indicator. Tuneable operating frequency and dead-time. Dedicated power stage enable pin. Analog reference interface for output voltage/current control. Analog signal output interface for monitoring voltage/current. Dedicated fan port with optional automatic power-on. Simple construction, less than 130 components on board. Easy to build with mostly THT components. Curated component selection for high accessibility. The working principle of this design is about as simple as it can get for a switched-mode power supply. I talked about the working principle of my design over on r/AskElectronics, so I’m not going to repeat it here. Most of the concepts stay the same, just with some design adjustments and the numbers changed. https://www.reddit.com/r/AskElectronics/comments/1s8ll9g/ Now, I want to go in detail about the design decisions that led into this design that you may find interesting. The lack of active PFC (Power Factor Correction) was determined after I reviewed many existing designs and products in the same power level and after noticing many of them get away without one, I decided to omit this feature. For my first SMPS design, I want to focus solely on the DC to DC conversion power stage. For my next iteration, I’m more likely to resort to a simple boost PFC to achieve tighter regulation. Double-ended hard-switch topology (half-bridge in particular) was chosen due to its suitability and simplicity in this application. Flyback is out of the question due to power requirement, single-ended topologies have poorer core utilisation and the high favour for current mode control, and resonant topologies don’t seem like a good choice for my first SMPS design (duh). An SG3525 with LM324 was chosen to generate the PWM signal and achieve regulation. SG3525 is quite popular for double-ended converters with plenty of documentation online, while the LM324 provides CC+CV regulation with two of its op-amps (because SG3525 only features one error amplifier). This effectively forms a setup based on voltage mode control. Voltage mode control was inherently chosen as the result of using SG3525 and it was favoured due to its “arguably” simpler implementation over current mode control. However, I find the better regulation and inherent cycle-by-cycle overcurrent protection offered in current mode control very enticing. I probably would resort to this approach for my next iteration. My galvanic isolation strategy was to have the entire control circuit on the secondary side and have the PWM signal driven to the primary through a gate drive transformer. This way, I can have simpler and more precise control over the voltage and current regulation without the nonlinearity issues of using optocouplers. ETD49 cores were used for both transformer and output inductor. I like the round bobbin that makes winding easier, and the calculations prove it’s suitable for power of 1kW at 64kHz. The gapped version was used for the output inductor because the high inductance requirement requires high turn number, and that gets complicated real quick with toroidal cores. After I finished the board, I wanted to know how my design performs in real-life. So, I conducted a few tests that are relevant for a power supply. The testing rig was pretty simple: A power meter at the input and four DS18B20 were used to track the energy consumption and component thermal profile over time. An electrolysis tank with electrodes that can be spaced accordingly was used to simulate multiple load profiles at power up to 1kW. A third positive electrode connected through a toggle switch was used to abruptly step the load in the dynamic tests. Hantek DSO2D10 was used to capture the waveforms in various tests. The test conducted, along with their results are as follow: The stress test was conducted for one hour and each component temperatures peaked at the following temperatures: half-bridge N-MOS 75°C / 167°F, main transformer 55°C / 131°F, output rectifier 69°C / 156°F, output inductor 44°C / 111°F. The efficiency characterisation was conducted at 50V and 1, 2, 5, 10, and 20 amps. 89% efficiency was achieved at 5A load or more. Maximum recorded efficiency was 90.3% at 50V 10A load, and efficiency at maximum load was 89.1%. The output ripple test was done with direct on-trace probing with a ground spring, 20M BW limit, 1x probe, and no added capacitor. No load ripple showed at 40mVpp, 1A load at 34mVpp, and maxes out at 94mVpp at full load. The turn-on curve tests showed that under loaded condition, it’s bound to the SG3525 soft start function and takes a second to reach the full 50V. At no load and lower setpoints, the voltage overshoots by a few volts. The load step tests showed about 3% voltage deviation going from no load to 10A and vice-versa. Going from 5A to 10A and vice-versa showed no sign of voltage deviation. CV to CC transition took 3ms to begin responding and a full 7ms until the voltage settled. CC to CV transition began immediately and took 3ms to settle. 50V CV to 10A dead-short showed 10App oscillation at 2.2kHz. The input bulk capacitor showed 24Vpp ripple and the DC blocking capacitor showed 14.2Vpp ripple. The primary side of the transformer showed about 75% overshoot that settled within 2 cycles. The N-MOS at conduction showed 184nS fall time for Vds and 572nS rise time for Vgs. At disconduction, the Vds rise time showed as 56nS and 556nS for Vgs fall time. I’m here not to glaze over my design. After reviewing the results and doing a retrospective, here are my critical opinions about this design. What I like about this design: Good efficiency figure (89.1% at full-load) Excellent ripple even without a second-stage filtration (94mVpp at full load) Good power density for an almost-fully THT build. What I don’t like about this design: The overcurrent protection is too slow, though it somehow works at preventing the half-bridge from exploding on the dead-short test. The compensator design fails in certain conditions (DCM/CCM transitions, output dead short), which results in output oscillation. The output diodes are hard to access or replace. The full schematic, gerber files, KiCAD save files, spreadsheet calculation, and full-res images are available on my Github repository: https://github.com/Luq1308/Forwarder1kW The build process and the in-depth testing are available in my YouTube video: https://youtu.be/MGMqqtXgwRg That’s all I have about this project. I hope this post is informative and can be used as a reference or for benchmarking purposes, in which I had difficulty in researching previously. If you have any unanswered questions, let me know and I’ll try to answer them. Thank you for reading, and I'll see you next time. submitted by /u/Luq1308 [link] [comments]

Just because generational device improvements aren’t in-your-face obvious doesn’t mean they aren’t sooner-or-later still tangibly impactful.

As mentioned last week, one of the perks that accompanied my recent personal-cellular-line transition from AT&T to Google Fi Wireless was a free (after two years’ service, albeit still notably discounted upfront) Pixel 10 smartphone, which I’d needed to press into service immediately in order to qualify for the various promotion discounts (this “stock” photo is of the “Indigo” colorway; as noted last week, mine’s “Obsidian”):

As long-time readers may recall, I’ve been a (mostly) Google Pixel “daily driver” since mid-2017, across multiple product generations. And I’ve been specifically using a pair of Pixel 7s for the past three years. So, I feel a “bit” qualified to offer some observations and comparisons with past device experiences. Without further ado…

I’m not a power user

What I’m referencing by means of this admittedly cryptic initial section header is the fact that although the Pixel 10, which I initially wrote about as part of my coverage of Google’s August 2025 multi-product launch event, has a three-generation-newer Tensor SoC inside it (the G5, versus the earlier G2), the performance differences aren’t strikingly obvious. at least to me. Not that they’re nonexistent, mind you; Google’s increasingly impressive AI “chops” are most evident at the moment in the handset’s computational photography capabilities. That said, I strongly suspect that AI’s effects will be comparatively even more broadly visible (both in their results, responsiveness and fundamental existence) with the passage of time.

To that point, the “bump” in RAM from the Pixel 7 (8 GBytes) to the Pixel 10 (12 GBytes) is likely at least as important as is bolstered inference processing “muscle” in delivering local AI enhancements, as it enables on-device deep learning models to be more comprehensive and otherwise robust than would otherwise be the case, delaying if not completely foregoing a performance- and power-sapping handoff to the “cloud” in the process. And if there’s one upside to today’s semiconductor memory shortages, it’s that it’ll compel Google’s and other organizations’ developers to make their models even more efficient (while retaining sufficiently high results accuracy) than might otherwise be the case.

Pleasantly pocketable and reliably chargeable

Put the two phones side-by-side and you’ll realize that although the active screen dimensions and other high-level display attributes are identical (6.3” diagonal OLED with 1080 x 2400 pixel resolution, though the Pixel 10 variable refresh rate tops out at 120 Hz versus 90 Hz for the Pixel 7, for whatever that’s worth…), the Pixel 10 (at left in the following photos) is actually a smidge shorter and narrower, the result in part of bezel decreases, not to mention rounder:

• Pixel 7: 6.13 x 2.88 x 0.34 inches (155.6 x 73.2 x 8.7 mm)
• Pixel 10: 6.02 x 2.83 x 0.3 inches (152.8 x 72.0 x 8.6 mm)

That aside, the Pixel 10 has a higher internal battery capacity than its Pixel 7 forebear—4,970 mAh vs 4,355 mAh—and the foundry transition from Samsung to TSMC that accompanied the to-Tensor G5 SoC evolution also aspires to improve not only performance (decreasing the energy consumption necessary to complete a given task in the process) but also stored-electron efficiency, with the two factors combining to boost claimed battery life.

Speaking of battery life, a few words on charging. The Pixel 7 supports wired charging at up to a 21W incoming power payload and wireless charging at up to 12W with conventional Qi chargers or 20W with the pricey, seemingly no longer available 2nd-generation official Google Pixel Stand:

For the Pixel 10 family, there’s a new wireless charger, the magnet-augmented Pixelsnap (reflective of the magnet-inclusive and Apple MagSafe-reminiscent QI2 support now within the phones themselves), which supports 15W charging speeds with the baseline Pixel 10 and 25W for the high-end Pixel 10 Pro (both of which also support wired charging at 30W rates):

And even though, as with the Pixel 7, I still need to use a case that’s magnet-inclusive with the Pixel 10 to ensure sufficient “cling” strength to a charger or whatever else I’m striving to stick it to (or, depending on the circumstance, stick to it), MagSafe-tailored chargers now work with it, too. With the Pixel 7, charging reliability with magnet-based chargers such as my Belkin-based desktop:

and in-car setups:

was flaky at best, typically DOA with the magnet-augmented case but magnet-less foundation. Now, for whatever reason, it’s ironclad (I hope I haven’t jinxed myself by writing those words).

Optics upgrades

Speaking of computational photography, while the Pixel 7’s front camera did implement face recognition-based unlock support (for the first time since the Pixel 4), it was both too flaky and insufficiently robust in associated software support to be something I could rely on. Beginning with the Pixel 8 (therefore also including the Pixel 10), the implementation is not only faster but also more accurate and broadly robust, thanks to machine learning algorithm augmentation:

That said, it’s still reliant on the front visible light image sensor, dropping the Pixel 4’s Kinect-reminiscent and IR-derived structured light approach in the process, in an ironic contrast to the conceptually similar IR-based TrueDepth technique that Apple uses to this day with FaceID. As such, it doesn’t work great in dim light, and not at all in the dark; thankfully, Google has also seemingly improved its historically woeful fingerprint ID detection implementation as a backup in such situations. And there’s always also your PIN or other unlock sequence, after all…

One other camera-related note; in the earlier backs-of-phones images you might have noticed what appeared to be a third lens on the Pixel 10’s rear “camera bar”. Or maybe you’ve just noticed the increased prevalence of ultra-closeup pictures in my recent teardowns, ones specifically taken without the bulky multi-piece accessory I had to use previously:

Google refers to it as a 5X telephoto, and it’s admittedly nice for that, but its Macro Focus capabilities are what I’m lovin’ the most, right now at least.

Tying up loose ends

I mentioned earlier in this piece, and have also mentioned previously, how much I appreciated the fact that Google extended support (not only security patches but also full O/S updates) for the Pixel 6 and 7 series from 3 to 5 years at the end of 2024. As such, they’ll remain reliable backup-at-least options in my smartphone arsenal for at least the next year-plus. That said, beginning with the Pixel 8 series, therefore also including both my Pixel 10 and Pixel 9a, support was further extended to seven years from initial release date. Nice.

One (very) minor downside, for which I have nobody but myself to “blame” since I knew about it before I pressed “purchase”, involves ultrawideband (UWB) support. Apple’s latest-generation AirTag trackers leverage not only integrated Bluetooth and Wi-Fi subsystems but also UWB capabilities to enable more precise location discernment. So too do advanced Android-friendly trackers such as Motorola’s Moto Tags, one of which currently resides on my teardown shelf:

This is all well and good, but there’s one key qualifier: tracker-based UWB is only meaningful if the connected device that’s doing the tracking also supports UWB. That gives a green light to the Pixel 10 Pro, but not my UBW-deficient Pixel 10. Oh well…First World problems strike again.

And speaking of Android friendliness, I’m ironically writing this piece one day ahead of Google I/O 2026, with my special-project coverage of it scheduled to be published weeks ahead of this piece. Google has already talked some about Android-centric stuff at least week’s (again, as I write this) Android Show I/O Edition, replicating a cadence tradition it did for the first time a year ago. I’ll be curious to see what else Android- and Pixel-related is unveiled tomorrow. And I hope it doesn’t obsolete what I’ve just written today in the process! I’ll see you all “on the other side”, where I as-always also welcome your thoughts in the comments.

—Brian Dipert is the associate editor, as well as a contributing editor, at EDN.

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Ceva’s RealSpace Elevate is a Microsoft-certified Windows Audio Processing Object (APO) that enables spatial audio for PC gaming headsets. Unlike OS-level solutions that offer limited differentiation or branded third-party applications that restrict customization, the production-ready APO gives OEMs full control over performance and product identity. This includes customizable tuning and presets optimized for gaming and entertainment use cases such as music, movies, and podcasts.

Leveraging Ceva’s RealSpace spatial audio technology, the APO integrates precise sound localization and natural externalization within the Windows APO framework for seamless deployment on Windows PCs. It is optimized for gaming headset use cases, combining rich entertainment audio with competitive gameplay enhancements.

RealSpace Elevate supports 7.1 multichannel rendering with pinpoint accuracy and a realistic soundstage. Gaming-focused enhancements include controls to highlight critical in-game sounds such as footsteps or gunshots.

The licensable APO is available now. 

RealSpace Elevate product page  

Ceva

The post Windows APO delivers customizable spatial audio appeared first on EDN.

A 3D direct ToF LiDAR module, the VL53L9CX from STMicroelectronics offers 2.3k-zone resolution for low-compute edge AI systems. This compact all-in-one module integrates a SPAD array, post-processing SoC, two VCSELs, a BCD VCSEL driver, infrared filters, metasurface optical elements (MOEs), and PMIC. It enables high-resolution spatial awareness in robotics, industrial automation, smart buildings, and healthcare.

The VL53L9CX provides 2,268 ranging zones (54×42) across a wide 55°×42° field of view, allowing detailed 3D depth mapping and precise detection of small objects, contours, and edges. With stacked BSI SPAD sensors and MOEs, the module delivers fast, accurate ranging from less than 5 cm to 8.8 m with up to 1% accuracy and frame rates up to 100 fps.

Dual-scan flood illumination reduces motion artifacts and eliminates dead zones while enhancing small-object detection. It also combines 2D infrared and 3D depth imaging, simplifying post-processing and enabling edge AI applications to run on small MCUs.

The VL53L9CX is supplied in a miniature reflowable package. Mass production is scheduled for July 2026.

VL53L9CX product page 

STMicroelectronics

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