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ST is introducing an initiative to provide Rust drivers for many of our sensors, opening a new avenue for those looking to adopt this programming language in their embedded systems development. Obviously, we will continue to ship and maintain our C-based ecosystem.

However, we are also aware of the growing popularity of the Rust programming language, the benefits it offers for many projects, and that building a robust, platform-agnostic alternative in another programming language takes significant time and investment. It’s for those reasons that we have started porting drivers piecemeal and are now advertising our presence on crates.io and showcasing projects like Embassy STM32, which provides a hardware abstraction layer in Rust for our MCUs.

Reason One: Safety

One of the most popular aspects of Rust is its inherent code safety compared to other languages, including C and C++. In essence, that means the Rust compiler will forbid certain operations that could jeopardise memory safety. Being memory-safe means that the Rust compiler will block any memory access if it hasn’t been explicitly allocated or has already been deallocated. This is a significant departure from C and C++, where developers have much more freedom in memory management. However, it also means that bad code can lead to issues such as buffer overflows, memory leaks, and “use-after-free” or dangling pointers. All of these can result in data corruption or even security vulnerabilities.

The reason Rust is safer is that it implements Resource acquisition is initialisation (RAII), a technique that automatically and immediately allocates resources when an object is created and releases them when the object is deleted. The compiler allocates these resources to an owner and can then transfer ownership or allow another owner to borrow it if needed. As a result, Rust handles resource management and does not need a garbage collector to manage memory allocations, unlike C++, another language that implements RAII but still requires developers to manage memory themselves. In practice, the absence of a garbage collector reduces overhead, but it also makes Rust code much less lenient.

While this blog post can’t begin to scratch the surface of all the ways Rust differs from C and C++ (we won’t even go into type safety), the point above illustrates an important reason why developers are moving to Rust and why ST has already tried to provide alternatives to its sensor drivers. The Rust learning curve is high. Writing safe code that compiles is challenging because there are so many guardrails to ensure code safety. However, it also means that once the code compiles, developers have far greater assurance of safety and security. And for developers new to Rust, having open-source drivers like the ones ST provides means they can study our implementations and learn from our experience.

Reason Two: Practicality, Portability, and Performance (sort of)

Another reason developers are adopting Rust for their embedded projects is the way it handles interfaces and bus operations. Unlike C, which traditionally uses a pointer-based bus abstraction, Rust uses “Traits”, which define interfaces as types and then provide a flexible abstraction over them. Through ecosystem standards such as embedded-HAL, interfaces for buses like I2C and SPI can be implemented consistently across platforms, helping developers gain expertise. In fact, our code already uses APIs aligned with our original C drivers to ease the learning curve, and we adopted consistent naming to smooth the transition to our Rust alternative.

One misconception we often encounter is that Rust is inherently “faster” than C or C++. The truth is far more nuanced. Depending on the application, Rust may be slower than, on par with, or faster than C. However, in many instances, Rust forces teams to rewrite their application, which naturally leads to refactoring, dropping legacy code, or creating new, optimised processes. The absence of a garbage collector in Rust, or its modern compiler enhancements, certainly helps, but embedded system developers should not rush in thinking it will magically provide significant runtime improvements. However, it will offer significantly safer, often more flexible code, which is why we are providing Rust alternatives for our C sensor drivers.

Reason Three: The Rust Community

The discussions in our GitHub repository for this project show a thriving community, which is an important factor for many developers. It’s not just key industry players like Meta, Google, or Microsoft that have publicly pledged to adopt the new programming language. Many smaller teams are investing in the new language because acquiring fluency takes time, and falling behind could lead to significant technical debt that would benefit a competitor. We know that adoption is still in the early phase. This is why we are providing Rust sensor drivers now. ST wants to support those who want to be first in this transition, which seems to be shaping the future of embedded systems development.

The best way to get started is to install Rust using rustup, then, as developers build their project, grab one of our packages on Crates. Our GitHub Page also walks users through the download and integration process. We offer examples in Cargo to help teams get results faster. And while the drivers themselves allow engineers to be MCU-agnostic, the examples we use are written for STM32 microcontrollers and primarily use the NUCLEO-F401RE development board. Current Rust drivers focus on I2C and SPI interfaces, as these are by far the most commonly used, but additional support, including I3C, is underway, and we will update this blog post as we release major updates.

The post Rust MEMS Drivers: 3 Reasons to Try and Adopt Our New Sensor Drivers Written in Rust appeared first on ELE Times.

Understanding the brain requires tools that can follow neural activity across many scales: from millisecond electrical spikes in individual neurons to brain-wide circuit dynamics that change over months, years, and even a lifetime.

New smart phones, earbuds and watches, this year with an added dash of memory price increases. It’s September in Cupertino again.

September 1 was Tim Cook’s last day as Apple’s CEO, after a 15-year tenure with that title. Hereafter he’ll be Executive Chairman of the board of directors, succeeded as CEO by John Ternus, former senior vice president of Hardware Engineering. And reflective of the changing of the guard, Cook was nowhere to be seen in this morning’s prerecorded launch event video, albeit in a brief cameo at the beginning.

Not because, I suspect, Cook’s got anything against product launches, although after having fronted so many of them by now, he’d certainly be entitled to a bit of burnout. Instead, I’m guessing he just wanted to make the passing of the baton as clean and obvious as possible.

Just like last year…and the year before it…and…Apple launched new and updated wearable and broader mobile products in September 2026 (which, I’ll note, has just started, so we might not be done with the month yet, far from the rest of the year). The biggest surprise this time around was that today’s unveilings weren’t the first in this year’s late-summer sequence, having been preceded by the release of new M-series SoCs and systems containing them late last month.

And speaking of M-series SoCs, there’s as-usual no shortage of commonality between those earlier latest-generation application processors for computers and high-end tablets and the one(s?) that rolled out today for high-end iPhones. Speaking of which…

The iPhone 18 Pro series

What do you do if rising DRAM and flash memory costs are clobbering your products’ bill-of-materials budgets? You focus your new-product energy on the stuff that’s most profitable already. And you do something else…which I’ll share in a minute. New stuff first. There’s no mainstream iPhone 18 yet, for the first time ever. But the high-end iPhone 18 Pro and Pro Max are here. And they’re priced $100 higher than were their forebears of similar memory capacities, along with adding an even higher-end (and higher-priced) 2 Tbyte storage tier.

That new SoC? It’s the A20 Pro. First-time 2 nm-fabricated by foundry partner TSMC. 50% higher memory bandwidth than the A19 Pro. Faster CPU (6 cores total, 2 “super” and 4 “efficiency) and GPU (seven cores total) subsystems than those in the A19 Pro. And a dual 16-core Neural Engine inference subsystem. Lessee…where have we heard this same messaging…two weeks ago, to be exact? Yessiree, it seems that once again there’s no shortage of shared DNA between the late-August M6 and today’s A20 Pro SoCs, albeit with varying dollops of various on-die resources, befitting varying platform cost, feature and performance requirements.

What I’m admittedly most excited about as an unabashed photography geek is the camera subsystem’s variable aperture (along with, by association, manual shutter speed setting) support for the rear main unit.

Yes, it enables more meaningful user control of exposure, particularly in low light environments (adjusting for bright-light settings can always alternatively be done via integrated or external neutral density filters, of course). But it also first-time affords user adjustment of depth of field, allowing for both shallow-depth “bokeh” effects and sharpness across a wider depth range than possible before.

Oh, and by the way…even though Apple delayed releasing the mainstream iPhone 18 (which, in saying so, I’m obviously assuming is still coming eventually), the company still found another way to use our credit cards and bank accounts as counterbalance to the higher semiconductor-content costs it was incurring. The iPhone 17 Pro and Pro Max are no more, of course. But the company’s still selling the baseline iPhone 17 and 16, the boutique iPhone Air, and the “cost-effective” (relatively speaking, at least) iPhone 17e. That said, post-Apple Store resurrection mid-day today, they all now cost $100 more than they did yesterday. Yay…???

The AirPods 5

Two years ago this same month, Apple released the 4th-generation AirPods in two flavors, $129 with only passive noise reduction (PNR, and not great, at that, given their imperfect ear-shape seal for many users), and $50 more for an active noise control (ANC)-supportive model. I’d love to see the comparative sales stat results between the two variants, but clearly the world has moved en masse to ANC since then.

To wit, Apple’s fifth-generation AirPods successors have dropped the PNR option, but the company’s marketeers can’t seem to quit the price-differentiation shtick completely. Want a conventional wired-charging case? That’ll cost you $129. How about a wireless charging-capable case option? $20 more, please. Maybe two years from now, Apple Marketing will realize that the world’s already moved en masse to Qi…oh, sorry, this is Apple…MagSafe…too. Wonder how they’ll try to extract more money out of our wallets next time? Reader prognostications are as-always welcomed in the comments!

Apple Watch Series 12 and Watch Ultra 4

Three key takeaways distinguish this year’s mainstream and high-end smartwatches from their prior years’ versions:

• An upgraded S11 processor, whose specifics were as-usual not revealed but likely include a sprinkle (or few) of deep learning inference acceleration, reflected in…
• AI as a first-time notable element in Apple’s smartwatch pitch this time, particularly focusing on ambient audio processing capabilities (including conversations, although Apple predictably maintains its “privacy by design” reassurance mantra) and thanks in no small part to a recently unveiled partnership with Google that has seemingly finally gotten Siri on track for something other than corporate embarrassment, and…
• The other notable AI-analyzed data set, an enhanced health sensor suite enabling, among other things, continues heart rate monitoring every five seconds, all day.

This year’s models are identically priced to their generational predecessors, surprisingly, although around 24 hours ago, I’d wondered if Apple was going to deal with its burgeoning semiconductor memory bill-of-materials burden in a different way. Beginning some time yesterday and continuing for quite a while, although subsequently corrected, the company’s entry-level Apple Watch SE 3 models all became “unavailable” for purchase.

Apple typically takes its online store down a few hours ahead of launch events to make the necessary tweaks in preparation and out of the public eye, but this was unprecedented. I’d wondered if Apple was planning on dropping the whole line, either because it wasn’t AI-capable and/or because memory cost increases had rendered it insufficiently profitable, and if someone had “pulled the plug” prematurely and highly visibly. But given that the Watch Series 3 had just been unveiled a year ago, the “yank” seemed premature. As, it turned out, it was. Maybe. Then again, maybe someone just decided to do a last-minute course-change. We’ll likely never know.

Back to the future

I guess John Ternus thought that instead of charting his own course, he’d use his first launch event to “channel” a predecessor’s past glory. Yes, he pulled out the memory closet a Steve Jobs “chestnut”, the “one more thing”. And of course, it was one of the worst kept secrets of recent Apple corporate strategy: the foldable iPhone. Although at least one thing was surprising about it: industry scuttlebutt had long branded it the “iPhone Ultra”, but instead it’s the “iPhone Duo”. Begging the question of what, if anything, the “iPhone Ultra” will be…but I digress.

It’s $1999 (and up, capacity-dependent). It won’t be available until next month (October). And like its iPhone 19 Pro siblings, it’s based on the A20 Pro Soc. But I don’t want to spend my precious few remaining paragraphs in this section talking about that. Instead, I want to talk about aspect ratios. Let’s start with my long beloved, in spite of chronic software bugs, Microsoft Surface Duo, an example of which still inhabits my storage closet in the hopes that someone will someday release a stable, robust-featured, reasonably current Android build for it or…dare I dream…Windows 11 for Arm with Wi-Fi and cellular data support? Be still my heart.

Yes, it was foldable. But no, unlike the iPhone Fold it wasn’t comprised of a single piece of bendable OLED internal “glass”. Instead, there was that jarring hinge in-between the two internal displays. And there was no external screen, either, so you had to unfold it to use it at all, even for basic smartphone tasks. But again, I digress. Look at its aspect ratio. Unfold it and, without rotating it 90°, you had a 7.36” wide by 5.72” tall screen (yes, I know, with a gap in the middle) perfect for reading eBooks in a style akin to that of actual books, watching movies, and the like.

Next, let’s look at the first-generation (2023) Google Pixel Fold, an example of which my wife bought me for my birthday earlier this year.

Same fundamental aspect ratio, this time with an added bonus: no midway gap. And this time, there was a third outer display, too.

But given overall system form factor dimensions, it was atypical in both size (5.8” diagonal) and (especially) aspect ratio in comparison to the ones in conventional smartphones. Atypical equals low volume. Low volume equals costly and supplier-option deficiency. All of which explains why second and subsequent-generation Pixel Folds have switched to “bifolds”, taller than before, albeit losing the unfolded “book” (or, if you prefer, movie screen) form factor in the process.

Now look at the iPhone Fold again. The “book” form factor is back (in black, aka “night sky”, as well as “star white”)!

Apple perhaps obviously has supplier leverage that Google doesn’t (or at least didn’t) have, so assuming customers buy into the design decision, I suspect it’ll play out better this time around. Agree or disagree, readers? Let me know your thoughts on this or anything else I’ve discussed here, in the comments!

—Brian Dipert is the associate editor, as well as a contributing editor, at EDN.

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• Apple’s question for the developer: Are you up for an AI do-over?
• Apple’s 2H 2025 announcements: Tariff-touched but not bound, at least for this round
• Microsoft’s Surface Duo: A software evolution testimonial, but for who?

The post The Microsoft-reminiscent iPhone Duo: How much customer holding-and-folding is necessary to keep Apple from folding on the experiment? appeared first on EDN.

Pure-play 8-inch specialty foundry DB HiTek of Seoul, South Korea has completed reliability qualification for its 1200V silicon carbide (SiC) MOSFET process on 8-inch (200mm) wafers. This marks a step in its expansion into the 8-inch SiC foundry market. Building on completion of this qualification, DB HiTek plans to strengthen product development support for customers, secure new customers and accelerate preparations for volume production in 2027...

Altera now provides post-quantum cryptography (PQC) support for Agilex 3 and Agilex 5 FPGAs, helping strengthen system security. The FPGAs’ reprogrammable architecture enables designs to evolve as new threats emerge and security requirements and cryptographic standards change. The devices form a scalable platform for embedded and edge applications by combining performance and power efficiency.

PQC-enabled secure boot authenticates trusted device configurations while protecting long-life systems against future quantum-era threats. A Secure Device Manager (SDM) provides additional security capabilities, including bitstream encryption for IP, physical anti-tamper support, key management, physically unclonable function (PUF) keys, embedded cryptographic cores, and platform attestation.

The PQC-enabled Agilex 3 and Agilex 5 devices are shipping today. Quartus Prime Pro Edition 26.1.1 includes a PQC software flow that simplifies implementation of post-quantum security protections.

Agilex 3 product page

Agilex 5 product page

Altera

The post Altera brings quantum-resistant security to FPGAs appeared first on EDN.

Two 600-V MOSFETs from AOS come in top-side-cooled packages with co-optimized electrical and thermal paths to maximize power density. The AOGT037V60DE2 and AOGT060V60DE2 αMOS E2 Super Junction MOSFETs feature a built-in fast body diode for enhanced robustness and reduced Qrr in high-stress applications.

The AOGT037V60DE2 has a maximum RDS(ON) of 37 mΩ and typical Qg of 146 nC, both at a VGS of 10 V. For the AOGT060V60DE2, the corresponding ratings are 60 mΩ and 85 nC under the same conditions. Both devices provide strong avalanche capability and in-rush current handling with a wide safe operating area (SOA).

AOS combines the αMOS E2 silicon with its GTPAK package to improve thermal performance through a top-side cooling pad, while gull-wing leads enhance board-level reliability. The MOSFETs are designed to prevent self-turn-on for reliable operation under dynamic conditions. Typical applications include rectifiers, solar inverters, motor drives, and industrial power systems using boost PFC, totem-pole PFC, LLC resonant, PSFB, and cyclo-converter topologies.

The AOGT037V60DE2 (600 V, 37 mΩ) and AOGT060V60DE2 (600 V, 60 mΩ) are now available in production quantities with a lead time of 16 weeks. Respective prices are $6 and $3 in quantities of 1000 units.

Alpha & Omega Semiconductor

The post AOS boosts power density with 600-V MOSFETs appeared first on EDN.

A SerDes chipset from EverProX, under its Silicon Line brand, aggregates two simultaneous MIPI D-PHY camera streams, each at up to 10 Gbps, over serialized links. As the first entry in the Silicon Line MIPI Serial Data Link (MSDL) family, the MSDL 20G dual-port chipset extends MIPI D-PHY connectivity to tens of meters.

Comprising the SL8582x serializer and SL8581x deserializer, the chipset overcomes the bandwidth, EMI, and reach limitations of conventional MIPI D-PHY while consuming less than 100 mW per link. It enables low-power connectivity between high-resolution cameras, displays, and processors.

The MSDL 20G supports up to two simultaneous single- or stereo-camera transmissions over one or two serialized links. Integrated VCSEL drivers and a transimpedance amplifier (TIA) enable optical links over tens of meters, while differential copper links can extend up to 2 meters. Typical power consumption is 71 mW per optical link and 87 mW per electrical link, excluding the integrated sideband SerDes.

The MSDL 20G (SL8582x/SL8581x) is sampling now to early-access customers in bare-die or 4×4-mm µBGA-78 packages. Evaluation kits are available now for link validation.

Silicon Line

The post Dual-port MIPI D-PHY SerDes delivers 20-Gbps bandwidth appeared first on EDN.

Marelli and Microchip have announced a display connectivity solution that uses the open-standard ASA Motion Link (ASA-ML) to stream graphics and video from a vehicle’s central computer directly to automotive displays. The companies say the approach can simplify display architectures, reduce system costs, and give automakers greater sourcing flexibility for software-defined vehicles.

Microchip is extending its ASA-ML products from camera connectivity to automotive displays, with Marelli providing the display-side integration. The demonstration uses Microchip’s VS7000 ASA-ML chipset to process and transmit graphics and video generated by the vehicle’s central computer over a high-speed standardized link. Marelli configures and optimizes the ASA-ML deserializer to decode the video stream directly at the display, simplifying the display-side electronics.

The ASA-ML connection supports data rates up to 16 Gbps and incorporates link-layer authentication and encryption. The open standard also enables interoperability among products from multiple technology providers, giving automakers greater sourcing flexibility.

For more information about Microchip’s ASA-ML solutions, visit the ASA Motion Link product page.

Microchip Technology 

Marelli

The post Marelli, Microchip extend ASA-ML to displays appeared first on EDN.

SECO has developed a 5-in. industrial HMI panel and a compact SBC, both based on the Qualcomm Dragonwing IQ-2390 processor. The Compact Vision 5 Dragonwing IQ-2390 and SBC-Dragonwing-IQ-2390 target industrial connected devices for HMI, control, vending, building automation, industrial vision, and other compact embedded applications.

With a quad-core CPU and 1.1-TOPS NPU, the Compact Vision 5 Dragonwing IQ-2390 is designed for applications requiring touch interaction, industrial reliability, and entry-level on-device AI. It integrates a 5-in. (800×480-pixel) touchscreen, 3D GPU, up to 4 GB of RAM, and 16 GB of eMMC storage in a 145.5×102.4×33.4-mm enclosure. The panel-mount unit supports Wi-Fi and Bluetooth and includes MIPI-DSI, RS-232, CAN, Gigabit Ethernet, and USB-C interfaces.

Aimed at custom embedded systems, the SBC-Dragonwing-IQ-2390 provides the same processing, memory, and connectivity as the Compact Vision 5 on a small 47×114-mm board. Both platforms run Clea OS, based on Yocto Linux, providing a software environment for development, deployment, and lifecycle management.

Register for the Early Access Program to receive information on evaluation options and next steps for the Compact Vision 5 Dragonwing IQ-2390 and SBC-Dragonwing-IQ-2390.

SECO

The post SECO pairs Dragonwing with HMI and SBC appeared first on EDN.

Ascent Solar Technologies Inc of Thornton, CO, USA – which designs and makes lightweight, flexible copper indium gallium diselenide (CIGS) thin-film photovoltaic (PV) panels that can be integrated into consumer products, off-grid applications and aerospace applications – has added Tom Bawol as its new director of strategic sales & market development, and Lieutenant General Steve Smith to its Strategic Advisory Board in the role of strategic advisor...

submitted by /u/SpecialistRare832 [link] [comments]

Epiwafer and substrate maker IQE plc of Cardiff, Wales, UK has reported greater-than-expected revenue of £64.6m for first-half 2026, up 43% from £45.3m in first-half 2025, supported by strong demand across all of the firm’s core segments...

Someday, Somehow, I'll buy a solder. submitted by /u/Curious_Deal5981 [link] [comments]

Courtesy of this circuit’s flexibliity, you can select and adjust both, one, or none of the channels of a dual digipot.

One huge advantage that digital potentiometers have over electromechanicals is, of course, the inherent flexibility the electronic interface provides versus the mechanical alternative. Figure 1 shows an example.

Figure 1 The 256-step (8-bit) resolution, dual-channel DPOT U2 can be programmed up/down with single step-per-push or auto-repeat (button held), with operating mode options including channel X or Y alone per switch S2’s position on X or Y, both ganged together with S2 in X&Y, or setting-protected (where accidental button pushing won’t disturb the setting) with S1 in LOCK.

Wow the engineering world with your unique design: Design Ideas Submission Guide

Dual tandom pots have certainly existed for a very long time, and are sometimes extremely useful. Adusting the volume on a stereo sound system, or tuning a two-pole filter, are obvious examples. But when mechanical pots share a common shaft, of course, they must turn in lockstep together forever, whether that suits the application at hand perfectly. Or not.

Figure 1’s circuit allows U2’s dual pots to step together, singly, or not at all as determined by simple switches S1 (SPST) and S2 (SPDT three position with center off). Convenient autorepeat is accessed by holding the desired step UP/DOWN button depressed for longer than a half second.

Which is certainly a step up in flexibility.

Stephen Woodward‘s relationship with EDN’s DI column goes back quite a long way. Over 200 submissions have been accepted since his first contribution back in 1974.  They have included best Design Idea of the year in 1974 and 2001.

Related Content

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• Synthesize precision Dpot resistances that aren’t in the catalo
• Op-amp wipes out DPOT wiper resistance

The post Double DPOT programming: Parallel gang-up, singleton, or none appeared first on EDN.

I couldn’t find any decent DAC/amp combos locally, and importing one would cost a small fortune. After digging into DIY audio designs, I realized I could build one myself for a fraction of the cost and get around 80–90% of the performance of commercial units. Specs: Controller: ESP32-S3 acting as a USB Audio Class (UAC) device. DAC: PCM5102A breakout board fed via I2S. Power Supply: ±12V linear power supply Two NE5532 dual op-amps: Op-amp 1: Stereo buffer stage. Op-amp 2: Stereo gain stage (~3.1x gain). (Opted for this layout to keep wiring simple for my first major soldering project!) Volume Control: Couldn't source 10k dual-gang logarithmic pots locally, so I implemented software volume control with a rotary encoder. Layout: Everything wired to a single star ground point. Sound Impressions: It drives my Beyerdynamic DT 990 Pro (250 ohm) effortlessly. Going from my laptop's built-in jack to this is night and day—it feels like the headphones were practically starving before. Noise floor is pitch black silence with zero audible hum or hiss. Really happy with how this turned out for my first major electronics build. (Note: I’m currently out and forgot to take photos of the back of the amp perfboard, but I can upload solder-side pics once I'm back home if anyone wants to see them!) submitted by /u/supergamer1185 [link] [comments]

Вітаємо ректора КПІ Анатолія Мельниченка з входженням у топ-100 найвпливовіших українців за версією «Фокусу» KPI4U-2 ср, 09/09/2026 - 12:21

A new flash cost calculator helps OEMs identify potential savings and explore alternative storage strategies for flash chips at a time when market conditions are putting growing pressure on memory costs. The calculator reduces component costs by selecting flash capacity closer to what the product actually requires, rather than paying for oversized managed components.

According to Gartner, NAND flash prices are forecast to rise 234% in 2026 with a meaningful pricing relief not expected until late 2027. But much of the industry conversation has focused on supply constraints and component prices, noted Steffan Schumacher, CEO of Tuxera. “The more important question is what engineers can do in response.”

Source: Tuxera

Schumacher added that the opportunity isn’t simply to source a cheaper component today, but to design storage architectures that use flash more efficiently and give manufacturers more choice as costs, availability, and technology inevitably change again. Here, Tuxera’s flash cost calculator gives OEMs greater flexibility in how they design and manage embedded storage.

In other words, the calculator increases sourcing flexibility by opening a wider choice of supported raw flash parts and vendors. It also reduces dependence on a single component roadmap. For instance, a product may need only 4 GB of storage, but manufacturers can face increasingly limited choices at lower eMMC capacities.

If the required capacity is no longer available, OEMs may be forced to move to a significantly higher-capacity alternative, potentially paying for far more storage than the product actually needs. Here, the calculator enables OEMs to move from managed flash such as eMMC to raw NAND. “Manufacturers cannot control NAND prices, component availability or suppliers’ product roadmaps, but they can build greater flexibility into how they use flash,” Schumacher said.

This design flexibility is crucial for manufacturers of automotive electronic control units (ECUs) and zone control units (ZCUs), smart meters, industrial equipment, and medical devices, where the impact comes not only from higher flash prices but also from the capacity options available to them. NAND flash prices and sourcing pressures are also likely to rise in edge AI and physical AI designs because devices will demand more storage and data infrastructure.

This is how the calculator works. OEMs can enter their required capacity, annual production volumes, and production lifetime to estimate potential savings, for instance, from moving from managed flash to right-sized raw flash. Moreover, they can enter their own supplier pricing to reflect their individual purchasing agreements.

The flash cost calculator is available now at Tuxera.com/flash-cost-calculator.

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• Kioxia’s Flash-for-DRAM Initiative Eyes AI Workloads
• Flash vendors show pricing restraint in surging market
• The Truth About Memory Supply, Pricing and What Comes Next

The post Flash calculator promising cost savings, design flexibility appeared first on EDN.

In a significant addition to India’s growing portfolio of home-grown enterprise intellectual property, Novac Technology Solutions, a distinguished leader in technology and AI solutions, has secured an Indian patent for its proprietary innovation, “System and Method for Managing a Project by Integrating Set of Modules” (Patent No. 595218). Designed and developed in India, the platform addresses one of the software industry’s most persistent challenges: fragmented project execution, highlighting the country’s growing role in creating globally relevant enterprise technologies through indigenous engineering and innovation.

Granted by the Indian Patent Office under the Controller General of Patents, Designs and Trade Marks (CGPDTM), the patent provides protection for Novac’s patented invention to enterprise software delivery. The innovation brings together every critical stage of the software development lifecycle, including project estimation, scheduling, project reviews, testing, defect tracking and maintenance, into a unified platform that enables organisations to manage software projects through a connected ecosystem rather than disconnected tools and workflows.

As software development becomes increasingly complex, organisations often rely on multiple tools to manage project estimation, planning, scheduling, testing and maintenance. While each serves a specific purpose, disconnected systems often result in fragmented workflows, manual coordination, inconsistent tracking and limited visibility across teams. Novac’s patented innovation addresses this challenge by integrating the key stages of software project management into a single integrated platform, enabling integrated information flow, stronger collaboration and a unified view of project execution.

A key differentiator of the patented platform is its dynamic scheduling and task-dependency management capability, which automatically updates interconnected tasks whenever changes are made to lower-level activities. This reduces manual intervention, improves planning accuracy and helps organisations improve resource utilisation while adapting to changing project requirements. The platform also integrates testing, defect management and project reviews, providing end-to-end traceability, better governance and timely insights that enable better-informed decision-making throughout the software delivery lifecycle.

Speaking about the patent, Mr. N.S Nanda Kishore, Managing Director & CEO, Novac Technology Solutions said, “Software engineering is becoming increasingly interconnected, yet many organisations continue to manage complex projects through disconnected systems and fragmented workflows. The future of enterprise software delivery lies in creating intelligent ecosystems that connect every stage of the development lifecycle, enabling greater visibility, seamless collaboration and informed decision-making. This patented solution reflects Novac’s continued commitment to engineering innovation by bringing an integrated approach to software project management.”

The patent marks an important milestone in Novac’s innovation journey and further strengthens its intellectual property portfolio. More broadly, it reflects the evolution of India’s technology ecosystem, where companies are increasingly creating proprietary enterprise technologies alongside delivering world-class technology services. As organisations worldwide continue to modernise software engineering and digital operations, innovations developed in India are playing an increasingly important role in shaping the future of enterprise technology.

The post Novac Technology Solutions Secures Indian Patent for Home-grown Innovation Transforming Enterprise Software Delivery appeared first on ELE Times.

Critical Manufacturing, the Industrial Operations Platform company that unites execution, connectivity, analytics and trusted AI, will exhibit at SEMICON India from September 17–19, demonstrating how semiconductor manufacturers can establish connected, data-driven operations that support intelligent production.

Exhibiting in collaboration with ASMPT, Critical Manufacturing will bring its vision of the factory of the future to life, showing how manufacturers can transform operational complexity into actionable intelligence through a unified platform.

India is moving from semiconductor ambition towards ecosystem development, with investment spanning fabrication, compound semiconductors, assembly and testing, advanced packaging and chip design. As new manufacturing capacity is established, companies will need to build digital production foundations that can support quality, traceability and coordination from the outset.

From execution to intelligence

At SEMICON India, Critical Manufacturing will demonstrate how its Industrial Operations Platform extends beyond traditional Manufacturing Execution Systems (MES). MES acts as the execution core within a broader platform that continuously connects production data, analytics and AI, enabling a closed-loop system where insights are generated and acted upon in real time.

For manufacturers developing new semiconductor operations, decisions made at an early stage can shape production performance for years to come. Establishing consistent processes, data structures and traceability from the beginning helps prevent fragmented systems from developing as facilities, product portfolios and production volumes grow.

The platform captures data at source, structures it across equipment, systems and sites, and provides the operational context needed to support informed decisions. This gives manufacturers a foundation that can scale with their operations while maintaining control over quality and production processes.

Experience the Factory of the Future

Visitors will be invited to “step into the factory of the future” through live demonstrations showing how machines, processes and data can be connected across the shopfloor.

The demonstration will highlight how real-time information flows between equipment and manufacturing systems, helping teams understand relationships between process conditions and production outcomes. This supports a shift from reacting to problems towards anticipating and addressing issues before they affect quality, output or delivery.

Together, these capabilities reflect the industry’s transition from digital transformation to intelligence-driven operations. By incorporating connectivity and manufacturing intelligence from the beginning, manufacturers can support continuous learning and improvement while avoiding isolated systems that later become difficult and costly to integrate.

“India has an important opportunity to build modern semiconductor operations without being constrained by the fragmented legacy systems found in many established manufacturing environments,” said Weng Keong Lan, Managing Director of Critical Manufacturing Malaysia, responsible for India’s Go-to-Market. “As new facilities and capabilities are developed, manufacturers can put the right execution, connectivity and data foundations in place from the outset rather than attempting to integrate them later.”

AI copilots for smarter decision-making

A key feature of the demonstration will be Critical Manufacturing’s AI Copilots, embedded directly within the MES environment. The copilots enable users to interact with manufacturing data using natural language and generate dashboards, charts and insights without complex queries or specialist expertise.

By making production information easier to access and interpret, AI Copilots can help engineers, operators and decision makers investigate changing conditions, identify trends and respond with greater confidence.

A joint approach with ASMPT

The joint presence with ASMPT reinforces the importance of considering manufacturing equipment and software as part of one coordinated production environment. Closely connected equipment and software ecosystems can provide greater coordination, control and performance across the production lifecycle.

Lan added, “At SEMICON India, we will demonstrate how a unified Industrial Operations Platform can help manufacturers standardise processes, establish end-to-end traceability and maintain control as production scales. Building these capabilities early will be essential if India’s growing semiconductor ecosystem is to translate investment into reliable, high-quality manufacturing.”

Experience the platform in action

Visitors to SEMICON India 2026 can experience live demonstrations at the ASMPT booth 1346, where Critical Manufacturing experts will showcase how the Industrial Operations Platform supports connected and intelligent semiconductor manufacturing.

Attendees are invited to explore how the platform can help manufacturers establish scalable operations, maintain production traceability and manage increasing complexity as facilities and output grow.

The post Critical Manufacturing to Showcase MES-Powered Industrial Operations Platform for Intelligent Semiconductor Manufacturing at SEMICON India 2026 appeared first on ELE Times.

The demand for low-voltage clock drivers continues to grow with the rapid adoption of advanced FinFET process nodes used in high-performance FPGAs, SoCs, AI accelerators and next-generation CPUs. Printed circuit board designers face increasing challenges due to the limited availability of standard 1.2V LVCMOS clock buffers and level-translating buffers capable of converting higher-voltage clock signals to the lower-voltage levels required by these advanced devices. Conventional approaches that rely on discrete components and voltage-divider techniques can compromise signal integrity and clock duty cycle accuracy while increasing board complexity and component count.

Microchip Technology has introduced the SY757xx family, a comprehensive portfolio of 1.2V-output LVCMOS clock buffers, designed to address these challenges. The new devices simplify system design by eliminating the need for traditional discrete component implementations while delivering ultra-low additive jitter performance. To provide flexibility for supporting legacy board power supplies and different clock-source voltage levels, the devices support a broad range of supply voltage (VDD) and a wide operating frequency range. The SY757xx family enables ultra-low additive jitter clock distribution while maintaining the high clock resolution and signal integrity required for today’s high-speed FPGA, SoC and CPU platforms.

“Our SY757xx family of clock buffers helps customers overcome the growing clock distribution challenges associated with next generation high-performance FPGA, SoC and CPU platforms,” said Maamoun Abou Seido, appointed vice president of Microchip’s timing and communications business unit. “By combining ultra-low additive jitter performance with broad VDD and wide frequency support in a single-chip solution, the SY757xx devices simplify board design, reduce component count and help customers maintain the signal integrity and timing accuracy required in today’s high-performance computing applications.”

Microchip’s SY757xx family strengthens the clock buffer’s role as a critically important SoC and FPGA interface for clock distribution and clock fanout functionality in application platforms where signal integrity is paramount. These platforms demand high-speed parallel processing, hardware reconfigurability, low latency and efficient real-time computing. These capabilities are required for applications ranging from embedded vision and video processing to AI/ML acceleration, industrial control and IoT, networking and communications, and signal processing and embedded systems.

Launching three products in production and eight that are sampling in limited volumes, the family spans a wide array of configurations in three space-saving packaging options. The devices protect against clock distortion across a 0 Hz to 250 MHz frequency spectrum while also offering a broad range of power supply input and output options across the 1.2V to 3.3V voltage-translation input range. This includes a single-chip option that reliably interconnects 3.3V components to FPGAs and SoCs with a 1.2V clock signal requirement. Additive jitter is as low as 26 femtoseconds (fs).

Compared to traditional discrete component solutions for these FPGA and SoC applications, the Microchip buffers simplify design and reduce bill-of-materials costs while helping to optimize AC coupling and biasing and maintain signal integrity. Voltage dividers using discrete components may not provide adequate design margin and can degrade signal integrity by causing duty-cycle distortion.

Microchip clock buffers complement the company’s comprehensive range of flash-based FPGAs and SoC FPGAs spanning ultra low density to mid-range density devices. These and other Microchip products that range from microcontrollers and analog components to power management, timing, connectivity and memory devices are pre-engineered and validated to enable a simplified, lower-risk and more holistic approach to system design.

The post Microchip’s 1.2V Clock Buffers Link Latest SoCs and FPGAs with Higher Voltage Components appeared first on ELE Times.