Збирач потоків

"This model was specifically designed for microelectronics, eliminating the image lag common in cheap USB microscopes connected to a PC." submitted by /u/dataclone82 [link] [comments]

Here's some animations I made of transistors turning on and off. In order, we have an NPN BJT, n-channel MOSFET, and finally an n-channel JFET. The red and blue dots represent electrons and holes, and white flashes are recombination events. The density of dots is proportional to the actual density of charge carriers. In the first set of animations, the velocity of the dots is equal to the velocity obtained by summing the diffusion and drift currents and dividing by the charge density, but diffusion is not explicitly shown. In the second set of animations, the dots undergo diffusion and drift, and this makes it a more correct depiction of carrier motion. The drawback is of course that the jiggling makes it more visually confusing. I made these with my semiconductor simulator (https://brandonli.net/semisim/). I also have higher quality versions of the animations here. submitted by /u/thepowderguy [link] [comments]

Global smartphone shipments fell 4% year-on-year in second-quarter 2026 as the ongoing memory crisis disrupted supply and pushed up component costs, according to Omdia’s Smartphone Horizon Service for July 2026 (sell-in shipments). The current dynamic has created severe market polarization, reflecting stark differences in vendors’ mitigation strategies, which vary according to their priorities, scale, price-band focus, and core audience demographics, notes the market research firm...

submitted by /u/brolpe [link] [comments]

If you periodically need to see the frequency response of a circuit, this easy, inexpensive project can help you out.

Editor’s note: This is a two-part series on how to create a noise generator with an adjustable bandwidth and a consistent amplitude. The previous entry: 

• Making noise with a BANG, part 1: Concept and hardware

The operation and firmware

As I mentioned last time, I was able to reuse much of the firmware from a previous Design Idea project. The Arduino C code consists of three files. One is the initialization code for the DAC, while another contains code for the LCD/touch screen operations. The third is the main code. Let’s look at these one at a time.

Wow the engineering world with your unique design: Design Ideas Submission Guide

The DAC initialization code does just what it says and is designed to get a DAC output as fast as possible. The LCD/touch screen code is the largest piece of the software puzzle. Before discussing it “under the hood”, let’s take a quick look at the some of the LCD/touch screen display outputs. Figure 1 shows most of the screens used in the BANG.

Figure 1 The BANG LCD screens are designed to be both intuitive and informative.

The first screen you see after the power-up splash screen is what I call the main screen. It allows you to select an output, but let’s hold off discussing this implementation aspect in detail until later. For now, just understand that on power-up, it will default to the noise output on the AC and DC BNC connectors.

Also on the main screen is the “Change Bandwidth” selection that will allow you to set the bandwidth for the noise (noise bandwidth is measured from 0 Hz). When you press “Change Bandwidth”, the screen will change to the keypad and allow you to enter your desired number. Note that if you exceed the maximum 225 kHz it will default to 225 kHz. Similarly, if you enter a number less than the minimum of 500 Hz it will default to 500 Hz. After hitting “ENTER” you will return to the main screen.

On the main screen, selecting “About” will take you to a screen showing lots of interesting information such as your selected bandwidth and the gain it will apply to the noise during filtering. You’ll also see the sample rate (which is fixed), firmware version, and (for those that are interested) your current IIR filter’s coefficients. Next, it shows the battery voltage and charge level. (If you do not have a battery installed you may see fully charged numbers as it is instead reporting the charger voltage. There is a #define in the top portion of the main code that you can set to “false” instead, in which case this line won’t be displayed if you don’t have a battery installed.) The last item shown is the incoming USB voltage.

The last screen shown in Figure 1 is the one displayed when “RUN” is selected on the main screen. If you see this screen, the noise signal is being generated and is being output to the BNC connectors.

Let’s talk a little about the code for creating these screens. It’s a bit long and mostly involves setting colors, drawing boxes, selecting fonts, aligning text in the box, and capturing positions of key presses. Almost all of this is done using higher level calls to the downloadable “Adafruit GFX Graphics Library”. Here’s a short example of the code showing how to display the word “BANG” in red against a grey background:

tft.fillScreen(tft.color565(0xe0, 0xe0, 0xe0)); // Grey tft.setFont(&FreeSansBoldOblique50pt7b); tft.setTextColor(ILI9341_RED); tft.setTextSize(1); tft.setCursor(13, 100); tft.print("BANG");

The third C file is the main code, which mostly directs calls to the correct LCD screen, executes miscellaneous housekeeping operations, and (of course) generates the noise signal, the latter starting with the bandwidth selected from the touchscreen. Using this value, we generate the coefficients for a digital 2-pole low-pass Butterworth IIR filter. The next step is to get a value for the gain we will be using on the noise signal. This is done by calling a function that has the bandwidth as an input and returns a gain number. Here is the code for that function:

//****************************************************** // AGC * // Does an automatic gain adjust to the * // random number amplitude. Run once after * // startup or a change in the LP filter. * //****************************************************** float AGC(float cutoff_freq) { float agcGain = 1; // Calculate agc gain based on the set bandwidth if (cutoff_freq >= 50000) agcGain = 31.0 * pow(cutoff_freq, -0.292); // for 225kHz to 50kHz else agcGain = 393.769851 * pow((cutoff_freq - 97.8961702), -0.524598029); // Curve fit of freq vs. amplitude data gainOffset = 1024.0f * (2.0f - agcGain); // Adjustment for shift in DC level return agcGain; }

You’ll see that there are two different formulas used for agcGain, based on whether the bandwidth selected is greater than 50 kHz. This dual-equation method makes curve fitting more accurate. These formulas were derived from data I generated by setting a bandwidth and then adjusting the gain in code to get a desired amplitude. The data was then used to generate curve-fitted equations (kudos to Standards Applied Engineering Tools, whose Curve Fitting Online utility gave by far the most accurate curve fit of all the tools I found and tried). Later, I’ll also detail how AI did (or, maybe more accurately, didn’t) with generating the same curve fit equation(s).

You can see from the second equation that the power function is based on -0.52; roughly the square root of 2 as we talked about at the beginning of part 1 of this series. The reason it is not exactly a square root of 2 function is because some noise, beyond the cutoff frequency of the 2-pole digital IIR filter, still exists in this roll-off portion of the filtered signal – i.e., it is not a brick wall filter.

Figure 2 shows a graph of this gain vs. bandwidth selected.

Figure 2 This graph shows the linear gain vs. bandwidth result for the equations used in this design.

With the bandwidth entered and the gain calculated, it is then incorporated into the coefficients of the lowpass IIR filter. This approach optimizes the calculations; we don’t need to add another multiplier inside the speed-optimized output loop.

Ok: we’re now ready to generate the noise signal. When the user selects “RUN”, the code enters a tight loop. In it, we get a random number from the true random number generator (TRNG). Next, we run the number through the IIR filter, which also applies the gain. Then, the lower 12 bits of this number are sent out of the DAC. (A note: the DAC has a slew rate of somewhere around 1 µS per volt to minimize the effect. The number is scaled to keep the signal mean coming from the DAC to around 1/2 Vcc.) This loop continues until the user selects “STOP”.

Those of you following closely may be thinking something along the lines of the following right now: “Another way to generate a noise signal of a given amplitude is to simply generate the random samples at a lower sample rate”. The downside of this alternative approach is that the analog reconstruction filter would need to be adjusted to follow the sample rate, which seems like a much more difficult analog design task. Also, we would still need to perform the digital low-pass filtering for anti-aliasing.

It’s time to look at the output of the BANG. Figure 3’s scope display shows the AC output time domain signal on the left and the FFT on the right. The BANG is set to give an output with a 25 kHz bandwidth.

Figure 3 This scope plot shows the BANG output with a 25 kHz bandwidth setting.

The enclosure

The BANG’s enclosure derives from a custom 3D-printable model (see later for a file-download link). It includes three parts: the main body, the base/PCB mount, and a stylus for the touchscreen. The main body’s download is modeled with two filament colors but can alternatively be printed in one color. If printed in a single color, the text is still readable, as it is also embossed. The base holds a 120 mm x 80 mm PCB. I used a protoboard as there were a minimal number of parts and was faster to build than designing and waiting for a custom PCB.

Wait, there’s more

While TRNGs are common in larger processors, they’re more rare in smaller micros. Most compilers therefore use pseudo-random number generators instead. But since this system was generating 32-bit true random numbers, it occurred to me that such a data stream may also have other uses, such as in cryptography systems, input data for testing code, a “seed” for pseudo-random number generators, or even helping you select “picks” for playing the lottery.

More broadly, it seemed like a waste to not have a way to output these generated numbers. So, I included support for this feature, via USB, in two format options – ASCII data or binary data. The desired format can be chosen from the “Select Output” LCD page shown in Figure 4 (as mentioned earlier, the power-up default is the noise generator output via the analog BNC connectors).

Figure 4 The design includes support for outputting the 32-bit true random numbers generated, over USB and in two format options.

Note that although the data is 32 bits, it can be sliced or appended to form any size random number you require. For example, you can use one bit of the 32-bit source, which will still be random, or you can append two 32-bit output numbers to create a truly random 64-bit number.

Comments on AI use

I only used AI (and then only experimentally) for one part of the project, the curve fitting of test data to create the equation(s) for the AGC. The result was…interesting. I’d already developed the earlier discussed frequency-to-gain equations for the AGC algorithm, but I thought I should also try AI to see what it came up with. I fired up Microsoft Copilot and gave it the frequency vs gain data that I’d already created by iteratively setting a frequency and then adjusting gain in the code until I got the fixed amplitude I was looking for.

Copilot noted that it looked like a power equation – good. Then it gave me a very simple equation: gain = 1.96 * freq-0.52 . Wow, I thought, much simpler than the equations I’d came up with. But it seemed too good to be true, so I got out a calculator. At a frequency of 10 kHz the gain should be around 3. When you make the calculation on the AI’s formula you get around 0.016. When I asked Copilot to use its equation on 10 kHz, it said the gain would be 3.68. Another AI with a case of cognitive dissonance. Perhaps obviously, I used the other formula instead!

Conclusion

This is a fairly easy and inexpensive project to build. If you periodically have the need to see the frequency response of a circuit, it may help you out.

Note that the schematic, code, 3D print files, Arduino software, links related to various parts of the project, and additional notes and pictures on the project’s design and construction can be downloaded for free at the MakerWorld website.

Damian Bonicatto is a consulting engineer with decades of experience in embedded hardware, firmware, and system design. He holds over 30 patents.

Phoenix Bonicatto is a freelance writer.

Related Content

• Making noise with a BANG, part 1: Concept and hardware
• A digital filter system (DFS), Part 1
• A digital filter system (DFS), Part 2

The post Making noise with a BANG, part 2: Software, integration and operating results appeared first on EDN.

Very simple circuit - i had a bunch of these charger/booster modules laying around and decided to learn about the dangers of bare 18650 batteries. Excited to do more. submitted by /u/Willy_V3 [link] [comments]

I wanted to modify my PS3 controller to USB-C, but it used a through hole connector. Not a problem! submitted by /u/circuitsable [link] [comments]

At the beginning of July, epiwafer and substrate maker IQE plc of Cardiff, Wales, UK appointed Robert Dennehy and David O’Carroll as non-executive directors, representative of MACOM Technology Solutions Inc of Lowell, MA, USA under the board appointment agreement between the two firms announced on 28 May. MACOM has a beneficial interest in IQE, representing 11.5% of IQE’s issued share capital...

Epiwafer and substrate maker IQE plc of Cardiff, Wales, UK has secured a multi-year production order worth $14m from a strategic global technology customer...

Conflicting application requirements can turn system-on-chip (SoC) design into a hall of mirrors. In particular, choosing a process technology can become a maze of contradictions and puzzles.

Then there is higher speed, which generally requires more power. Next, the technology that delivers the necessary performance and power efficiency may be unacceptable due to cost or supply-chain constraints.

However, a design partner who can customize foundational IP—logic cell libraries or memories—and shepherd the custom cells through the design flow, manufacturing, and testing can often bring an SoC design safely through the maze.

One recent engagement with a crypto-mining client illustrates the importance of custom foundational IP in resolving these trade-offs. And it also shows how the impact of custom cells can ripple through the design flow, from tape-out and beyond, emphasizing the need for a design partner with expertise in both IP creation and SoC implementation.

A unique application

Crypto mining is the process of generating new coins in a cryptocurrency. For many such currencies, including the ubiquitous Bitcoin, the process requires a so-called proof-of-effort: a computationally intensive task with no known shortcut.

Factoring a huge number is an example: the only way to find the prime factors is to keep trying new prime numbers. In principle, the cryptocurrency’s governors would publish a large number, the crypto miners would set to work searching for factors, and the first miner to publish all the factors would receive a new coin.

Obviously—luck aside—the miners with the most computing power will get the most coins. That leads to a computing arms race. Less obviously, this game consumes a tremendous amount of energy—one reason China attempted to ban crypto mining in 2021. To make the enterprise profitable, the miners need to stay on the leading edge of computing performance while minimizing capital investment and operating costs. These costs are dominated by power consumption.

Under those pressures, crypto miners quickly migrated from farms of CPU-based server boards to FPGAs, and then to vast arrays of ASIC hardware. Today, miners demand high computing performance, very low power consumption, very low front-end investment, and low unit cost—a set of contradictory requirements.

The mining SoC

This was the scenario presented to us by our crypto-mining client. Together, we determined that the lowest-cost approach that met their performance and power requirements would be a FinFET process with an extremely low operating voltage.

In fact, we had fully characterized 0.5-V logic libraries for this process. There was just one problem. The library could not meet the client’s speed requirements. The problem, it turned out, was the registers. This library, like virtually all standard logic libraries, uses a conventional master-slave D-type flip-flop. But it could not operate reliably at the required clock frequency. So, we decided to create a custom D-type flip-flop cell.

The D flip-flop

The D-type flip-flop has been a fundamental element in digital design for decades, used for everything from state machines to registers (Figure 1).

Figure 1 Schematic highlights a 32-bit D-flip-flop used to implement D-type registers. Source: Faraday Technology

The cell’s performance and stability are vital to any RTL design. The conventional cell design uses two stages and two clock phases. The first stage captures the input data on one clock edge, and the second stage latches the captured data on the second clock edge. In most designs, this requires routing two very accurately timed clock phases to every flip-flop cell.

We believed we could eliminate one of these clock signals and achieve a higher operating speed. Eliminating one clock would also substantially reduce the cell’s power dissipation and could reduce area and routing congestion.

But could we accomplish this, and hit the required frequency? And could we do all that while sacrificing the inherent stability of the dual-phase clock approach and still have a device that is resistant to process variations and electrical upset?

The TSPC flip-flop

Our exploration of circuit designs led to the development of the true single-phase clock (TSPC) D-type flip-flop (Figure 2).

Figure 2 Schematic of a traditional positive-edge triggered TSPC flip-flop showing how a TSPC flip-flop would meet the customer’s power requirements. Our proposed circuit design allowed the TSPC flip-flop to also operate over the necessary frequency range. Source: Faraday Technology

However, circuit design and proof of concept were just the beginning. We fully simulated the circuit in SPICE to understand the layout and sensitivities of this novel cell. We needed to characterize the TSPC flip-flop not only in isolation but also in a dense layout surrounded by other cells, under marginal, noisy clocks, and process variations. At last, we reached our goals for both performance and reliability.

The SoC design using our TSPC flip-flop met our crypto-mining client’s speed requirements. The cell also achieved a 40% reduction in power at rated speed compared to the conventional D-type flip-flop cell it replaced. It reduced the area by about 7%. And from a functional perspective, the TSPC cell was simply a normal D-type flip-flop.

But our detailed characterization of the cell revealed differences in the new device’s operating characteristics. These differences would influence the implementation flow for the SoC.

The cell in use

One unique characteristic of the TSPC cell influences front-end design, specifically power management planning. The single-phase clock for the TSPC flip-flop must not stop during operation, or the flip-flop state may be lost. This places significant limits on the use of power-management techniques such as clock gating and clock throttling. A design that interrupts the register clock must tolerate an unpredictable state when the clock resumes.

Other special characteristics of the cell further influence downstream design. For example, the cell is quite sensitive to clock signal integrity. This requires careful, skilled planning of clock networks from the outset and equally careful routing of clock trees. Conventional clock-tree synthesis tools may not deliver the necessary signal quality across all flip-flop instances, resulting in unreliable operation.

The cell is also sensitive to process variations, even at a local level. This issue can impact yield, but it can be overcome by careful placement during logic layout. We generally use manual insertion to instantiate the TSPC cells, as we have found them unsuitable for use with synthesis tools. Once the cells are placed, routing constraints are relatively minimal. The foremost issue is to maintain signal integrity on the clock lines.

Timing analysis is straightforward, of course, using the TSPC cell’s timing data. Signoff is also conventional—with the enhanced attention to clock integrity. Thanks to our exhaustive characterization and refinement of the cell design, there are no special process corners to be investigated. During test, some changes to the test vectors may be helpful to inspect the unique behavior of the cells.

A new degree of freedom

SoC designers are used to trading off power, speed, and process to meet design requirements. But sometimes no setting of these knobs will achieve the desired result. Our crypto-mining client faced this challenge: running an affordable, available FinFET process at 0.5 V would achieve all design goals except maximum speed. But consuming more power or moving to a more advanced process node in exchange for more speed was not an acceptable trade-off.

The solution was to move outside the power-performance process box with customized foundational logic. Faraday determined that we could meet the client’s needs with only one custom cell—a novel D-type flip-flop design. But once characterized, we found that the cell would place significant demands on the implementation team, from power planning through test design (Figure 3).

Figure 3 To reduce power consumption, we used a TSPC circuit to replace a master-slave flip-flop; but TSPC has an operating frequency limit, so we proposed a solution to this limitation. Source: Faraday Technology

The TSPC flip-flop thus could have become only academic exercise. However, it became an out of the box solution here. Today, the crypto-mining SoC is in volume production and meets all design requirements. The chips are out there, searching for coins and earning their living.

Jason Kang is director of IP technology at Faraday Technology. He has over 20 years of experience in fundamental IP development, PDK integration, and IP model characterization. His expertise lies at the intersection of advanced-node design flows, device modeling, and EDA methodologies, with a strategic focus on silicon implementation and the emerging field of AI-driven design automation.

Related Content

• Bitcoin ASIC in Chips-to-$ Race
• Design Houses Bank on AI, Bitcoin
• Crypto Mining ASIC Goes Deep Sub-Threshold On 3 nm

The post Crypto mining SoC unearths a need for custom IP appeared first on EDN.

The Indian Army has initiated the process to acquire indigenous long-range, one-way attack drones capable of striking targets up to 1,000 km away, as it looks to strengthen its deep-strike capabilities with AI-enabled systems. The procurement is being pursued under the Long Range Loiter Munition (LRLM) programme through the Make-II route of the defence acquisition policy.

The procurement is being pursued under the Long Range Loiter Munition (LRLM) programme through the Make-II route of the defence acquisition policy. The Army is looking for drones that can accurately engage targets at a range of 1,000 km, operate in GPS-denied environments and feature artificial intelligence-enabled targeting capabilities. The platform should be capable of carrying a 25-kg warhead with a 50-metre kill radius, fly at altitudes above 5,000 metres and achieve speeds of at least 400 kmph.

Under this framework, private companies will fund their own research and development, while the Army will procure the systems if they meet the required technical specifications. While the exact order size has not been finalised, the armed forces are expected to require thousands of one-way attack drones across different operational ranges.

The post Indian Army Seeks Indigenous AI-enabled Attack Drones with 1,000-km Strike Range appeared first on ELE Times.

India has launched an ambitious programme to build indigenous high-altitude airships capable of conducting long-duration surveillance and intelligence-gathering missions, with several private companies expected to compete for the project. The project is being executed under the government’s Make-I procurement framework, which allows the Centre to fund up to 70% of research and development costs for selected industry partners.

The project is being executed under the government’s Make-I procurement framework, which allows the Centre to fund up to 70 percent of research and development costs for selected industry partners. As per The Economic Times, the Defence Acquisition Council (DAC) approved the programme in February, with the overall project estimated to cost around Rs 15,000 crore, including prototype development and procurement of multiple systems.

The proposed airships are expected to remain airborne for months at a time, enabling persistent intelligence, surveillance and reconnaissance (ISR) operations. The Indian Air Force’s Directorate of Operations (Remote) is overseeing the initiative and aims to develop Air Ship-based High Altitude Pseudo Satellites (AS-HAPS). The platforms are expected to operate at altitudes exceeding 20 kilometres, carrying advanced payloads for optical surveillance, electronic intelligence (ELINT) and long-range communications.

Alongside the airship initiative, the Defence Ministry is also pursuing the development of fixed-wing High Altitude Pseudo Satellites that can take off conventionally and undertake extended surveillance missions.

The post India Launches Rs 15,000 Crore Project to Build Indigenous Stratospheric Airships for High-Altitude Surveillance appeared first on ELE Times.

Continuing its aggressive order book expansion, Bharat Electronics Limited (BEL) has secured fresh contracts worth Rs 572 Crore. This order outlines BEL’s sustained order inflow. The Rs 572 Crore win highlights BEL’s dominance in the domestic defense electronics segment. This announcement highlights BEL’s strategic alignment with the country’s defense roadmap.

BEL remains a primary beneficiary of the ‘Atmanirbhar Bharat’ initiative in the defense sector. The dual triggers of steady order inflow and an upcoming earnings report place the defence PSU in a critical watch zone for institutional and retail investors alike. This multi-crore order effectively underscores the consistent demand for its core products.

BEL’s ability to secure mid-sized orders consistently outside of major multi-billion-dollar platform contracts is a testament to its diversified electronics portfolio. While the market often focuses on mega-orders, these recurring sub-Rs 1,000 Crore wins provide high-margin stability. We view the timing of this order—just two weeks before earnings—as a positive sentiment booster, though the core focus remains on execution efficiency which will be detailed in the Q1 disclosures.

The Indian defense electronics market is evolving from basic radio communication to advanced electronic warfare and radar systems. BEL, as a dominant PSU, holds nearly 60% of the market share in electronics for the tri-services. Competitors from the private sector are emerging, but BEL’s manufacturing scale and R&D integration with DRDO provide a significant moat.

The post Bharat Electronics Wins ₹572 Crore Defense Order appeared first on ELE Times.

Випускниця ФМФ Олександра Парій: "Фізика навчила мене не боятися складних систем" kpi вт, 07/14/2026 - 12:00

In a bid to create India’s first backward-integrated private-sector capability of its kind, Adani Defence & Aerospace, the defence and aerospace arm of Adani Enterprises Limited (AEL) has announced a defence infrastructure project worth Rs 2,500 crore to establish South Asia’s largest missile manufacturing plant in Shivpuri, Madhya Pradesh. This project will design and develop an advanced missile ecosystem with composite propellant and Trinitrotoluene (TNT) production at a single location.

Strengthening India’s defence manufacturing ambitions and the vision of Aatmanirbhar Bharat, this project marks one of the most significant private investments in India’s defence sector. It will enhance India’s capabilities in missile production, advanced weapon systems, precision-guided munitions, and defence technologies.

The facility will strengthen India’s indigenous missile capabilities, supporting the operational requirements of the Indian Armed Forces while advancing long-term defence preparedness. It is slated to accelerate the transition of DRDO-developed indigenous missile systems from successful trials to serial production.

The investment is predicted to generate 5,000 direct and indirect skilled jobs in India, providing employment opportunities across different areas such as engineering, quality assurance, logistics, testing, maintenance, and support services. Beyond employment, the investment is likely to accelerate the supply of precision engineering products, electronic components, advanced materials, tooling, software, and testing equipment.

Since 2020, Adani Defence & Aerospace has developed a robust small arms ecosystem in Gwalior, improving the state’s contribution to India’s defence manufacturing capabilities. From this manufacturing facility, weaponry like pistols, light machine guns, carbines, assault rifles, and other advanced small arms systems are being supplied to the Indian Armed Forces. Backed by the support and guidance of the state government, the Gwalior complex has emerged as a key pillar in India’s drive for self-reliance in defence production.

This announced project under defence will combine advanced manufacturing technologies, automated production systems and globally benchmarked safety standards to support multiple missile programmes simultaneously. Designed to meet the requirements of the Indian Armed Forces as well as trusted international partners, it will strengthen India’s strategic defence industrial capabilities while reinforcing the country’s position as a reliable supplier of precision-guided munitions.

The post Adani Defence Announces India’s Largest Private Missile Manufacturing Hub, Invests Rs 2,500 Crore appeared first on ELE Times.

Інтелект молоді. Раціональне природокористування та новітні енергоефективні технології Інформація КП вт, 07/14/2026 - 11:04

29-й випуск офіцерів ІСЗЗІ КПІ ім.Ігоря Сікорського kpi вт, 07/14/2026 - 11:04

Texas Instruments (TI) (Nasdaq: TXN) today introduced the industry’s
highest-cell-count battery monitor with an integrated electrochemical impedance spectroscopy
(EIS) engine, bringing predictive intelligence, comprehensive data and real-time diagnostics to
battery monitoring in electric vehicles (EV) and energy storage system (ESS) applications.
The BQ79826Z-Q1 battery monitor enhances safety and extends battery life by detecting
potential failures from within battery cells. The single chip delivers the highest-cell-count
monitoring in its class, tracking up to 44% more channels than previous generations. With this
increase in channels, the device significantly decreases the number of components required in a
battery pack, reducing system complexity and cost without compromising reliability. TI is
showcasing this innovation at the 2026 Power Conversion, Intelligent Motion Expo and
Conference (PCIM), June 9-11, in Nuremberg, Germany.

“The electrification of transportation and the rapid expansion of energy storage are redefining
what battery performance must deliver, and as a leader in battery management technology, TI is
uniquely positioned to meet that challenge,” said Wenjia Liu, vice president and general
manager, battery management systems (BMS) at TI. “Our high-cell-count battery monitor with a
built-in EIS engine helps ‘shine a light’ inside battery cells, delivering rich chemical-state data
that enables systems’ software to make informed, real-time decisions on safety and performance
of the battery pack, allowing engineers to address the most critical challenges in battery
management.”

Delivering safety and performance with EIS technology
Just as an electrocardiogram (EKG) monitors the heart, EIS monitors a battery. It delivers
continuous, real-time insight that reveals the battery’s health and warns of issues before they
become critical. Integrated EIS technology enables the BQ78926Z-Q1 to detect fault conditions
earlier – from inside the cells – helping maintain safety and notifying passengers of potential
vehicle hazards such as thermal runaway.

These same benefits extend to ESSs, where reliable battery monitoring is critical to meeting the
growing power demands of artificial intelligence data centers. As effective storage solutions
become increasingly vital in the grid-to-gate ecosystem, EIS gives engineers real-time visibility
into the state of charge and state of health of each battery cell, regardless of system size.

Maximizing efficiency with industry-leading cell count
The performance of an EV or ESS is fundamentally affected by the quality and efficiency of its
batteries. The BQ79826Z-Q1 supports up to 26 cells per device, eight more than any competing
solution, setting a new industry standard. Fewer monitoring devices means a lower bill of
materials, simplified architecture and reduced board space requirements, translating to
meaningful cost savings per channel without sacrificing quality or reliability.
When paired with the BQ79881-Q1 pack monitor and optional TI communications bridge, these
devices create a powerful chipset that works across different module sizes, battery chemistries
and mechanical designs, giving engineers the flexibility to design once and deploy everywhere.
This scalability reduces engineering overhead and accelerates time to market for automotive and
energy storage designers.

Calculating charge readings with the best-in-class accuracy
With a voltage accuracy of <2mV across a full temperature range of –40°C to +125°C, higher
resolution analog-to-digital converters and ultra-low noise, the BQ78926Z-Q1 enables more
accurate state-of-charge calculations, directly addressing one of the biggest concerns for EV
drivers: range anxiety. Utilizing EIS technology, this device enables more accurate temperature
and state-of-charge estimation, helping designers achieve longer battery life and faster charging
without compromising battery health. With an EIS measurement time that is five times faster
than previous solutions, this device delivers the highest functional safety voltage reading per cell.
Compliance with Automotive Safety Integrity Level D and International Organization for Standardization 26262 gives designers a smarter, more efficient path to safer, longer-lasting
batteries.

Innovating what’s next in power at PCIM 2026
Visitors to PCIM can see new products and solutions from TI that are enabling engineers to
innovate what’s next in power in Hall 7, Booth No. 652. The new BQ79826Z-Q1 battery monitor
will be featured in an EIS-enabled BMS reference design, alongside other innovations such as an
11kW single-stage bidirectional onboard charger, a 50kVA solid-state transformer cell stack with
Ethernet and Fast Serial Interface communication and short-circuit protection for silicon carbide
power metal-oxide semiconductor field-effect transistors with technology from Flex.

The post TI brings intelligence to battery management systems with industry's highest-cell-count EIS-enabled battery monitor appeared first on ELE Times.

Infineon Technologies AG (FSE: IFX / OTCQX: IFNNY) and
LS ELECTRIC have signed a Memorandum of Understanding (MoU) to collaborate on high-
efficiency direct current (DC) power infrastructure solutions for AI data centers and next-
generation power grids.

Rapid advancements in AI, the resulting increase in data center power demand and the
expansion of digital infrastructure are driving the need for efficient power distribution
technologies. At the same time, power grids are evolving into increasingly complex,
distributed networks, accelerating the adoption of DC-based power systems. Accordingly,
the two companies will collaborate on key technologies to enhance energy efficiency,
system performance and scalability in next-generation power infrastructure.

“The increasing electricity demand, especially from AI data centers, is reshaping the way
power is generated, distributed and consumed," said Andreas Weisl, Executive Vice
President and Chief Sales Officer of Industrial & Infrastructure at Infineon. "High-efficiency
DC architectures will play a key role in addressing increased energy demand while
improving overall system performance and sustainability. By combining Infineon's
semiconductor expertise with LS ELECTRIC's strength in system integration, we are well
positioned to accelerate the development and deployment of next-generation DC power
infrastructure.”

“The importance of high-efficiency DC power technologies is growing more than ever with
the expansion of AI data centers and next-generation power grids," said Kil Young Ahn, Vice
President and Head of Production and R&BD at LS ELECTRIC. "Through our collaboration
with Infineon, which possesses worldwide-leading power semiconductor technologies, we will strengthen our competitiveness in core DC power infrastructure solutions and will evolve
into a total solutions provider leading the global AI data center market and future power
markets.”

The collaboration will focus on key DC infrastructure areas, including power conversion
systems for energy storage systems, solid-state transformers (SSTs) and solid-state circuit
breakers (SSCBs). SSTs are advanced, semiconductor-based power conversion devices
that can be up to 30 percent 1 smaller and lighter while offering higher efficiency compared to
conventional copper and iron-based transformers. SSCBs use semiconductors and smart
algorithms to protect electrical circuits from damage caused by short circuits or overloads.
They interrupt the flow of current and operate on the microsecond scale to improve system
stability and protection. These semiconductor-based solutions are becoming increasingly
important in high-density power environments such as AI data centers. The collaboration
aims to improve power and voltage conversion efficiency while enhancing the stability and
reliability of next-generation DC power systems.

Under the provisions of the MoU, Infineon will support the development of high-efficiency,
high-performance DC power infrastructure systems with its broad semiconductor portfolio
that includes power semiconductors, microcontrollers and power control solutions. LS
ELECTRIC will leverage its expertise in power systems and industrial automation to drive
system-level integration and implementation. Together, the two companies will align
technology roadmaps and advance co-development efforts to capture growth opportunities
in the next-generation energy infrastructure market.

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