Збирач потоків

From a Jena-based spin-off to a globally sought-after test and inspection specialist.

In May 2026, GÖPEL electronics celebrates its 35th anniversary. Founded in 1991 as a spin-off of Carl Zeiss Jena Measurement and Testing Technology, the company continuously evolves and is now one of the world’s leading providers of innovative test and inspection systems, with approximately 240 employees as well as locations and partners in more than 25 countries.

GÖPEL electronic was founded as a family business by Holger Göpel, Thomas Wenzel, and Manfred Schneider. To this day, this family-oriented character shapes the corporate culture. With Alice Göpel, Jörg Schneider, and Ricardo Wenzel, the next generation is now also actively involving in management and leadership roles. With annual revenue exceeding 40 million euros, GÖPEL electronic is now one of Thuringia’s leading medium-size technology companies.

A central component of the corporate strategy is consistent investment in research and development. Approximately one-quarter of annual revenue is invested in new technologies, products, and innovations. In doing so, the company lays the foundation for sustainable growth and long-term competitiveness each year. In addition to innovative inspection systems for electronics manufacturing, GÖPEL electronics’s core competencies include electrical test systems based on embedded JTAG and boundary scan, as well as test solutions specifically for the automotive sector.

As early as 2002, the company’s individual test platforms became the de facto standard in the European automotive industry. Worldwide, the AOI systems of the Basic Line, Vario Line, and Multi Line series ensure the highest quality in electronics manufacturing and production lines. In the field of boundary scan, GÖPEL electronic is also internationally known as a leading provider of complex solutions and their seamless integration into existing test environments.

At the same time, GÖPEL electronics is increasingly expanding into new industries. Test solutions for the medical, avionics, security technology, and industrial manufacturing sectors complement the portfolio for the automotive and electronics industries. In the field of inspection systems, the manufacturer is setting new standards this year with its new Multi Line AXI X-ray system, which is based on the new ASPECT technology, and opens up expanded possibilities for the inspection of electronic assemblies. In the Embedded JTAG sector as well, the focus is on innovative software solutions and new models that enable an unprecedented level of test depth in boundary scan. The systems are complemented by modern AI-supported functions that further simplify operation and analysis processes.

“35 years of GÖPEL electronics stand for innovative strength, reliability, and sustainable growth,” explains Alice Göpel, Managing Director of GÖPEL electronics. “We are proud to continue writing the success story of our family business together with our employees, customers, and partners. Many of our current solutions have emerged directly from our customers’ requirements. Together, we develop technologies that solve today’s challenges and help shape the future of electronics manufacturing.”

About GÖPEL electronic

GÖPEL electronic develops and manufactures innovative electrical and optical test, measurement, and inspection equipment for electronic components and printed circuit board assemblies, as well as industrial and automotive electronics systems. GÖPEL electronic has four business units:

•  Automotive Test Solutions
• Embedded JTAG Solutions
• Inspection Solutions AOI-AXI-SPI-IVS
• Industrial Function Test

The company is active worldwide, with its own subsidiaries as well as through distributors, and generated sales of approximately 40 million euros in 2023 with 240 employees. For further information, visit www.goepel.com/en.

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Companies to collaborate on R&D to accelerate the introduction of the latest packaging technologies for next-generation AI chips and systems. Partnership will leverage Applied’s global network of innovation centers, including the new EPIC Center in Silicon Valley.

Applied Materials, Inc., the leader in materials engineering for the semiconductor industry, today announces that Broadcom Inc. will join Applied’s EPIC platform as an innovation partner to accelerate the development of next-gen chip packaging technologies critical to next-generation AI systems.

The explosive growth of AI has driven a surge in demand for high-performance, energy-efficient compute infrastructure. To address this demand, chipmakers and system designers are increasingly adopting the latest packaging techniques and heterogeneous integration of multiple chips, aiming to boost energy-efficient performance across their systems. To unlock AI’s full potential, the industry is developing a new set of packaging building blocks to dramatically increase the interconnect density and bandwidth of tomorrow’s systems.

“The EPIC platform is designed to drive co-innovation across the ecosystem to change the way semiconductor technologies are developed and commercialized,” said Gary Dickerson, President and CEO of Applied Materials. “This new model gives leading system designers like Broadcom early access to foundational innovations in materials and process equipment, providing an opportunity for deep collaboration to accelerate the introduction of new advanced packaging technologies.”

“Close collaboration with partners throughout the supply chain is critical to delivering the next generation of high-performance AI systems,” said Charlie Kawwas, President of the Semiconductor Solutions Group at Broadcom. “By bringing together Applied’s expertise in materials engineering with Broadcom’s leading capabilities in semiconductor and system design, we can accelerate the time to market for innovations in AI.”

Through the EPIC platform partnership, Broadcom will leverage the R&D work taking place across Applied’s global innovation centers – driving progress in advanced packaging capabilities for connecting multiple chips within a computing system.

“Innovation in advanced packaging is essential to enabling sustainable progress in the AI era,” said Dr. Prabu Raja, President of the Semiconductor Products Group at Applied Materials. “We look forward to working side-by-side with Broadcom engineers to explore new technologies for boosting performance-per-watt through advanced chip packaging. With our global innovation platform and the new EPIC Center in Silicon Valley, Applied is uniquely positioned to help chipmakers and system designers accelerate the journey from concept to commercialization.”

“Cross-ecosystem collaboration has never been more important to address the rising complexity of chips for AI systems,” said Dilip Vijay, Vice President and Head of Global Operations for Silicon Products at Broadcom. “System designers must navigate a complex array of solution paths and packaging architectures, while simultaneously driving a faster cadence of product introductions. Collaborating with Applied will provide earlier access to the foundational technologies needed to accelerate progress in advanced packaging.”

Applied’s new EPIC (Equipment and Process Innovation and Commercialization) Center in Silicon Valley is the cornerstone of the company’s global EPIC platform. Representing the largest-ever U.S. investment in semiconductor equipment R&D, the center is designed from the ground up to dramatically reduce the time it takes to commercialize breakthrough technologies from early-stage research to full-scale manufacturing. The facility is on track to become operational in 2026.

Forward-Looking Statements

This press release contains forward-looking statements, including those regarding Applied’s investment and growth strategies, the development of new materials and technologies, industry outlook and technology requirements, the plans and expectations for the EPIC platform and Center, and other statements that are not historical facts. These statements and their underlying assumptions are subject to risks and uncertainties and are not guarantees of future performance. Factors that could cause actual results to differ materially from those shown by such statements include, without limitation: the demand for semiconductors and customers’ technology requirements; the ability to develop new and innovative technologies; the ability to obtain and protect intellectual property rights in key technologies; the ability to achieve the objectives of the EPIC platform and Center; and other risks and uncertainties described in Applied’s filings with the Securities and Exchange Commission, including Applied’s most recent Forms 10-K, 10-Q and 8-K. All forward-looking statements are based on management’s current estimates, projections, and assumptions, and Applied assumes no obligation to update them.

About Applied Materials

Applied Materials, Inc. is the leader in materials engineering solutions that are at the foundation of virtually every new semiconductor and advanced display in the world. The technology we create is essential to advancing AI and accelerating the commercialization of next-generation chips. At Applied, we push the boundaries of science and engineering to deliver material innovation that changes the world. Learn more at www.appliedmaterials.com.

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$2.59 Trillion in AI Spending Excels by Vendors and Hyperscalers, with Enterprises Yet to Flex Spending Potential.

Worldwide spending on AI is forecast to total $2.59 trillion in 2026, a 47% increase year-over-year, according to Gartner, Inc., a business and technology insights company.

“Through the next several years, the need for capacity will make AI infrastructure, including AI-optimized IaaS, AI-optimized servers, AI network fabric, AI processing semiconductors and devices, the largest segment of the market, accounting for over 45% of spending, which will be driven by vendors,” said John-David Lovelock, Distinguished VP Analyst at Gartner. “Within this segment, spending on AI-optimized servers will triple over the next five years to become the largest subsegment, as cloud services providers expand capacity in anticipation of the workloads created by GenAI models and agentic workflows.”

Enterprises are expanding their use of both GenAI models with built-in existing software applications and the latest AI agents within multiple workflows. Model consumption increases through multistep processes and integration into broad suites of tools as enterprises recognize the potential value of agentic automation. This dynamic means that the short-term outlook for AI models would increase to 110% growth in 2026, adding $6 billion in spending this year.

Worldwide AI Spending by Market, 2025-2027 (Millions of U.S. Dollars)

Market	2025	2026	2027
AI Services	436,351	585,527	759,418
AI Cybersecurity	25,920	51,347	85,997
AI Software	282,897	453,209	638,431
AI Models	15,494	32,604	59,161
AI Platforms for Data Science and Machine Learning	21,292	29,928	42,639
AI Application Development Platforms	6,587	8,416	10,922
AI Data	826	3,126	6,480
AI Infrastructure	975,581	1,431,509	1,890,310
Total AI Spending	1,764,947	2,595,667	3,493,358

Source: Gartner (May 2026)

“Up to this point, AI spending has primarily been driven by technology companies and hyperscalers,” said Lovelock. Enterprises have yet to really flex their spending potential. That is coming, and 2026 will be the inflection year. Currently, organizations show limited appetite for using AI to drive disruptive enterprise change. Instead, they favor tactical AI initiatives with incremental improvements in efficiency and productivity.

“For this reason, CIOs face challenges in proving the value from AI investments and demonstrate tangible business outcomes,” said Lovelock. “Aligning AI initiatives with strategic business objectives is the essential step for success. This incremental approach persists despite AI hype and valuations that reflect aspirations to transform the broader economy.”

Gartner is the World Authority on AI

Gartner is the indispensable partner to C-Level executives and technology providers as they implement AI strategies to achieve their critical priorities. The independence and objectivity of Gartner insights provide clients with the confidence to make smart decisions and unlock the full potential of AI. Clients across the C-Level are using Gartner’s proprietary AskGartner AI tool to determine how to leverage AI in the business. With more than 2,500 business and technology experts, 6,000 written insights, and more than 4,000 AI use cases and case studies, Gartner is the world’s authority on AI. More information can be found here.

Gartner IT Symposium/Xpo

The outlook on AIs during Gartner IT Symposium/Xpo is the world’s most important conference for CIOs and other IT executives. Gartner analysts and attendees explore how to become agents of change in their organizations and harness AI for successful digital transformation. Follow news and updates from the conferences on X and LinkedIn using #GartnerSYM, and on the Gartner Newsroom.

Upcoming dates and locations for Gartner IT Symposium/Xpo include:
September 14-16, 2026 | Gold Coast, Australia
October 19-22, 2026 | Orlando, FL
November 4-6, 2026 | Yokohama, Japan
November 9-12, 2026 | Barcelona, Spain
November 16-18, 2026 | Kochi, India

About Gartner for High Tech Leaders and Providers

Gartner for High Tech Leaders and Providers equips tech leaders and their teams with role-based best practices, industry insights, and strategic views into emerging trends and market changes to achieve their mission-critical priorities and build the successful organizations of tomorrow. Additional information is available at www.gartner.com/en/industries/high-tech.

 

 

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Науковці НН ІМЗ ім. Є.О. Патона конструюють новітні матеріали на атомному рівні Інформація КП пт, 05/29/2026 - 12:00

Artificial intelligence (AI) silicon is increasingly defined not only by compute capability, but by how data moves through the system. Modern AI SoCs, edge AI processors, automotive compute platforms, and AI accelerators depend on large volumes of data moving among compute engines, memory systems, sensor interfaces, accelerators, chiplet interfaces, firmware controllers, and I/O.

This is why network-on-chip (NoC) architectures have become essential. An NoC provides the internal communication fabric that helps organize routing, arbitration, bandwidth allocation, quality of service, congestion management, and latency behavior inside complex AI silicon.

But it’s important to make a clear distinction.

An NoC is part of the chip execution architecture. It’s not the same as the external signaling interfaces that bring data into or out of the chip.

External signals may arrive through MIPI, SerDes, PCIe, CXL, UCIe, LPDDR, HBM, Ethernet, CAN, or other physical and protocol interfaces. Those interfaces use PHYs, controllers, and protocol layers to move signals into a form the SoC can process internally. Once inside the chip, the NoC routes transactions among internal blocks such as CPUs, NPUs, GPUs, DSPs, memory controllers, sensor-processing blocks, safety islands, and I/O controllers.

In other words, external interfaces move signals into and out of the silicon. The NoC organizes internal data movement inside the silicon. This distinction matters because data movement is not the same as evidence governance.

NoC is not the governance layer

An NoC can move data efficiently, but it does not determine whether a later system symptom was caused by NoC behavior, timing weakness, placement and routing (P&R), power delivery, package behavior, firmware scheduling, workload bursts, or thermal conditions.

For example, a system may observe:

• Accelerator stalls
• Latency spikes
• Traffic congestion
• Power bursts
• Voltage droop
• Timing-margin loss
• Thermal hotspots
• Memory-access delays
• Chiplet-interface errors
• Workload-dependent failures

These symptoms may involve NoC activity, but NoC activity alone does not prove NoC causality.

A thermal hotspot may correlate with NoC traffic, but the root cause could also be local transistor density, P&R, clocking behavior, package thermal resistance, power-delivery weakness, firmware scheduling, workload concentration, sensor placement, board conditions, or cooling limitations.

A latency spike may appear in an NoC counter, but the underlying contributor could be memory-controller contention, cache behavior, firmware policy, workload burstiness, arbitration settings, clock-domain crossing, timing margin, or external I/O behavior.

This is the central point: NoC may be one possible contributor to observed AI silicon behavior, but it should not be assumed to be the source of the problem without admissible evidence.

Where SEGA-AI fits

SEGA-AI does not replace NoC architecture, RTL design, physical implementation, timing closure, P&R, verification, or post-silicon debug. Its role is different.

SEGA-AI defines how NoC-related observability, telemetry, counters, workload traces, firmware logs, power data, thermal data, package evidence, and system behavior are qualified before any root-cause conclusion or lifecycle-governance decision is made.

The contribution is not SEGA-AI sees a problem and knows the cause. The contribution is SEGA-AI governs the evidence path required before the system is allowed to assign cause, trigger corrective action, refine assumptions, or update lifecycle policy.

This distinction is essential for complex AI silicon because many physical, architectural, and operational mechanisms can produce similar symptoms.

• A detected hotspot is a symptom
• A detected latency spike is a symptom
• A voltage droop event is a symptom
• An accelerator stall is a symptom

SEGA-AI asks whether the evidence behind that symptom is mature enough, synchronized enough, causally valid enough, and admissible enough to support a decision.

From symptom to evidence through CEMH

Consider a realized AI SoC where telemetry reports a localized hotspot during a high-throughput workload. At level 1, with raw data, the system has only a thermal sensor observation: a localized temperature rise was detected. This observation is useful, but it’s not yet decision-ready evidence.

At level 2, with interoperable data, the temperature reading can move into a diagnostic environment, firmware log, validation database, or fleet-monitoring system. But movement does not create authority. The hotspot may be visible and accessible, but its cause is still unknown.

At level 3, with normalized evidence, the observation is linked to the context required for interpretation:

• Workload type
• Timestamp and runtime epoch
• Firmware policy state
• NoC traffic counters
• Accelerator utilization
• Memory-controller activity
• Voltage droop measurements
• Clock and power state
• Floorplan region
• Thermal sensor location
• Package thermal path
• Board and cooling condition
• Package lot and assembly history
• Validation correlation status

Only at this stage can the event begin to be compared across domains.

At level 4, with admissible evidence, the evidence must pass the Trusted Convergence Governance (TCG) gate. The system must confirm provenance, synchronization, realization-state validity, causal relevance, measurement confidence, and chain-of-custody integrity before the hotspot data can influence a convergence decision.

At level 5, with convergence-authoritative evidence, the system has enough qualified evidence to support bounded action or lifecycle refinement. That action may be a firmware policy adjustment, workload throttling, degraded mode, validation update, package constraint refinement, or future design-rule feedback.

• The hotspot may be related to NoC congestion.
• It may be related to accelerator placement.
• It may be related to P&R density.
• It may be related to package thermal resistance.
• It may be related to voltage droop and increased local switching.
• It may be related to firmware scheduling or workload concentration.
• The purpose of SEGA-AI is to prevent premature conclusions.
• A thermal sensor does not prove NoC causality.
• An NoC counter does not prove package causality.
• A voltage droop event does not prove timing causality.

SEGA-AI requires that the evidence mature through Convergence Evidence Maturity Hierarchy (CEMH) and pass TCG admissibility before any root-cause conclusion or lifecycle-governance action receives authority.

The role of CEMH, TCG, and GFL

Within the SEGA-AI framework, three layers are especially relevant.

Convergence Evidence Maturity Hierarchy (CEMH) defines how information matures from raw observation into convergence-authoritative evidence. A thermal sensor value, NoC counter, voltage monitor, or firmware trace begin as raw or interoperable data. It does not become decision-ready evidence until it has been contextualized, synchronized, qualified, and connected to the correct realization state.

Trusted Convergence Governance (TCG) acts as the trust gate. It asks whether evidence preserves provenance, synchronization validity, realization-state consistency, causal relevance, and bounded authority before it influences a decision.

Governance for Lifecycle (GFL) asks whether the realized system can remain converged throughout operational life. It’s concerned not only with whether the chip worked at initial signoff, but whether chip, package, board, firmware, workload, and field behavior remain aligned over time.

Together, these layers prevent a common failure mode: mistaking observable behavior for proven causality.

Diagnostic evidence plan

This also changes how AI silicon should be planned before implementation. Here, SEGA-AI can contribute by helping define the diagnostic evidence plan.

• Which NoC counters are needed?
• Which congestion metrics should be exposed?
• Which workload tags must be preserved?
• Which timestamps and synchronization epochs are required?
• Which voltage, thermal, clock, and power monitors are needed?
• Which firmware traces must be connected to physical state?
• Which package and board conditions must be tracked?
• Which evidence fields are required to distinguish NoC behavior from timing, P&R, PDN, thermal, firmware, or package causes?

This does not mean SEGA-AI designs the NoC. It means SEGA-AI asks what evidence must exist later so that realized-system behavior can be interpreted correctly. That is the bridge between design intent and lifecycle governance.

Why data movement alone isn’t enough

NoC architectures are essential because AI silicon needs scalable internal communication. But moving data correctly inside the chip does not automatically explain system behavior after realization. An NoC may deliver a packet correctly while the system still experiences thermal drift. Likewise, a controller may report a valid transaction while the package creates a local thermal bottleneck.

Next, a firmware trace may show a workload transition while the underlying voltage margin is collapsing. Or a sensor may report a hotspot while the causal chain remains ambiguous. This is why observability must become governed evidence before it can support lifecycle decisions.

The key question is not only: Did the data move? The real question is: Is the observed behavior mature enough as evidence to support diagnosis, intervention, or lifecycle refinement? This distinction becomes especially important in edge AI and ADAS systems.

In an ADAS platform, camera, radar, lidar, IMU, wheel-speed, steering, and vehicle-state data enter through physical interfaces and controllers. Inside the AI SoC, the NoC routes internal traffic among image processors, AI accelerators, CPUs, memory controllers, safety islands, and I/O blocks.

The AI accelerator may detect pedestrians, lanes, vehicles, or collision risk. But if a late response, thermal event, inference delay, or braking-decision uncertainty is observed, the system should not automatically blame the NoC, the AI model, the memory controller, or the package. It must first build an admissible evidence chain.

This matters because ADAS is not only a performance application; it’s a safety-critical realization environment.

A latency spike or inference delay may affect warning time, braking distance, steering support, or driver handoff. In that context, clean data movement is not enough. The system must know whether the evidence supporting the decision is synchronized, causally valid, realization-consistent, and authoritative enough for action.

For low-risk edge AI applications, a wrong output may create inconvenience or cost. For ADAS, a wrong output may affect human safety. That changes the required evidence maturity.

A safety-critical output should not receive full action authority simply because data moved correctly through the chip. It should be supported by level 5 convergence-authoritative evidence or by a pre-qualified safety envelope that has already been validated through admissible evidence.

In SEGA-AI terms, the chain is:

Input evidence → local inference → confidence and uncertainty → synchronization check → causality check → TCG admissibility gate → bounded output authority

This is why edge AI and ADAS show the difference between data movement and evidence governance. The NoC may help move sensor data, model data, and inference results; but SEGA-AI governs whether the observed behavior is trustworthy enough to support diagnosis, intervention, degraded mode, fleet learning, or safety-critical action.

From execution fabric to governance framework

The NoC is an execution fabric; SEGA-AI is a governance framework. The NoC helps the chip move data; SEGA-AI helps the system determine whether observed behavior can be trusted as evidence. And these are complementary roles.

As AI silicon becomes more complex, the industry will need both: data-movement architecture to move information efficiently inside the chip, and evidence-governance architecture to determine whether observed behavior can support root-cause analysis, corrective action, lifecycle refinement, or fleet learning.

This becomes increasingly important as systems move from design into package, board, validation, deployment, runtime adaptation, and field operation. And this discussion is not only theoretical. If realized AI systems require governed evidence, then implementation must account for evidence maturity from the beginning.

That means the design and validation plan must define not only what data moves, but what data must later be observable, timestamped, correlated, and qualified. For example, if post-silicon validation or field operation needs to distinguish NoC congestion from P&R density, package thermal resistance, memory-controller contention, or firmware scheduling, then the required evidence must be designed into the system earlier.

This includes counters, monitors, timestamping, workload tags, synchronization epochs, sensor placement, firmware traceability, package-state linkage, and validation correlation methods. In SEGA-AI terms, the theoretical model becomes practical only when it’s translated into implementation artifacts: evidence fields, admissibility checks, traceability rules, synchronization requirements, gate criteria, diagnostic workflows, and lifecycle feedback paths.

This is why the next step after governance theory is implementation specification. A system cannot govern evidence it never planned to observe.

Silicon governance complementing NoC

AI silicon performance depends heavily on data movement. NoC architectures are essential because they organize internal communication among compute, memory, accelerators, controllers, chiplet interfaces, and I/O. But NoC observability is not the same as causality.

A latency spike, hotspot, voltage droop, or accelerator stall may involve NoC behavior, but it may also be driven by timing, P&R, power delivery, package thermal paths, firmware policy, workload behavior, or system-level conditions.

However, the role of SEGA-AI is not to replace NoC design. The role of SEGA-AI is to govern the evidence required before symptoms become conclusions and before conclusions become decisions.

For AI silicon, the next challenge is therefore not only moving data efficiently. It’s qualifying observed behavior into admissible, causally grounded, convergence-authoritative evidence. In short, interoperability moves data; admissibility qualifies evidence; and governed convergence closes decisions.

Dr. Moh Kolbehdari is senior director of IC/packaging at Socionext US.

Related Content

• Speeding AI SoC development with NoC-enabled tiling
• How data movement defines performance for AI silicon
• Why verification matters in network-on-chip (NoC) design
• Taming the beast: Memory efficiency in an AI/crypto world
• Automotive silicon in the era of AI, functional safety, and cybersecurity

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На війні загинув випускник нашого університету — Реваз Гегечкорі kpi чт, 05/28/2026 - 22:48

Purdue University has formed a strategic partnership with Taiwan-based GeChi Compound Semiconductor Co (GCCS) to accelerate the commercialization of silicon carbide (SiC). The collaboration targets the critical thermal, power and 6G bottlenecks currently constraining the next generation of high-compute infrastructure...

A fundamentally new approach is required to fuse AI-driven automation and multiphysics intelligence across the entire design and manufacturing flow. That was the crux of the keynote by Synopsys president and CEO Sassine Ghazi at the SAFE Forum 2026, held by Samsung Foundry in San Jose, California.

Ghazi especially mentioned design and technology co-optimization (DTCO) initiatives for synthesis and layout, as well as sign-off, delivering meaningful power, performance, and area (PPA) enhancements. He also talked about the design partnership between Samsung Foundry and Synopsys, which encompasses production-ready, AI-powered EDA tools, certified interface IP, and silicon-based test capabilities.

Hyung-Ock Kim, VP and head of the Foundry Design Technology Team at Samsung Electronics, echoed similar views, stressing the need for close alignment across design, test, and manufacturing to ensure the success of AI and multi-die designs on advanced nodes.

He also presented an update on Samsung Foundry’s collaboration with Samsung for production-ready, AI-powered digital and analog flows. “Our continued close collaboration with Synopsys delivers silicon-based, customer-validated solutions that help our customers reduce design integration risk, improve silicon predictability, and move confidently from design to production for their most innovative solutions,” Kim said.

Ravi Subramanian, chief product management officer at Synopsys, briefed on AI-powered digital and analog flows for Samsung’s second- and third-generation 2-nm processes. “As designs become more heterogeneous, customers need production-ready, silicon-proven solutions that address complexity and minimize risk from silicon to systems,” he said. “Our work with Samsung Foundry translates years of DTCO and silicon learning into enablement that helps our customers get their advanced designs to market quickly and with confidence.”

The partnership encompasses AI-powered EDA flows, multiphysics sign-off, interface IPs, and silicon-based test patters. Source: Synopsys

Below are the five key tenets of this design partnership between Samsung Foundry and Synopsys.

1. Production-ready digital and analog flows for 2-nm process

As part of DTCO initiatives, Synopsys Fusion Compiler delivers measurable power and performance improvements in the third-generation 2-nm class process compared to the second-generation 2-nm class process.

2. Sign-off with certified multiphysics capabilities

Synopsys PrimeShield process sensitivity analysis and PVT Explorer support design-specific optimization and engineering change order (ECO) decisions during sign-off. That leads to frequency improvement of up to 2.7% within 5% leakage current degradation. Moreover, Synopsys Totem-SC, a newly certified electromigration (EM) and IR drop analysis solution, improves silicon design power integrity and reliability in second-generation 2-nm and 4-nm class processes.

3. 3DIC with hybrid copper bonding

Samsung Foundry and Synopsys have joined hands to enable scalable 3D multi-die designs through certified multiphysics signoff solutions delivered within Synopsys 3DIC Compiler, a unified exploration-to-signoff platform being validated on a hybrid copper bonding (HCB) 3D test chip.

This platform brings together planning, implementation, and multiphysics analysis to enable co-optimization across integrated compute, memory, and advanced packaging systems for Samsung’s 3DIC solutions with HCB technology. And it replaces manual, margin-based approaches with automated, AI-driven system optimization to accelerate productivity and enhance the quality of results (QoR).

4. Interface and foundation IP portfolio

Synopsys offers a broad portfolio of IPs across Samsung Foundry’s advanced processes, ranging from 14-nm, 8-nm, and 5-nm processes to the latest 4-nm and second-generation 2-nm nodes. The interface IP offerings cover UCIe, PCIe 7.0, 112G/224G, MIPI, LPDDR6, DDR5 MRDIMM Gen2, and USB4. Likewise, its foundation IPs include embedded memories, logic libraries, GPIOs, security IP, and Silicon Lifecycle Management (SLM).

5. AI-powered tests

Samsung Foundry and Synopsys are also applying silicon-proven methodologies to design-for-test (DFT) and manufacturing test capabilities to reduce test cost and improve test quality for designs on advanced process nodes. Furthermore, physically aware tests and failure diagnosis at the die and multi-die level improve test quality and failure analysis turnaround time with results validated on silicon at Samsung Foundry.

For instance, Samsung Foundry teams employed Synopsys TestMAX along with AI-assisted automatic test pattern generation (ATPG) technologies to reduce test patterns and test cycles by up to 20%. Samsung Foundry customers leveraging these AI-powered, silicon-based design and manufacturing test capabilities acknowledge test efficiency improvements of up to 20%.

Related Content

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• How generative AI puts the magic back in hardware design
• 4 basic steps in implementing an AI-driven design workflow

The post 5 takeaways from Samsung Foundry’s design tie-up with Synopsys appeared first on EDN.

RF, microwave and power component distributor RFMW of San Jose, CA, USA (a Division of Exponential Technology Group Inc) has announced a global distribution agreement with South Korea-based RFHIC Corp...

A welcome career transition (and employer-responsibility expansion) begs for a hardware-plus-software evolution. Hold his beer; this engineer’s got this.

As some of you may have already noticed (assuming you even care about such things), my relationship with EDN recently (and happily) re-deepened. After being a full-time as a (senior, eventually) technical editor from 1997 to 2011, I returned beginning a year later, this time as a content contributor. And now I’ve added associate editor to my EDN repertoire.

“Wait,” you might be asking, “isn’t Aalyia Shaukat the associate editor at EDN?” You’re part-right; for nearly four years, she was. And for a couple of recent months, she (somehow) worked a double shift of jobs. But she’s now the full-time editor-in-chief at Power Electronics News, where she’s already rockin’ the house with her talent abundance. And I’m grateful to follow in her EDN associate editor footsteps, along with continuing my own frequent content-contribution cadence.

What’s this all got to do with “de-commingling (or if you prefer simpler vocabulary, “separating”) LAN equipment”? An excellent question. Now that I’m more intimately interacting with the EDN website and other publication (and publisher, and corporate owner) resources and services, I needed to set up a standalone computer so that nothing attacking my home office LAN could make its way to the corporate network and other facilities, too. That said, I remained heavily broadband-reliant. And I wasn’t up for setting up a completely separate Comcast service connection just for a single (albeit also a singularly important) computer. What to do?

Just call me “guest”

That last part was actually the easiest part to solve, it turns out. My home LAN, as mentioned before, is based on a multi-node mesh implemented using multiple Google Nest Wifi routers, with the primary one connected to the cable modem in the furnace room.

One nifty nuance of the Google Nest Wifi system (shared by not only other Google LAN equipment generations and gear from other suppliers, mind you) is that you can set up a distinct “guest” network that by default (which I’ve left unchanged in my case) is packet-isolated from the main LAN beyond their shared WAN connection.

The computer I’m dedicating to my EDN associate editor work is one you’ve seen before; a Microsoft Surface Pro 7+ (SP7+):

along with my longstanding tech-gear companion, a Kensington Dock:

mated as so:

LAN-migrating the SP7+ was easy-peasy. I disconnected the wired Ethernet cable from the back of the Kensington Dock, switched the computer from my main “RockyMountainBri” wireless network to “RockyMountainBri-guest”, and…that was it. And since my Brother multifunction laser printer was right next to the computer, I didn’t even need to bother migrating the wireless network that the MFC was connected to, foregoing printing support for the rest of my LAN in the process. I just ran a USB cable from the Kensington Dock to it, and…I was done. Perhaps obviously, by the way, any real guests are no longer able to use my “guest” wireless network.

Split personality

How do I handle the fact that, still acting as a contributing editor along with my other contributor colleagues, I’m now in effect submitting content to myself for subsequent publication, now wearing my associate editor hat? My contributing editor workflow is unchanged, actually. The only thing that’s different is the email address I now send my stuff to.

It used to be that I’d submit content from my personal email account to Aalyia’s corporate email address. Now, instead, it’s my corporate email address that the goods go to. I’m still using one of my other systems for initial writing—typically but not always a Mac. But, to maintain “firewall” purity between my newly transformed associate editor work system and the rest, I exclusively receive corporate email (and don’t send or receive personal email) on the SP7+.

Going loc(al, not o)

And what about backing up and archiving all this content I’m now receiving? Regular readers may remember that I’ve long been a fan, along with a frequent implementer and upgrader, of network-attached storage (NAS) for such (and other) purposes. That said, unless I wanted to dedicate a NAS solely to my “guest” network and connect it exclusively over slow Wi-Fi, I was going to need to transition to some other solution.

Therein lies the admittedly and intentionally somewhat obscure title of this piece. Instead of network-attached storage, I wanted something locally tethered. It had to be at least dual drive configuration, with RAID 1 support so I didn’t lose everything if a hard drive died. And ideally it’d run hardware RAID to avoid bogging down the computer. Yes, I know, if the RAID controller fails, you’re dead in the water, too, which is why I also wanted something that was reasonably popular. That way, I could, if necessary, find a replacement to slot the HDDs into without too much trouble.

I figured I’d start my search using the term “DAS”, for direct-attached storage. Interface technologies I’d used in the past—Firewire, Thunderbolt, and eSATA among them—weren’t relevant to this particular hardware configuration, so I settled on USB 3.x, as fast a flavor as possible, over USB-C. My (perhaps imperfect) search yielded exactly one result, QNAP’s TR-002, which ironically is primarily intended to capacity-expand the company’s NASs but can also find use as a standalone storage peripheral.

Tomato, tomahto

At this point, I reset my lingo-options list, expanding beyond “DAS” to also include “enclosure”. That change helped a lot from a results-options list length standpoint. What I’ve ended up with is the Mercury Elite Pro Dual from a company I’ve mentioned multiple times before, Other World Computing (aka, OWC) and bought open-box (with 1-year warranty) for $167.50.

It’s hardware RAID-based, supporting four different operating modes (albeit only one at a time):

• RAID 0 “Drive Striping”
• RAID 1 “Drive Mirroring” (the mode I’m using)
• Span, and
• Independent Drives

Its interface to the computer is 10 GBps USB 3.2; perhaps obviously, I’m direct-connecting it to the SP7+ versus going through the Kensington Dock intermediary. It also embeds a three-port hub, a particularly attractive proposition given the SP7+’s dearth of integrated connections. And here’s a rarity (as I’ve written about before); the hub’s USB-C and dual USB-A ports are all 10 Gbps peak bandwidth-capable, too.

Why, you might be asking, did I go with HDDs instead of SSDs? I’ll turn around and ask you a question in response to yours: have you priced SSDs lately? That said, HDD price tags are also skyrocketing lately, although they still hold a tangible edge over solid-state alternatives especially at higher capacities. And in my case, I thankfully was able to repurpose a couple of spare 3TB HDDs I’d already bought in the “before times” and still had sitting around unused (I’ll have more to say here in an already-planned upcoming follow-up post).

Software completes the magic trick

The last, but not the least, question: how to integrate it with my computer for mirroring and broader backup purposes? I planned on consistently using the SP7+’s upgraded-by-me 1 TByte SSD as primary storage of in-process and completed associated editor work, so one-way mirroring (versus two-way syncing) that portion of the SSD to external storage would be fine.

But I wanted that mirroring to be file-by-file, not lumped together into some unified-file or otherwise nonstandard format (Apple’s Time Machine, for example) that would make it difficult to resurrect the contents if primary storage in the computer failed, say, or if I needed to physically pass the external storage device to someone else. And, of course, I’m also looking for cheaper solutions, so open source or another free source would be best.

I found my solution in a two-part open-source program suite, developed and maintained by the FreeFileSync project and supporting Linux, MacOS and Windows platforms. FreeFileSync itself does the sync-and-mirror heavy lifting for both files and the folders containing them. And the closely related RealTimeSync monitors directories for content changes, which then kick off FreeFileSync (or any other operation more broadly).

This discussion thread was very helpful when I was setting up RealTimeSync and FreeFileSync on my system. And ever since then, it’s run like a charm; the only time it pauses is when it detects an abnormally large number of changes (multiple directories-and-files moved at once) and wants my OK before it proceeds.

Oh, and by the way…since I’ve got plenty of empty capacity available, at least at this early stage in my associate editor career, I’m also using the OWC Mercury Elite Pro Dual more broadly as a successor to the NAS for my ongoing computer-wide backup purposes using Windows’ built-in File History and (deprecated but still functional) Backup and Restore facilities that I’ve mentioned before. With that, I’ll wrap up for today. I hope what I’ve shared will be of help to at least some of you in similar configuration situations either now or in the future. As always, please share your thoughts on what’s worked (or not) for you in the comments!

—Brian Dipert is the associate editor, as well as a contributing editor, at EDN.

Related Content

• The whole-house LAN: Achilles-heel alternatives, tradeoffs, and plans
• The Microsoft Surface Pro 5 succession: Selections, motivations, and initial impressions
• Beefing up backup
• USB 3: How did it end up being so messy?

The post De-commingling (?) LAN equipment: It’s all in what you call it appeared first on EDN.

Epiwafer and substrate maker IQE plc of Cardiff, Wales, UK has completed its fundraising, yielding total subscription proceeds of £81m...

Infineon Technologies AG expands its CoolGaN BDS 40 V G3 bidirectional switch (BDS) family with two new devices, the IGK048B041S and IGK120B041S. The new additions reduce PCB footprint by 82 percent and cut component count in half. For engineers designing within the strict spatial constraints of modern smartphones, notebooks, and wearables, this is a significant and quantifiable step forward. Targeting compact consumer devices, the new devices give power system designers greater flexibility to optimize efficiency and streamline designs without sacrificing performance.

“As consumer devices continue to shrink while power demands grow, engineers face increasing pressure to deliver more from less. The new CoolGaN BDS devices directly address this challenge,” said Johannes Schoiswohl, GaN Business Line Head at Infineon. “Each device integrates the function of two back-to-back silicon MOSFETs into a single component, reducing component count by half and simplifying PCB layouts. Design teams can leverage existing driver layout, avoiding costly redesigns and accelerating time to market. The result is a leaner and more cost-effective power path.”

The BDS, like other GaN devices, is compatible with 5 V gate drive. Offered in WLCSP chip-scale packages measuring 2.1 x 2.1 mm² and 1.7 x 1.2 mm², the IGK048B041S and IGK120B041S are engineered for the tight spatial constraints of smartphones, notebooks, and wearables. The larger GaN device achieves 4.2 mΩ RDD(on) while the smaller device delivers 9 mΩ RDD(on). The CoolGaN BDS devices further distinguish themselves through superior switching and leakage performance. Gate charge is up to approximately 40 percent lower than that of comparable competing devices. Lower gate charge translates directly to faster switching transitions, reduced switching losses, and better system efficiency in fast-charging applications. Additionally, Drain-Drain Leakage current is more than 85 percent lower than competing solutions, underscoring the inherent leakage advantages of GaN technology. Together, these characteristics reduce thermal rise, supporting long-term reliability and helping manufacturers meet increasingly stringent safety requirements.

Unlike silicon MOSFETs, which rely on a body diode that can allow unintended current flow, the CoolGaN BDS devices allow bidirectional voltage and current blocking. This true bidirectional blocking capability is essential for applications such as USB overvoltage protection in smartphones and portable devices, where preventing unwanted reverse current is critical to protecting sensitive downstream components. The devices are equally well-suited to load switching and power multiplexing functions in multi-rail power architectures, where precise control of current direction across multiple supply rails is required.

With the addition of these two devices, the Infineon CoolGaN BDS 40 V G3 family now comprises three devices: the IGK048B041S, IGK120B041S, and the IGK080B041S, addressing the full spectrum of mobile power switching requirements from compact wearables to high-performance notebooks.

Infineon has a strong portfolio with more than 40 new GaN product announcements in the last year and is a preferred partner for customers seeking high-quality GaN solutions. The company is on track with its implementation of scalable GaN manufacturing on 300-millimeter wafers, with first samples already being shipped to customers. 300 mm GaN enables higher production capacity and faster delivery of high-quality GaN products, which further strengthens Infineon’s position in the GaN market.

The post Infineon CoolGaN BDS Chips Splash Portable Power Footprint by 82% appeared first on ELE Times.

MathWorks, the leading developer of mathematical computing software, today announces new Hardware Support Packages that directly connect Model-Based Design and simulation to execution on Renesas‘ RH850/U2A microcontroller for automotive applications and the RA6T2 microcontroller for industrial controls. The new MATLAB and Simulink integrations enable engineering teams to move from simulation to running code on hardware with automatic build, flashing, and on-target execution while also accelerating development cycles, eliminating many manual integration steps.

“Our customers expect a straightforward path from simulation model to microcontroller, and the new integration with MATLAB and Simulink delivers exactly that,” said Brad Rex, Senior Director of System Solution Team, UX (User Experience) Group at Renesas. “By working with MathWorks, we’ve removed the need to assemble toolchains and device drivers by hand so teams can simulate and validate designs earlier, iterate faster, and reduce integration effort across ECU and industrial-control projects.“

The new support packages provide engineering teams with a consistent Model-Based Design workflow across both automotive and industrial programs, reducing integration effort and accelerating deployment. Renesas’ RA microcontroller platform focuses on industrial and robotics applications that require flexible connectivity, real-time responsiveness, and scalable embedded control. The integration with the RA family enables rapid prototyping of servo and variable-speed drive applications, with one-click deployment that streamlines hardware bring-up and on-bench validation for motion profiles and closed-loop tuning.

The automotive electronic control units widely uses he Renesas RH850/U2A microcontroller, which provides the deterministic performance and safety-critical features for EV motor control, latest driver-assistance systems (ADAS), and body electronics. Automotive engineers developing traction motor control for electric vehicles can deploy field-oriented control and regenerative braking algorithms directly from Simulink to RH850/U2A-based ECUs. This shortens the time from concept to vehicle-level testing, supports smoother torque delivery during rapid transients, and speeds calibration across drive cycles—without writing initialization code or custom build scripts.

“Our collaboration with Renesas strengthens the level of interoperability that engineers expect when using MATLAB and Simulink,” said Anuja Apte, India Product Marketing Manager, MathWorks. “By providing a direct path from Simulink models to optimized microcontroller deployment, we help engineering teams move from design to hardware more efficiently while staying integrated with the broader toolchains they rely on. This approach reflects the MathWorks Connections program, which brings partners and customers together to accelerate innovation and reduce time to market within a widely adopted engineering and scientific platform.”

For more information on the new hardware support packages in MATLAB and Simulink, visit the Renesas RH850 hardware support page and the Renesas RA hardware support page on the MathWorks website.

The post MathWorks Launches New Renesas Hardware Support Packages to Enable Rapid Prototyping for Automotive and Industrial Engineers appeared first on ELE Times.

Ювілейна  олімпіада з енергетичного менеджменту Інформація КП чт, 05/28/2026 - 11:53

The planet is facing a crisis in energy demand versus supply, and data centers are at the center of this dilemma due to the increasing demand from new data-intensive applications. This article will explore the causes of data center inefficiency and speculate on methods to improve efficiency. It will also acknowledge the U.S. Department of Energy’s analysis on energy efficiency, which provides a basis for this work.

Energy demand and where it’s being used

The announcement that Three Mile Island nuclear reactor was being recommissioned to power an AI data center might have been shocking news to some, but it’s no secret in the industry that the exploding demand for energy is outpacing our ability to deliver power to data centers. For the first time, power efficiency is now a higher priority to data center architects than performance of the individual components.

Semiconductor Research Corp. modeled this increase in energy demand in the context of the planet’s projected energy generation capacity, which includes the assumption that more nuclear power plants will be deployed. Figure 1 shows a daunting projection, and the potential for the lines of supply and demand to intersect around the year 2055 has the electronics industry rethinking its choices in how data centers can be designed.

Figure 1 The worldwide energy consumption trends show that we will eventually consume more energy than we produce. Source: Stanford University

Sadasivan Shankar at Stanford University broke down the places where we are spending that energy. In addition to AI, another culprit in energy demand is cryptocurrency. When combined, AI and crypto are consuming over 1.5% of the planet’s energy already. Some projections estimate that their data consumption will increase to 3% by 2030 and 4.4% by 2035 (see Figure 2). Note the scaling for the Y-axis in Figure 2: Applications such as cryptocoin mining require 18 orders of magnitude more energy than the base instructions on which the computers operate.

Figure 2 The energy demands for AI and cryptocurrency are a magnitude greater than that of other operations. Source: The U.S. Department of Energy

With this in mind, it makes sense to determine the efficiency of a data center by measuring the work accomplished for each watt that is spent. Figure 3 breaks down the power consumption per operation. It’s critical to note that almost every operation in the top two-thirds of the table refers to moving data around, while the bottom third of the table represents data processing.

Figure 3 Data centers consume different amounts of power for different functions. Source: Wolley Inc.

The memory, storage, and communications hierarchy is commonly shown as a pyramid, with processor registers at the top, various levels of cache followed by DRAM, then storage and communications at the bottom. This article will use this simplistic model, as shown later in Figure 5. The pyramid’s biggest issue is that it does not highlight how each resource is on a separate bus. In addition, moving information from one resource to another typically involves multiple movements on many buses, each of which consumes power and generates heat.

Figure 4 shows an example in which an application is read from the disk though the CPU across one channel—for instance, a PCIe—to be written to the memory over another channel (for example, a DDR), only to be read back to the CPU one cache line at a time to execute the application and store the temporary results back to the memory.

Figure 4 Here is how data movement demands high power. Source: IEEE

The application may read content across a communications channel, such as PCIe to a wide area network, then crunch that data to be written back to the disk. Even in this simple example, it’s obvious that data processing is an exceptionally minor outcome and that data movement is dominant. The percentage of data operated upon rather than moved around is close to zero as to be unmeasurable.

Why focus on memory?

Memory utilization is a focus area because there is a high potential to make substantial improvements in energy efficiency. Memory consumes as much power as many CPUs, at about 22% of server power. The increasing number of tiers of memory creates both the best and worst of trends.

The good news is that more power-efficient memories are being added closer to the processor. The bad news is that these near-memory tiers have limited capacity and require additional larger capacity, higher power memories to keep filling the datasets into the local memory. The power consumption of each tier adds to the total power footprint.

High bandwidth memory (HBM), for example, offers an interface around 1.5 pJ/bit, which compares favorably to a double data rate memory module at 15pJ/bit (see Figure 5). Unfortunately, these memories still burn significant power—for instance, 75 W or 100 W per HBM stack—and they are co-located with the high-power processor on the same substrate. This makes cooling extremely challenging compared to DDR modules, which are around 15 W each but located farther from the processor in areas that may be air-cooled.

Figure 5 Memory and accompanying storage consume considerable amounts of energy. Source: Monolithic Power Systems

Efficiency by tier

Speculation can improve system performance tremendously, but speculation always implies waste as well—even processor registers have implied waste. A system variable with a 32-bit integer that never assumes a value outside the range 1 to 10 has an implied waste factor of 87.5%. Processor caches have very high hit rates of 95% and higher, so one could invert that number to imply a 5% waste. DRAM access efficiency drops the further the memory is from the processor, with direct attached DDR memory at 27% waste and CXL-attached DDR at over 40% waste.

These numbers may not sound bad until one considers the activity inside each DRAM that allows cache line hit rates. The majority of processors operate with a 64-byte cache line. Consider how 64 bytes map to the internal structure of a DRAM. Each DRAM has an internal page buffer of 1 kB, and DRAMs are typically combined into ranks for 10 DRAMs energized per access (see Figure 6).

Figure 6 DRAMs are typically combined into ranks for 10 DRAMs energized per access. Source: Monolithic Power Systems

To fulfill a single cache line, a DRAM module is “activated” to read 1 kB from each DRAM into its sense amplifiers, or 10 kB across the width of the module. 64 bytes are read and sent to the processor. DRAM activation is destructive—the cells of the memory core are wiped out by the activation—so the cells must be rewritten from the sense amplifiers back into the core. The math for a single random access is 20 kB moved for 64 bytes of work, or 99.7% waste.

This factor of 0.3% efficiency is only against that movement of a 64-byte cache line. If that DRAM tier is operating at a 60% hit rate, efficiency drops to 0.18%. If only 1 byte from that cache line was actually needed, the waste factor increases to 99.98%. As you can see in this simple example, data center efficiency is rapidly approaching zero.

Another form of speculation that improves system performance is execution and access speculation, where a processor may pre-load code on both sides of a branch condition in case the branch is taken. Many SSDs do the same, pre-loading pages that may be accessed. These forms of speculation have 100% waste if the branch is not taken or the access is never made.

Total cost of ownership (TCO)

With electricity access becoming a bottleneck for data center expansion, architects are finally acknowledging that total cost of ownership (TCO) is a primary factor driving system design. While processor vendors focus strictly on performance, their customers are forced to determine whether they can power these machines and cool them. By some estimates, cooling a data center is currently consuming 43% of the cost of operating a data center, which is equivalent to the 43% required to run the machines themselves.

This expenditure is driving architects to measure efficiency not only as petaFLOPS/second but also petaFLOPS/watt-hour.

Improving memory energy efficiency

Improving the accuracy of speculative accesses is an obvious key to taming memory subsystem power consumption. Similar to telling a doctor “It hurts when I do this,” system architects should ask the question, “Is this speculative access successful often enough to pay for the energy consumed?”

For example, if a CXL memory module is in a memory pool and shared by multiple processors, what is the hit rate on any particular bank of DRAM? Should a page be left open, delaying precharge in case of another hit on that row of memory or be closed, issuing the precharge immediately under the assumption it will not be accessed?

Non-uniform memory access (NUMA) has been in server architectures for years to allow tightly coupled processors to share memory resources as demand shifts. However, multiple hops for each memory access can more than triple the power consumed, whereas moving the task to a processor closer to the memory resource can significantly reduce power (see Figure 7). Computational storage is a variation of task relocation that has had some success, though this success is limited by standards for the tasks executed on the devices.

Figure 7 For a server DRAM module, moving the task to a processor closer to the memory resource can significantly reduce power. Source: Monolithic Power Systems

Similarly, placing data in the appropriate tier of memory can have a significant impact on energy consumption. Figure 8 shows the temperature of the data, where hot data is accessed often, and cold data is accessed less often.

Figure 8 Map data based on how often it’s accessed to determine its temperature (where “hotter” data is accessed more often). Source: Monolithic Power Systems

Persistent memory is a system option that can be exploited for data reliability. Persistent memory is either based on a memory technology that does not lose its contents if the power fails (for example, MRAM) or uses an energy source to maintain data integrity by saving DRAM contents in a non-volatile memory (NVM), such as a flash-on power failure. Persistent memory can also be thought of as a significant way to reduce system power by eliminating the need for “checkpointing,” or saving intermediate results (see Figure 9). In many systems, checkpointing is responsible for 7% to 8% of the system traffic and therefore power.

Figure 9 Persistent memory can reduce checkpointing. Source: Monolithic Power Systems

Hybrid memory modules that combine storage and direct access memory on the same module are available to minimize system traffic as well. For example, flash memory mounted as an SSD can be coupled with DRAM, which is directly accessed by a cache line at a time. The efficiency of hybrid modules comes from the statistic of the typical 4-kB block moved from SSD to system memory; only 100 bytes on average are used, which results in an efficiency of only 2.5%.

Software has a huge impact on efficiency

Hardware cannot fix every challenge; software plays a significant role in taming this beast, too. Zooming in on the power consumed by data type, orders of magnitude more power are used for complex and large data types such as floating point, whereas integer math consumes far less power (see Figure 10). This may be as simple as programmers considering the range of values needed by variables in their software. For example, “for (i=0; i<10; i++)” does not need for i to use a 32-bit counter value.

Figure 10 Software plays a significant role in energy consumption. Source: The U.S. Department of Energy

The choice of variable types is sometimes the result of using the wrong programming language for the task (see Figure 11). Not all programming languages allow much flexibility in choosing the data types for variables, and these impacts are magnified tremendously by the matrix math employed by languages such as Python, a common tool for AI applications. Python has another energy-consuming characteristic: the programmer source is compiled to bytecode and then interpreted by a virtual machine as opposed to C programming, which compiles to processor native codes.

Figure 11 Programming languages can be ranked based on their energy consumption. Source: Wireunwired Research

You can’t fix what you can’t measure

Measuring runtime power is a key to tuning efficiency. The voltage regulators for memory modules—such as the MPQ8894, MPQ8895, and MPQ8896—are power management integrated circuits (PMICs) with an integrated system management interface to I2C, I3C, or SidebandBus. This system management interface allows the host system to interrogate the PMIC while the system is running. The current used by each voltage rail can be read from the PMIC to calculate the total power for the memory module while running test and measurement programs, or even while customer applications are running.

Triggers may be configured into the PMICs, and these devices can keep logs of any conditions that exceed the expected maximums. The host system may respond to the triggers by reading the telemetry registers and then acting on those conditions, such as by throttling applications that exceed system-imposed limits.

Choosing the right PMIC is a power-saving measure. With improved 4% power regulation efficiency when compared to competing solutions, this results in a total data center power reduction of 2%. For a typical 300 megawatt-hour installation, this would reduce power by 6 MWh and CO2 emissions by roughly 4 metric tons per year.

The power balancing act

Data centers are projected to keep increasing power demands until they become physically or financially impossible to expand. So, the total cost of ownership has become a focus for all datacenter architects as they balance the needs for performance from their customers with the reality of providing those services in a cost-effective manner.

Data center efficiency, as measured by the data processed vs. data moved around, is embarrassingly low. However, there are several ways to adjust efficiency, from cache management parameters to speculation priorities. Resource and job allocation over fabrics such as NUMA and CXL enable new classes of optimization.

The careful selection of energy efficient components such as voltage regulators can play a significant role in reducing the energy use of a data center. Every percentage of efficiency improvement leads to major reductions in CO2 emissions, a leading cause of pollution. Voltage regulators, for instance, take a holistic view of the system solution, providing high efficiency coupled with methods for measuring and fine tuning the solution to achieve optimal power savings.

Software plays a huge role in efficiency as well, from the low-level allocation of data types to the choice of programming languages for each task. In addition, measuring system efficiency at runtime helps data center operators monitor the health of the system and give insight into ways to improve or limit power as needed. Next, telemetry information helps system software to understand where energy is being used.

Most importantly, TCO analysis requires a change in mindset from operations per second to operations per watt-hour, a major shift forced on the industry by skyrocketing power demand. The use of high efficiency voltage regulators helps reduce data center energy usage, which lowers the cost of providing data services.

Bill Gervasi is principal memory solutions architect at Monolithic Power Systems.

Related Content

• Get a grip on your data center power efficiency
• Why Data Centers Must Become System‑Aware
• Space-Station Tech Pivots to Cool AI Data Centers
• Data Centers in Space: A Brilliant Idea or Delusional?
• Data center power meets rising energy demands amid AI boom

The post Taming the beast: Memory efficiency in an AI/crypto world appeared first on EDN.

Opened up a clock so I can make it a tiny guitar amp. Was not expecting what looks like a ghost got…excited…all over this RadioShack clocks innards. submitted by /u/mrmeatypop [link] [comments]

submitted by /u/1Davide [link] [comments]

submitted by /u/1Davide [link] [comments]

Toshiba is sampling its TXZ+ Entry-Class M4H microcontroller group for small-scale system control of consumer and industrial equipment. Powered by a 120-MHz Arm Cortex-M4 core with an FPU, the devices deliver the real-time performance needed for applications ranging from home appliances to factory automation.

M4H MCUs operate from a 2.7-V to 5.5-V supply, supporting 5-V powered equipment. A built-in high-speed oscillator provides ±1% accuracy across a –40°C to +105°C temperature range, eliminating the need for an external oscillator. Integrated peripherals include a 12-bit ADC, timers, UART, SPI, I²C, and DMA. The devices also feature an advanced programmable motor driver for brushless DC motor control.

Engineering samples are available for evaluation, along with starter kits, sample software, CMSIS-compliant drivers, and support for major IDEs.

TXZ+ Entry-Class M4H product page 

Toshiba Electronic Devices & Storage

The post Entry-level MCUs ease system control appeared first on EDN.

Two 3.3-kV SiC power modules from Wolfspeed target high-voltage energy infrastructure, including AI data centers, renewable energy systems, and grid equipment. The HAB900C33LM4 half-bridge baseplate module supports applications above 800 A, while the IBB020A33GM4 full-bridge baseplate-less module is rated for 100 A. Both modules accommodate 2-kV and higher DC-link architectures, allowing designers to reduce power stages and use simpler 2-level topologies.

Part of the LM platform, the HAB900C33LM4 half-bridge module is intended for converters used in solar, grid-scale energy storage, and wind-power systems. Wolfspeed states that it delivers up to 42% lower switching losses than comparable SiC products and more than 90% lower switching losses than IGBTs under the same test conditions. A member of the WolfPACK family, the IBB020A33GM4 baseplate-less device is designed for modular converter architectures, including solid-state transformers and series-stacked or parallel systems.

Both power modules use Gen 4 SiC technology and advanced packaging techniques, including sintered die attach, to enhance durability and power-cycling performance. Wolfspeed says the modules also maintain switching performance over temperature, helping reduce the size of magnetics and EMI filters while increasing system power density.

Samples of the HAB900C33LM4 and IBB020A33GM4 in industry-standard packages are available through Wolfspeed’s direct sales representatives.

Wolfspeed

The post SiC modules simplify high-voltage topologies appeared first on EDN.