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Discover Angelo, an open source portable audio amplifier designed to improve communication with elderly or hearing-impaired people. This project combines simple electronics with a human-centered approach, making it easy to build, customize, and use.

A antenna tuner circuit which incorporates the resistance of the panel meter light into the accuracy of the meter. One must wonder why they would do this. They no longer support this unit so the bulb is hard to find. It is an axial lead bulb much like a axial lead resistor. I could replace the bulb with a resistor that is the same ohms as the bulb, I suppose. No back lit meter then but at least the meter would work again. Dumb design. submitted by /u/RefrigeratorLess9786 [link] [comments]

Чеська компанія RSE відкрила в КПІ ім. Ігоря Сікорського Energy Resilience Lab з обладнанням MWM Київ, 27 серпня 2026 року KPI4U-2 пт, 08/28/2026 - 16:29

submitted by /u/Dr-Double-A [link] [comments]

Iteration3D is a French web platform that generates customizable 3D models for printing, using a parametric engine to create models on demand based on user specifications.

i had one mechanical keyboard after getting bored i tried to reverse engineer it but i couldn't send any usb data or i could not see much on the terminal when i tried to see if it listens to the data and after opening i saw that it only takes +5v and gnd plus the processor something like BYK.. was a hard coded chip that doesnt listen notes i was newbie to hardware and really scared to try anything. so i gave up but seeing my brother have a kreo rgb keyboard it gave me some boost to open it up and i learned so much and burnt my hand while trying to solder. heck i even burnt the solder iron's wire itself (sniff sniff whats that smell). so the plane was that i would use a mcu as esp 32 or pico that listen to my command and can do anything that i want . first month really .... i bought a mulitmeter and did the traces of all the rows and col sicne there was no pcb and other design files there i didnt know how keyboard matrix works at all i went rhough whole thing.. after getting all the traces and nothing them i was really soul scattered by the fact how this whole thing worked but then i got to know this was a common thing everyone knew this. after this i took pico as the main mcu why... it was small it has higher clock speed. it was one sale since the esp was on boom and the price of pico was dropped it has more computer power that i needed for Fourier transform for disco light that i wanted for the custom rgbs i would put there quickly after that i ran into a problem of less gpio also after that i took a longer time to solder since i was learning and it was very scarry to solder on the pcb but as i did i grew more confident .. after burning my finger prints. i bought a io expander because of 6 rows and 17 cols it got burnt and again tried that was jittering the one signal was affecting other signal. so i gave up 3-4 cols and went for the gpio full on. The RGBs... Hardest the rgb i had to cut each rgb strip stick them all on each keys then use the single core wired without the cover and solder each joints aroung 300 small pieces of them total 600 joints appx and it was tough because heating one end would make other end heat up also. but since i cascaded 100 of them the voltage kept decreasing and it was 0.5v at the end so i just provided supply from both of rows and it worked and there was no deeming and jitters. thats it... if u want to know about the logic behind it then u can ask me i will add it most of things and testing and all the stuff is in the video submitted by /u/shiv20242028 [link] [comments]

Learn how to set up a virtual machine with VirtualBox and install Ubuntu or Kubuntu safely, from downloading the software to enabling Guest Additions and optimizing performance.

I had a lego pack sitting around that I has sorta messed up years ago for somthing, desided see if I could jam a 9v to 5v converter in it, to say the least I sorta went way smaller than I actually needed, in theory it can take 1.5 amps, I wont get even close to that using it, to help with the heat it has some copper sheet attached the sits against the AA to help spread heat from it, parts used are two 10UF caps, ceramic 0.47UF on 9v side and a ceramic 0.1UF on the 5v side, the souldering is a little rough, but this is the smallest thing Ive ever made by far, Im sure it would be better if I did it a few times. submitted by /u/dronko_fire_blaster [link] [comments]

📌 Сесія професорсько-викладацького складу kpi чт, 08/27/2026 - 21:39

BluGlass Ltd of Silverwater, Australia — which develops and manufactures gallium nitride (GaN) visible laser diodes based on its proprietary low-temperature, low-hydrogen remote-plasma chemical vapor deposition (RPCVD) technology — has appointed Yam Rubenstein as a non-executive director to support its growing global operations...

📰 Газета "Київський політехнік" № 27-28 за 2026 (.pdf) Інформація КП чт, 08/27/2026 - 15:54

КПІ ім. Ігоря Сікорського відвідав віцепрезидент і керівник апарату президента американської компанії Lockheed Martin — Річард «Оттер» Б’ю KPI4U-2 чт, 08/27/2026 - 15:13

While updating and streamlining the hardware setup improved the situation, why it achieved this welcome outcome was less clear. And then there was the truly “shocking” discovery…

Last time, in part 1 of this series, I gave a historical overview of my longstanding broadband and television relationship with Comcast (aka Xfinity, the company’s brand for consumer products and services), focusing on the service in my most recent (and current) Colorado residence.

Specifically, I discussed the increasing frequency and severity of service “drop” issues my wife and I experienced subsequent to inadvertent cabling damage consecutively done by our community’s water and sanitation service provider last October and our power company earlier this summer.

At last week’s writeup’s conclusion, I was awaiting the arrival of yet another Comcast technician, subsequent to a recent service issues-escalation to a near-daily cadence (a particular problem given that my wife and I both work from home), an on-site visit which I’d insisted on sticking with in spite of the service’s as-usual temporary resurrection later that same evening. The on-site technician visit wasn’t scheduled until the next afternoon, but he called me mid-morning that (next) day and asked if he could arrive early, a rare deviation from the “late arrival” norm.

Competence is the best

Appreciative of his promptness and hopeful that I could still persuade him into making the debug session gratis for us, I asked him to delay his arrival only 45 minutes until my wife and I had both wrapped up a few work to-dos. He happily obliged, subsequently pulling up on the street in front of our house right on time. I’m not sure whether he was an “official” Comcast employee or a contractor, not that it really matters; his vehicle was a minivan with no corporate markings on it, albeit filled with Xfinity-branded tools, cabling, and other equipment.

I identified myself as a “techie” and asked if I could follow him around, periodically picking his brain and more generally absorbing through observation at least a bit of his conceptual plus experience-accumulated knowledge. He was happy to oblige: “this’ll be fun” were his exact words. And indeed he was smart and nimble of mind, not to mention enthusiastic; a delightful experience, all in all. But he also was in a hurry, so I strove to practice appropriate question-cadence restraint.

The first notable thing I learned from him was that the strand of coax coming out of the ground around the back of the house was completely unrelated to the plastic box labeled “Comcast” attached to the wall on the other (front corner) end of the house, first mentioned and pictorially shown in part 1 of this series.

This cable ran straight to the tap near the street. I assumed it was the mysterious “other line of service that the prior owner had installed” mentioned by the realtor more than a decade earlier.

Speaking of taps, not to mention the RF amplifiers I mentioned last time, along with other constituent building blocks of a hybrid fiber-coax system such as Comcast’s, check out this block diagram from Wikipedia’s as-always thorough, accurate and otherwise excellent entry on the topic.

I don’t know, by the way, where the fiber-to-coax conversion node(s) is/are located in our community, either in general or to what degree of proximity to my residence location.

MIA (not to mention obligatory)

The second thing the technician immediately noticed and I learned, to our mutual great dismay, was that this length of coax was nowhere properly earth-grounded nearby where it entered my home. The plastic box, which I was now realizing was likely associated with the legacy Comcast service likely stretching back to the original owners, was grounded.

As was the tap near the street.

But here? Nothing. Thereby representing not only potentially serious fire and electrocution danger for the home and its occupants but also suggestive of why I’ve endured multiple bouts of electrical shock-induced equipment destruction in my so-far time here (ironically, by the way, there’s a summer-monsoon lightning storm underway as I type this).

Then he saw the three-way splitter attached to the outer wall, which predated (by how long I have no idea) the initiation of my home ownership. Attached to the input end was the PoE (which stands for point-of-entry in this particular case, not power over Ethernet) filter I’d subsequently added for network security purposes back when I was experimenting with MoCA, and which I’d neglected to remove afterwards.

And attached to the splitter outputs were short spans of coax that ended up at wall connectors in two downstairs bedrooms (one each), along with a longer third coax span that also ended up inside, this time in the furnace room, where it split one more time and fed both the CableCARD receiver and cable modem.

After shaking his head and muttering “I don’t know how you even have any broadband service at all” under his breath, he fired up his smartphone, on which was installed a Comcast-proprietary (presumably) app that enabled him to live-monitor my cable modem’s statistics over its WAN connection. Once again, this time louder and more emphatically, he said (and this time also gestured), “I don’t know how you even have any broadband service at all” and invited me to look at the phone display for myself.

I noticed that the upstream transmission power ratings for the various in-use channels were all in the upper 50 dBmV range. I didn’t know much (and still don’t know as much as I’d like) about cable systems, but I knew enough to realize that this wasn’t a good thing.

Swaps and simplifications

Again, I realized he was in a hurry, so I refrained from asking a bunch more questions. He indicated that he thought the existing splitter was left over from a long-past satellite television system installation. I don’t quite buy that theory; although the DC power pass-through support and broader top-end frequency afforded by such a splitter (2.4 GHz vs 1 GHz, with a common 5-MHz bottom end of the range), the latter theoretically allowing for neighbors’ latest-generation MoCA signals to “leak” into my setup, might destructively interfere with my DOCSIS 3.1 modem. So, the PoE filter I’d inadvertently left installed would (or at least should) have alternatively blocked neighborhood noise.

That said, the splitter and filter were admittedly ancient, both also containing passive RF circuitry. So, perhaps something inside either or both had gone awry with advancing age and longstanding lightning, moisture, temperature, and other ambient environmental exposure.

He asked if I was currently using the downstairs bedrooms’ splitter outputs. When I replied in the negative, he wholesale-replaced the splitter with a grounding block (and wire) containing an integrated PoE filter, leaving the other two previous splitter-supplied coax feeds detached.

He also swapped out the connectors on both ends of the new grounding block-plus-PoE filter combo. Then he revisited his smartphone app and happily reported that the data he was seeing was “still not great, but much better now, and good enough”. Again, I got only a brief glimpse of the screen, but enough to confirm that the upstream channels’ power measurements were all now comfortably in the lower end of the 50s dBmV range.

I wish they were even lower than that, but again, we’re at the end of the neighborhood “loop” line. And it’s been more than three weeks (as I write this) since his visit, with not a single service drop, so in the spirit of “perfect is the enemy of good”…I’m good!

In case you were wondering, by the way, I immediately ordered, and subsequently installed as soon as it arrived, a grounding rod to attach to the other end of the grounding block-and-wire he’d generously given me.

The sticker on the side of the rod’s snug plastic packaging was awesome.

When I walked him back to his car (passing by the mysterious plastic box marked Comcast on the way, of which he had no knowledge and no spare time to further explore that day), he gifted me a bunch of extra hardware—MoCA filters, grounding blocks, 2- and 3-way splitters, and a 10’ span of high-quality coax cable with connectors on both ends—all of which I’ll be discussing more in next week’s finale (as planned, but who knows for sure) to this series.

In the upcoming concluding post(s), I’ll suggest some possible theories as to why (and to what degree, straight from my cable modem’s logs) his efforts bore fruit. I’ll also share the results of my subsequent sleuthing regarding the aforementioned mysterious plastic Comcast box and the various cables running into and out of it, as well as what was within it. Stay tuned for that and more; for now, please continue to share your thoughts in the comments!

—Brian Dipert is the associate editor, as well as a contributing editor, at EDN.

Related Content

• Debugging intermittent Comcast, part 1: Scenario-setting
• Will a location change improve my MoCA?
• The whole-house LAN: Achilles-heel alternatives, tradeoffs, and plans
• A quest for faster upstream bandwidth
• Lightning strikes…thrice???!!!

The post Debugging intermittent Comcast, part 2: Remediation details appeared first on EDN.

submitted by /u/ShriKaranHanda [link] [comments]

Почути звук із 13 століття завдяки науковцям ФЕЛ kpi чт, 08/27/2026 - 11:00

SemiQ Inc of Lake Forest, CA, USA — which designs, develops and manufactures custom silicon carbide (SiC) power semiconductors and 150mm SiC epitaxial wafers for high-voltage applications — has announced a distribution agreement with power electronics firm Ibérica Semiconductores de Potencia of Madrid, Spain...

We stand at the dawn of a new era in chip design as artificial intelligence (AI) moves from a conceptual promise to a practical necessity in the semiconductor landscape. Semiconductor companies are looking to AI to help manage design complexity, accelerate development cycles, and maintain the high standards of quality and reliability demanded by the semiconductor industry.

IC design teams are confronting physical, electrical, and reliability verification challenges that require new approaches to achieve acceptable speed and cost. Advanced-node designs bring thousands of design rules, dense hierarchical layouts, and millions of circuit errors that need to be debugged during the design flow. Manual workflows that once sufficed now create schedule bottlenecks which threaten product launches and market windows.

This creates a fundamental tension between speed and risk: Verification teams need AI-driven acceleration to manage complexity and compress schedules, yet IC signoff remains one of engineering’s most risk-averse domains.

A single undetected error can cost millions in respins or field failures. The question facing design organizations is not whether to adopt AI, but how to deploy it in ways that enhance both speed and confidence.

The intelligence foundation: Generative and agentic AI platforms

By balancing advanced algorithms with openness, these platforms can serve design needs while upholding intellectual property (IP) integrity—a crucial factor for building trust. Such systems ensure that designers can tap into a powerful, secure, and customizable environment, enabling continuous learning within a protected infrastructure.

The AI platforms becoming available are designed to integrate across the entire electronic design automation (EDA) tool stack, providing a unified intelligence layer. Figure 1 shows an example of a system architecture that integrates AI models with a multimodal “data lake” to support diverse verification tasks.

Figure 1 In an AI platform for chip design, the internal architecture with AI models and a multimodal data lake underpin the tools for a design flow. Usage modalities are shown on the right. Source: Siemens EDA

Determinism at the core: Why signoff engines must remain AI-free

A strategic consideration in the age of AI is that for the core signoff calculations—which determine whether a chip design is clean and ready for manufacturing—must be done with rigorous, deterministic algorithms, not probabilistic AI models. IC design teams responsible for signoff need confidence that repeated runs will always produce the same results; there is no room for AI “hallucinations” seen with probabilistic models.

This foundation in determinism directly supports trust in any design flow that includes AI. Engineers, managers, and foundry partners must be able to rely on results, providing certainty that each signoff result is the product of rigorous, provable mathematics. Figure 2 illustrates how a deterministic signoff engine remains central to the process, ensuring reproducible analysis and audit-ready results, while AI-powered tools enhance peripheral tasks like setup, error debugging, and collaboration.

Figure 2 This diagram illustrates an AI-augmented signoff process, detailing inputs, the core deterministic signoff engine, AI-accelerated setup, AI-powered error grouping and debug, AI-enabled collaboration tools, and the resulting outputs. Source: Siemens EDA

Productivity revolution: Where AI transforms the verification journey

While the core signoff remains deterministic, the path leading to signoff involves a series of complex phases that are ripe for AI-driven optimization. Leveraging AI in conjunction with deterministic engines is already improving productivity in three primary areas:

Resource optimization

Setting up verification jobs is increasingly complex, time consuming, and error prone due to the number of tasks and different compute environments, from on-premise clusters to the cloud. AI can help engineers manage and optimize these jobs by providing real-time monitoring, actionable recommendations, and post-run analytics. This approach improves hardware usage through compute resource optimization and speeds up job turnaround.

Error debugging and prioritization

One of the biggest bottlenecks in signoff is debugging. Designs at advanced nodes often generate millions of errors in early verification passes. AI-powered tools let designers sift rapidly through enormous error sets by categorizing and prioritizing issues so engineering attention is immediately focused on the most critical problems. In one instance, a leading GPU manufacturer leveraged AI-driven visual analysis to reduce verification time by 50%—translating weeks of effort into just days.

Collaboration and delegation

Modern semiconductor teams are globally dispersed. AI can group errors and assign them to specific team members, ensuring that productivity isn’t lost in handoffs. Applying familiar digital collaboration workflows—such as bookmarking and assignment—in an engineering context brings clarity and speed to what used to be a fragmented process.

AI-driven verification tools, like the one illustrated in Figure 3, integrate full chip analysis with intelligent debug capabilities to streamline error management and team communication.

Figure 3 Modern verification software provides a visual interface for full chip analysis, intelligent debugging through error clustering and prioritization, and enhanced user collaboration for streamlined results distribution. Source: Siemens EDA

Learning and growing with AI-assisted tools

AI in physical or electrical verification is not just about automation for its own sake. Features that provide contextual, in-house documentation and root-cause explanations help both experienced and junior designers understand not only what went wrong, but why it matters and how to fix it.

Incorporation of AI into design tools can be used to capture critical designer knowledge that can be leveraged throughout the organization. In this way, AI is part of the debug process, where a training aid accelerates ramp-up and enables distributed teams to achieve expert-level productivity.

Figure 4 shows how an intelligent interface can display a detailed list of design checks with results, allowing users to add fixing suggestions, view visual comparisons, and access shared notes. In this example, this “assistant” gets more valuable over time as it captures designer expertise every time it’s utilized.

Figure 4 Capturing notes about fixing a violation or displaying shared insights across the organization enhances the design verification flow. Source: Siemens EDA

Keeping IP secure: Customization, openness, and control

Gaining trust in AI also depends on how data is managed and knowledge is shared. A “data lake” approach ensures each organization can incorporate its own designs, best practices, and internal documentation into the AI system—always within a secure, isolated environment. The result is continuous system learning and richer insight that ensures sensitive IP remains strictly within the company boundary.

As design and manufacturing complexity continue to grow, the industry is extending AI-enabled productivity gains to additional domains: layout versus schematic (LVS), electrical reliability, and even automated error correction. The roadmap is ambitious, but the guiding philosophy remains clear: trust the deterministic core and unleash productivity with AI where it adds value.

AI with accountability: A balanced approach

The semiconductor industry’s balance between innovation and risk requires a nuanced approach to AI. By aiming for practical automation around a bedrock of deterministic signoff, design teams can achieve real-time productivity and confidence without compromising on quality or control.

As industry moves toward higher complexity chips, this blend of innovation and trust will be the true differentiator in AI-driven EDA.

Carey Robertson, VP of product management at Siemens EDA, oversees the product development for Calibre Design Side products. He has been with Mentor Graphics/Siemens EDA for 27 years in various product management/engineering roles. Prior to Siemens EDA, Carey was a design engineer at Digital Equipment Corp. (DEC), working on microprocessor design.

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The post How AI is reshaping IC signoff: Trust, speed, and intelligent workflows appeared first on EDN.

Keysight Technologies, today announced that AttoTude Inc., a pioneer of next-generation ASICs over Dielectric interconnect technology for AI and hyperscale data center applications, has expanded its use of Keysight EDA software to manage its full IC design workflow. As a result, AttoTude has reduced its design cycles by more than 50% while achieving first-pass silicon success across advanced RF, sub-THz, and THz tape-outs that underpin its guided-wave interconnect platform.

Design velocity is emerging as a competitive advantage, with global semiconductor revenue forecast to exceed $1.3 trillion in 2026 and AI semiconductors expected to account for 30% of the market. For organizations developing AI interconnect technologies, accelerating silicon development while minimizing costly respins is vital to delivering the required bandwidth, efficiency, and scalability.

AttoTude designs integrated circuits that support per-lane data rates of 200G, 400G, and 800G, where on-chip interconnects behave as waveguides and accurate electromagnetic simulation is essential. With engineers working in parallel on sub-THz and THz subsystems, coordinating workloads without a shared, version-controlled environment makes first-pass silicon success difficult to achieve at scale. With the Keysight Advanced Design System (ADS) platform, AttoTude has cut design cycles to less than six weeks, with designs consistently performing to specification on first silicon.

Utilizing Keysight’s design data management software, AttoTude maintains a single source of truth across its design environment, giving engineers full traceability and visibility at every stage. System-level scenario planning allows the team to explore design trade-offs before committing to silicon, with simulation-to-measurement correlation ensuring results reflect performance. As operating frequencies extend from RF into the sub-THz and THz domains, maintaining consistency between layouts, electromagnetic models, and simulation data becomes critical to delivering reliable silicon.

Richard Chan, ASIC Architect and Development Leader, AttoTude, said: “Developing an ASICs over Dielectric interconnect platform that spans signaling frequencies from 100 GHz to 3 THz requires an exceptional level of design accuracy and simulation fidelity. Keysight’s EDA software has enabled our engineering team to move faster with greater confidence, helping us accelerate development while consistently achieving first-pass silicon success.”

Nilesh Kamdar, General Manager, Keysight EDA, said: “At Keysight, we measure success by what our customers achieve. The next generation of AI infrastructure will be built by the teams that move from design to silicon fastest, and AttoTude is proving what that speed makes possible.”

The post Keysight Accelerates AttoTude IC Design Cycles by More Than 50% appeared first on ELE Times.

The rise of generative AI and large-language models is forcing a complete redesign of data centers in India. Traditional setups designed for 5 to 10 kW per rack simply cannot handle modern GPU clusters, which regularly push power densities beyond 30 to 100 kW. When you hit those numbers, standard air conditioning stops working, and the risk of thermal throttling or total power failure becomes a daily operational challenge.

Running an AI-ready facility today comes down to specialized power electronics, direct-to-chip liquid cooling, heavy-duty physical enclosures, and rock-solid grid stability. Here is how five key infrastructure providers are building the physical hardware behind India’s AI compute push.

1. Delta Electronics India

AI workloads pull massive, continuous surges of electricity while throwing off extreme heat. Delta handles both sides of that equation with specialized power electronics and liquid cooling built explicitly for compute-dense environments. The portfolio centers on megawatt-scale power shelves, high-efficiency UPS systems, and specialized Liquid-to-Liquid (L2L) and Liquid-to-Air (L2A) Cooling Distribution Units (CDUs). By routing direct-to-chip liquid cooling straight to high-TDP processors, Delta keeps Power Usage Effectiveness (PUE) low without letting high-density racks overheat under peak workloads.

2. Eaton India

Training large AI models creates sudden, severe power spikes that can strain local grids and trigger dangerous voltage sags within a facility. Eaton solves this at the power layer with high-density Power Distribution Units (PDUs), energy-storage-ready UPS setups, and smart switchgear designed to buffer heavy load fluctuations. Their systems make it possible to integrate renewable energy directly into high-density data centers while keeping internal power quality steady around the clock.

3. Stulz India

When heat outputs surpass standard HVAC limits, precision thermal management takes over. Stulz specializes in custom direct to-chip and liquid cooling infrastructure, precision air handling, and high-capacity chillers engineered for dense server rooms. Their fluid distribution loops allow operators to shift from hybrid air-water systems toward full liquid cooling setups, keeping sensitive server components running safely without risking heat-induced performance drops.

4. Rittal India

Heavy AI server nodes—packed with multiple GPUs and fluid lines—are drastically heavier and more complex than standard IT equipment. Rittal manufactures industrial-grade modular rack systems, climate-controlled enclosures, and inline cooling manifolds engineered to bear heavy structural loads. Their sealed rack designs integrate liquid lines directly into the enclosure frame, keeping complex server arrays organized, cooled, and isolated within small physical footprints.

5. CoolIT Systems

When rack densities cross the 100 kW mark, pulling heat directly off the silicon becomes non-negotiable. CoolIT builds the custom cold plates, fluid distribution manifolds, and heat-exchange units that sit directly on top of high-performance chips. Partnering with global server OEMs and data center builders, they provide the internal liquid loops necessary to keep high frequency processors running cool under continuous parallel processing loads.

Building the Foundation for AI Compute

India’s AI growth depends entirely on what is happening on the server room floor. The real work is being done by high efficiency power converters, liquid cooling loops, robust enclosures, and stable sub-stations. As compute demands scale up, these hardware manufacturers are laying down the actual foundation that makes real-world AI processing possible.

The post 5 Technology Companies Powering India’s AI Data Center Infrastructure appeared first on ELE Times.