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Fabless firm Cambridge GaN Devices Ltd (CGD) — which was spun out of the University of Cambridge in 2016 to design, develop and commercialize power transistors and ICs that use GaN-on-silicon substrates — has appointed Fabio Necco as chief executive officer. The move is designed to drive forward CGD’s entry into key markets...

This is an SoC Camera sensor and controller from an old webcam likely manufactured in the early 2000s hence that chip is manufactured in 2004 (the year i was born in lol) i found this camera in my grandparents house a decade ago i grapped it as a kid and thought it was cool and disassembled it and through it in a big plastic bag along with my cool junk collection. A decade later i found it's pcb (the shell is no where to be found lol) and desoldered it's components and found that SoC chip that i thought it's pretty cool! submitted by /u/inevitable_47 [link] [comments]

While Wi-Fi 7 adoption is accelerating among enterprises, Wi-Fi 8 routers and mesh systems could arrive as early as summer 2026. It’s important to note that the IEEE 802.11bn standard, widely known as Wi-Fi 8, is expected to be ratified in 2028. So, the gap between Wi-Fi 7’s launch and the potential availability of Wi-Fi 8 products in mid-2026 could shorten the typical cycle between Wi-Fi generations.

At CES 2026 in Las Vegas, Nevada, wireless chip vendors like Broadcom and MediaTek are unveiling their Wi-Fi silicon offerings. ASUS is also conducting real-world throughput tests of its Wi-Fi 8 concept routers at CES 2026.

Figure 1 Wi-Fi 8 aims to deliver a system-wide upgrade across speed, capacity, reach, and reliability. Source: Broadcom

Wi-Fi 8—aimed at boosting reliability and reducing latency in dense, interference-prone environments—marks a shift in Wi-Fi evolution. While Wi-Fi 8 maintains the same theoretical maximum data rate as Wi-Fi 7, it aims to improve effective throughput, reduce packet loss, and decrease latency for time-sensitive applications.

Another notable feature of Wi-Fi 8 designs is the incorporation of AI ingredients. Below is a short profile of an AI accelerator chip that claims to facilitate real-time agentic applications for residential consumers.

AI accelerator for Wi-Fi 8

Wi-Fi 8 proponents are quick to point out that it connects the wireless world with the AI future through highly reliable connectivity and low-latency responsiveness. Real-time, latency-sensitive applications are increasingly seeking to employ agentic AI, and for that, Wi-Fi 8 aims to prioritize consistent performance under challenging conditions.

Broadcom’s new accelerated processing unit (APU), unveiled at CES 2026, combines compute and networking ingredients with AI acceleration in a single silicon device. BCM4918—a system-on-chip (SoC) device blending compute acceleration, advanced networking, and security—aims to deliver high throughput, low latency, and intelligent optimization needed for the emerging AI-driven connected ecosystem.

The new AI accelerator for Wi-Fi 8 integrates a neural engine for on-device AI/ML inference and acceleration. It also incorporates networking engines to offload both wired and wireless data paths, enabling complete CPU bypass of all networking traffic. For built-in security, cryptographic protocol acceleration ensures end-to-end data protection without performance compromise.

“Our new BCM4918 APU, along with our full portfolio of Wi-Fi 8 chipsets, form the foundation of an AI-ready platform that not only enables immersive, intelligent user experiences but also does so with efficiency, security, and sustainability at its core,” said Mark Gonikberg, senior VP and GM of Broadcom’s Wireless and Broadband Communications Division.

Figure 2 When paired with BCM6714 and BCM6719 dual-band radios, BCM4918 APU allows designers to develop a unified compute-and-connectivity architecture. Source: Broadcom

AI compute plus connectivity

The BCM4918 APU is paired with two new dual-band Wi-Fi 8 radio devices: BCM6714 and BCM6719. While combining 2.4 GHz and 5 GHz operation into a single piece of silicon, these Wi-Fi 8 radios also feature on-chip 2.4-GHz power amplifiers, reducing external components and improving RF efficiency.

These dual-band radios, when paired with the BCM4918 APU, allow design engineers to quickly develop a unified compute-and-connectivity architecture that enables edge-AI processing, real-time optimization, and adaptive intelligence. The APU and dual-band radios for Wi-Fi 8 are now available to early access customers and partners.

Broadcom’s Gonikberg says that Wi-Fi 8 represents a turning point where broadband, connectivity, compute, and intelligence truly converge. The fact that it’s arriving ahead of schedule is a testament to its convergence merits, and that it’s more than a speed upgrade and could transform connection stability and responsiveness.

Related Content

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• Exploring the superior capabilities of Wi-Fi 7 over Wi-Fi 6
• Understanding the Differences Between Wi-Fi HaLow and Wi-Fi
• Chipsets brings Wi-Fi 7 to a broad range of wireless applications
• Europe Focuses on 6GHz Regulation, While Wi-Fi 7 Looms Beyond

The post CES 2026: Wi-Fi 8 silicon on the horizon with an AI touch appeared first on EDN.

Ages ago, humankind crawled out of the primordial analog ooze and began to do digital. They soon noticed and quantified a fundamental need to interconnect their new quantized numerical novelties with the classic continuum of the ancestral engineer’s world. Thus arose the ADC.

Of course, there were (and are) an abundance of ADC schemes and schematics. One of the earliest and simplest of these was the single-slope type.

Single slope ADCs come in two savory flavors. In one, a linear analog voltage ramp is generated and compared to the input signal. The time required for the ramp to rise from zero (or near) to equality with the input is proportional to the input’s amplitude and taken as its digital conversion. 

We recently saw an example contributed by Dr. Jordan Dimitrov to our own friendly Design Idea (DI) corner in “Voltage-to-period converter offers high linearity and fast operation.”

In a different cultivar of the single sloper, a capacitor is charged to the input voltage, then linearly ramped down to zero. The time required to do that is proportional to Vin and counts (pun!) as the conversion result. An (extremely!) simple and cheap example of this type was published here about two and a half years ago in “A “free” ADC.”

Wow the engineering world with your unique design: Design Ideas Submission Guide

While simple and cheap are undeniably good things, too much of a good thing is sometimes not such a good thing. The circuit in Figure 1 adds a few refinements (and a bit more cost) to that basic design in pursuit of an order of magnitude (or two) better accuracy and perhaps a bit more speed.

Figure 1 Simple speedy single-slope (SSSS) ADC biphasic conversion cycle.

Here’s how it works:

1. (CONVERT = 1) switch U1 charges C1 to Vin
2. (CONVERT = 0) C1 is linearly discharged by 100 µA current sourced by Z1Q1

Note: Z1, C1, and R2 should be precision types.

Conversion occurs in two phases, selected by one GPIO bit configured for output (CONVERT/ACQUIRE).

During the ACQUIRE (1) interval SPDT switch U1 connects integrator capacitor C1 to the input source, charging it to Vin. The acquisition time constant of the charging is:

C1(R sZ1+ U1 Ron, + Q2’s input impedance) = ~10 µs

To complete the charge to ½-lsb-precision at 12-bit resolution, this needs an ACQUIRE interval of:

10µs*loge(2(12+1)) = 90µs

The controlling microcontroller can then return CONVERT to zero, which switches the input side of C1 to ground, driving the base of the comparator transistor negative for a voltage step of –Vin, plus a “smidgen” (~12 mV).

This last is contributed by C2 to compensate for the zero offset that would otherwise accrue from Q2’s finite voltage gain and storage time.

Q1’s emergence from saturation drives INTEGRATE positive. Here it remains until the discharge of C1 is complete and Q1 turns back ON. This interval is:

Vin*C1 / 100µA = 200µs/v = 1-ms maximum

If the connected counter/peripheral runs at 20 MHz, then the max-count accumulation and conversion resolution will be 4000, or 11.97 bits.

This 1-ms, or ~12-bit, conversion cycle is sketched in Figure 2.  Note that good integral nonlinearity (INL) and differential nonlinearity (DNL) are inherent.

Figure 2 The SSSS ADC waveshapes. The ACQUIRE duration (12 bits) is 90 µs. The INTEGRATE duration is 1ms max (Vin C1 / Iq1 = 200 µs/V). Amplitude is 5 Vpp.

 Of course, not all signal sources will gracefully tolerate the loading imposed by this conversion sequence, and not all applications will find the tolerance of available LM4041 references and R1C1 adequately precise.

Figure 3 shows fixes for both of these limitations. A typical RRIO CMOS amplifier for A1 eliminates the input loading problem, and the R5 trim provides a convenient means for improving conversion calibration.

Figure 3 A1 input buffer unloads Vin, and R5 calibration trim improves accuracy.

Stephen Woodward’s relationship with EDN’s DI column goes back quite a long way. Over 100 submissions have been accepted since his first contribution back in 1974.

Related Content

• Voltage-to-period converter offers high linearity and fast operation
• A “free” ADC
• Another weird 555 ADC
• 15-bit voltage-to-time ADC for “Proper Function” anemometer linearization

The post Simple speedy single-slope ADC appeared first on EDN.

Courtesy: Cadence

Are you still relying solely on simulation to validate your RTL design? Is there any more validation required?

Simulation has been a cornerstone of hardware verification for decades. Its ability to generate random stimuli and validate RTL across diverse scenarios has helped engineers uncover countless issues and ensure robust designs. However, simulation is inherently scenario-driven, which means certain rare corner cases can remain undetected despite extensive testing.

This is where formal verification adds significant value. Formal doesn’t just simply mathematically analyse the entire state space of your design; it checks every possible value and transition your design could ever encounter, providing exhaustive coverage that complements simulation. No corner case is left unchecked. No bug is left hiding. Together, they form a powerful verification strategy.

Why Formal Matters in Modern Validation

Any modern validation effort needs to take advantage of formal verification, where the apps in the Jasper Formal Verification Platform analyse a mathematical model of RTL design and find corner-case design bugs without needing test vectors. This can add value across the design and validation cycle. Let’s look at some standout Jasper applications: Jasper’s Superlint and Visualise can help designers to quickly find potential issues or examine RTL behaviours without formal expertise. Jasper’s FPV (Formal Property Verification) allows formal experts to create a formal environment and sign off on the IP, delivering the highest design quality and better productivity than doing block-level simulation. Jasper’s C2RTL is used to exhaustively verify critical math functions in CPUs, GPUs, TPUs, and other AI accelerator chips.

Jasper enables thorough validation in various targeted domains, including low power, security, safety, SoC integration, and high-level synthesis verification.

“The core benefit of formal exhaustive analysis is its ability to explore all scenarios, especially ones that are hard for humans to anticipate and create tests for in simulation.”

Why Formal? Why Now?

Here’s why formal verification matters now:

• No more test vectors or random stimuli. Formally, mathematically, and automatically explores all reachable states; verification can start as soon as RTL is available without the need to create a simulation testbench.
• Powerful for exploring corner-case bugs. Exhaustive formal analysis can catch corner case bugs that escape even the most creative simulation testbenches.
• Early design bring-up made easy. Validate critical properties and interfaces before your full system is ready.
• Debugging is a breeze. When something fails, formal provides a precise counterexample, often with the shortest trace, eliminating the need for endless log hunting.
• Perfect partnership with simulation. Simulation and formal aren’t rivals; they are partners. Use simulation for broad system-level checks, and Formal for exhaustive property checking and signoff of critical blocks. Merge formal and simulation coverage for complete verification signoff.

Conclusion

As RTL designs grow in complexity and stakes rise across power, safety, and performance, relying on simulation alone is no longer enough. While simulation remains indispensable for system-level validation, formal verification fills the critical gaps by exhaustively exploring every reachable state and uncovering corner-case bugs that would otherwise slip through. By integrating formal early and throughout the design cycle, teams can accelerate bring-up, improve debug efficiency, and achieve higher confidence at signoff. In today’s silicon landscape, the most robust verification strategy isn’t about choosing between simulation and formal—it’s about combining both to ensure no bug goes unnoticed and no risk is left unchecked.

The post Don’t Let Your RTL Designs Get Bugged! appeared first on ELE Times.