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Altera is now sampling its Agilex 9 Direct RF AGRW039 wideband SoC FPGA for aerospace, defense, and communication systems. According to Altera, the device delivers a 40% increase in compute capability per square millimeter. It also provides 45% greater logic and DSP density than the previous generation and supports DDR5 and LPDDR5 memory technologies.

With integrated 64-Gsample/s wideband RF and increased compute and memory resources, the programmable device eliminates the need for multichip designs and enables advanced beamforming, radar, and data cube processing. The AGRW039 provides high-bandwidth signal capture and generation, allowing customers to scale performance while maintaining design flexibility.

Agilex 9 Direct RF SoC FPGAs combine high-speed data converters, programmable logic, and processing elements in a single package. The integrated architecture helps reduce system complexity and power consumption for wideband RF applications that require real-time performance.

Production silicon and development kits for the Agilex 9 Direct RF AGRW039 are expected to be available in Q3 2026.

Agilex 9 Direct RF series

Altera

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Navitas has developed a TO-247 package offering more than 6000 V of isolation for its 1200-V, 2300-V, and 3300-V SiC MOSFETs. Designated the UHV-TO-247-4-ISO, the through-hole package supports direct-cooled thermal management through a reflow-compatible isolated thermal pad. It also provides over 12 mm of pin-to-pin creepage, enabling module-level performance in a compact discrete form factor.

Compared to standard non-isolated through-hole packages, the UHV-TO-247-4-ISO reduces the need for external high-voltage isolation while improving thermal and EMI performance. These benefits extend to high-voltage grid-tied power conversion systems, solid-state transformers, battery energy storage systems, and renewable energy applications.

The UHV-TO-247-4-ISO delivers integrated high-voltage isolation using an AlN substrate, reducing die-to-heatsink capacitance and helping lower common-mode noise and radiated EMI. Its reflow-compatible, direct-cooled thermal interface enables direct mounting to liquid- or air-cooled heatsinks, improving thermal performance while eliminating the need for external TIM and isolation materials. The package also enhances thermal cycling and power cycling lifetime through its AlN/AMB construction and robust heatsink interface.

To request samples or additional product information, please contact a Navitas sales representative or email info@navitassemi.com.

Navitas Semiconductor 

The post TO-247 SiC package boosts high-voltage isolation appeared first on EDN.

Deposition equipment maker Aixtron SE of Herzogenrath, near Aachen, Germany has announced a strategic production partnership with ROHM Semiconductor, which has selected Aixtron’s G10-GaN metal-organic chemical vapor deposition (MOCVD) system to establish in-house gallium nitride (GaN) epitaxy at its Hamamatsu plant in Japan. The system is currently ramping for volume production of 8-inch GaN epitaxial wafers for 650V and 100V power device platforms...

Efficient Power Conversion Corp (EPC) of El Segundo, CA, USA — which makes enhancement-mode gallium nitride on silicon (eGaN) power field-effect transistors (FETs) and integrated circuits for power management applications — has introduced the EPC91132, a compact 3-phase BLDC motor drive inverter reference design based on the EPC33110 GaN three-phase module...

Efficient Power Conversion Corp (EPC) of El Segundo, CA, USA — which makes enhancement-mode gallium nitride on silicon (eGaN) power field-effect transistors (FETs) and integrated circuits for power management applications — says that its new EPC2378 25V eGaN power transistor has entered mass production, enabling high-density power system designers to achieve higher efficiency, faster switching and greater power density in demanding DC–DC conversion applications. EPC2378 is optimized for synchronous rectifier applications on the secondary side of a 48V-8 or 5V LLC converter. In addition to what is claimed to be the best-in-class 410µΩ typical RDS(on), the devices have an industry-leading low RDS(on) x QG figure of merit that enables higher-frequency and higher-efficiency operation. These capabilities are of particular value in fast-growth markets such as AI infrastructure, data centers, telecom, industrial systems and advanced computing platforms...

Lotus Microsystems’ vStrata vertical power delivery platform targets the electrical, thermal, and mechanical challenges of AI infrastructure. The first module in the vStrata Power Series, the LS0580, is a fully integrated power-system-in-package (PSiP) that places power conversion closer to the load to reduce distribution losses and board complexity. The device has completed tape-out for leading CPU, GPU, and AI accelerator platforms, with engineering samples shipping in Q3 2026.

Built on a silicon-based substrate, vStrata combines power delivery, thermal management, and packaging in a single architecture. Designed for kiloampere-class AI workloads, the platform delivers up to 96% point-of-load efficiency while reducing power losses and thermal constraints. Its low-profile vertical architecture is enabled by silicon PIT technology, supporting ultra-thin designs below 1 mm by placing power directly beneath the processor to shorten electrical paths and improve transient response.

The vStrata platform is compatible with existing power management controllers and reference designs. Lotus is currently evaluating the platform with hyperscale customers and additional partners through an early access program.

vStrata product page

Lotus Microsystems 

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The Melexis MLX92344 is a 2-wire, 2-bit Hall-effect switch for contactless detection of up to four positions in automotive body electronics. Unlike conventional microswitch-based approaches that often require multiple mechanical switches to detect intermediate positions, the MLX92344 simplifies system design by providing programmable current levels and magnetic thresholds. It is suited for applications such as seat track positioning, soft-closing doors, and multilevel trunk locks.

A dual programmable architecture lets designers assign output current levels directly to the device’s magnetic operating and release thresholds, with temperature compensation for both neodymium and ferrite magnets. Up to four different current levels can be configured between 3 mA and 28 mA, enabling the MLX92344 to emulate standard microswitch interfaces while maintaining compatibility with existing hardware and ECUs. The device can be sensed through standard I/O triggers or an ADC, requiring only software readout adjustments.

The MLX92344 offers a wide magnetic operating range from 0.5 mT to 200 mT. It is ASIL B SEooC compliant, AEC-Q100 qualified, and operates from 2.7 V to 28 V over a temperature range of -40°C to +150°C. The switch is available in both surface-mount and through-hole packages.

MLX92344 product page 

Melexis

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NVIDIA has unveiled the RTX Spark, a “superchip” delivering up to 1 petaflop of AI compute to enable Windows PCs to run personal AI agents. The device combines 128 GB of unified memory with an NVIDIA Blackwell RTX GPU featuring 6,144 CUDA cores and fifth-generation Tensor Cores that provide FP4 precision. The GPU connects to a high-performance 20-core Grace CPU via the NVLink-C2 chip-to-chip interconnect.

NVIDIA collaborated with MediaTek on the custom CPU design, contributing to strong power efficiency, performance, and connectivity. NVIDIA also partnered with Microsoft to deliver a secure Windows platform for on-device agents, incorporating new Windows security primitives and the NVIDIA OpenShell runtime to safely run autonomous AI agents.

RTX Spark brings NVIDIA’s AI and graphics technologies to creators, developers, and gamers. It can run 120-billion-parameter language models, render large 3D scenes, and accelerate 12K video editing. For gaming, the platform supports ray tracing and NVIDIA DLSS technologies for enhanced visual quality and performance.

RTX Spark-based laptops and compact desktops will be available this fall from leading manufacturers.

RTX Spark product page 

NVIDIA

The post NVIDIA chip powers local AI workloads appeared first on EDN.

The first article in this silicon governance series established a fundamental reality: observability is not automatically governed evidence. Advanced AI silicon platforms generate a massive stream of runtime telemetry, including network-on-chip (NoC) counters, voltage diagnostics, thermal maps, memory-state logs, firmware traces, error signatures, and workload-dependent behavior. But raw observability alone lacks the context, synchronization, and causality required to explain physical system behavior.

The second article extended that thesis into runtime operation by introducing the firmware–hardware handshake. Hardware senses transient states. Firmware executes localized, bounded actions. A governance layer determines whether those runtime actions remain valid, safe, and causally justified.

This third article closes the loop.

Once complex AI accelerators, multi-die chiplets, HBM modules, advanced heterogeneous packages, and cloud-scale systems are deployed at enterprise scale, a new question appears. How does field evidence refine future silicon, package, firmware, and system decisions without creating an uncontrolled feedback loop of autonomous adaptation?

That question requires fleet learning to operate under bounded gate authority. The operating principle is simple: Fleet learning recommends and bounded gate authority approves.

Fleet learning can identify macro-scale failure signatures, detect structural drift across deployed systems, and recommend policy refinement. But fleet learning should not independently close development gates, alter firmware release criteria, rewrite operating envelopes, or approve lifecycle actions.

That final step requires bounded decision authority.

From single-chip handshake to cluster-scale drift

The firmware–hardware handshake begins locally.

A voltage droop appears on an internal rail.

• A thermal sensor reports a localized hot spot.
• A SerDes lane loses operating margin.
• A memory controller logs an error correcting code (ECC) event.
• Firmware responds through a pre-validated, bounded action envelope.

At the single-device level, this can preserve operation. But modern AI infrastructure does not operate as isolated silicon. Instead, a single accelerator becomes a board.

• A board integrates into a rack.
• A rack scales into a data-center cluster.
• A cluster becomes a globally distributed fleet.

At that scale, localized runtime compensation is no longer sufficient. Thousands of multi-die devices operating under shifting workloads begin to reveal multi-physics patterns that no isolated lab test, qualification plan, or pre-silicon simulation could fully predict.

A high-speed SerDes retraining event may appear harmless on one device. Across a fleet, it may reveal an advanced-package escape, connector-aging issue, or workload-dependent signal-integrity margin deficit.

A recurrent voltage droop may look like firmware tuning noise. Across many systems, it may correlate with one package substrate lot, one raw-material source, one board configuration, or one power delivery network (PDN) resonance condition.

A persistent thermal asymmetry may look like a local cooling issue. Across a data-center tier, it may expose thermal interface material (TIM) variation, substrate warpage, lid-attach tolerance, or airflow interaction. Next, scattered ECC events may appear random. Across workload, voltage, temperature, memory location, and package population, they may reveal a wafer-to-package interaction or localized timing drift.

The purpose of fleet learning is not to collect more telemetry; the purpose is to normalize field behavior into governed lifecycle evidence.

Telemetry is not convergence

Modern AI clusters are already saturated with logging mechanisms. They continuously capture physical, electrical, firmware, and workload states. But this raw telemetry stream is not system convergence. A monitoring dashboard can flag a symptom.

• A generic AI model can identify a statistical correlation.
• An error log can timestamp an interruption.
• A fleet database can reveal clustering.

But none of those observations automatically confirms physical causality.

A recurring signal-integrity degradation event may look like normal channel aging. In reality, the root cause could be board-level connector variation, package escape routing discontinuity, local thermal expansion, substrate variation, return-path interruption, or mechanical stress accumulation at the package-to-board interface.

A voltage instability event may look like a firmware behavior. In reality, it may originate from package inductance, PDN resonance, voltage regulator module (VRM) response, decoupling placement, silicon switching current, or thermal drift.

A thermal excursion may look like a cooling problem. In reality, it may involve workload placement, TIM thickness, lid attach, airflow, die placement, package warpage, or power-map concentration. This is why unconstrained AI analytics can be risky in high-reliability semiconductor environments.

A system that blindly changes operating bounds based on weakly governed telemetry may optimize the wrong variable, amplify false correlations, mask physical defects, or push firmware parameters outside validated design boundaries. But the objective is not more raw data; the objective is trusted, admissible evidence.

SEGA-AI response: A governed feedback architecture

Fleet learning within the SEGA-AI/governance for lifecycle stack is fundamentally different from standard cloud-level log analytics.

• It’s not generic telemetry analytics.
• It’s not unconstrained AI optimization
• It’s not self-modifying infrastructure

Fleet learning is a governed realization-feedback architecture. Its purpose is to connect deployed behavior back to the assumptions made during pre-silicon design, packaging floor-planning, post-silicon validation, qualification, manufacturing release, and firmware policy definition.

It asks: 

• Was the original design guardband correct?
• Was the package-level simulation model complete?
• Did the system EM corridor have enough high-frequency margin?
• Did the physical PDN respond as predicted under maximum dI/dt load steps?
• Did the firmware policy preserve global convergence or only local stability?
• Did one package lot behave differently from another?
• Did one board configuration or connector population age differently?
• Did field behavior expose a validation escape?

This transforms the field from a passive reliability archive into an active lifecycle evidence source. But the field does not rule the system. Instead, deployed behavior informs the governance stack, and bounded gate authority governs the decision.

Fleet learning recommends and bounded gate authority approves

The most important safety principle is that fleet Learning can recommend refinement, but bounded gate authority must approve action.

This prevents a dangerous failure mode: allowing field data, machine learning, or runtime analytics to directly modify firmware policy, release criteria, validation guardbands, or corrective-action rules without sufficient evidence authority.

In large fleets, an unsafe automated update can create systemic instability. A local firmware action that works on one device may create thermal imbalance across a rack. A voltage policy that improves one workload may reduce aging margin elsewhere. A SerDes retraining policy may preserve one link but increase synchronization overhead across a cluster.

Therefore, fleet-scale learning must pass through a multi-state decision gate. Here, bounded gate authority can issue one of six outcomes.

1. Close: The fleet evidence is mature, admissible, causally verified, and sufficient to advance the configuration.
2. Remain open: The evidence is immature, stale, incomplete, conflicting, or not yet tied to critical to quality (CTQ) parameters.
3. Reopen: Authoritative fleet evidence invalidates a previously closed validation, firmware, package, or release assumption.
4. Escalate: Uncertainty, risk severity, or cross-domain conflict exceeds the bounded authority envelope and requires human engineering review.
5. Approve bounded action: A limited mitigation is allowed inside a pre-validated safe envelope, such as narrowing a frequency range, changing a retraining threshold, adjusting a voltage policy, or applying a lot-specific firmware constraint.
6. Block release: A critical CTQ, causality path, or reliability condition remains unresolved.

This is the difference between learning from the fleet and being controlled by the fleet. Fleet learning identifies the pattern; bounded gate authority decides whether the pattern is mature enough to authorize action.

Example 1: SerDes retraining across a fleet

Consider a high-speed SerDes interface operating across thousands of deployed systems. A single lane retraining event may not be alarming. It may result from temperature, workload burst, supply noise, aging, or normal link management. But if fleet learning detects repeated retraining patterns across a specific package lot, board revision, connector family, thermal condition, or workload pattern, the signal becomes more important.

The system must ask:

• Is this random runtime behavior or a repeatable system EM corridor weakness?
• Does the pattern correlate with package escape, PCB material, connector transition, thermal gradient, return-path discontinuity, or voltage noise?
• Does it appear only under specific workloads or across all operating conditions?
• Does retraining preserve operation, or does it mask progressive margin loss?

Fleet learning can recommend a refinement: adjust validation thresholds, update link-margin assumptions, modify firmware retraining policy, or reopen a system EM corridor gate. But bounded gate authority decides whether that recommendation is admissible and actionable.

The gate should not close until the evidence is mature enough to distinguish a transient workload excursion from a real corridor degradation pattern.

Example 2: Voltage droop tied to one package lot

A runtime voltage droop may initially appear as a firmware or VRM issue. But fleet-scale evidence may show that the event occurs more frequently in systems built from one package lot, one substrate batch, one board stackup, one decoupling configuration, or one supplier population. That changes the engineering question.

The issue may involve package inductance, silicon switching current, decoupling placement, VRM response, PDN anti-resonance, substrate variation, thermal concentration, or workload-driven current transients.

Fleet learning can identify the population-level pattern. But the decision cannot be automatic. Bounded gate authority must determine whether the evidence is strong enough to reopen a package PDN assumption.

• Adjust firmware voltage policy
• Change validation stress conditions
• Hold a package lot
• Escalate to package reliability or failure analysis
• Approve a bounded runtime mitigation

The field may reveal the pattern, but the gate determines authority.

Example 3: Thermal asymmetry and package realization

Thermal asymmetry is common in AI systems because workloads are uneven, packages are large, and cooling solutions interact with board and chassis design. A single hot region may not prove a package problem.

But if repeated thermal asymmetry appears across a fleet and correlates with package construction, TIM behavior, lid attach, substrate warpage, airflow condition, or power map, it becomes lifecycle evidence. Here, fleet Learning may recommend updates to thermal guardbands.

• Package model assumptions
• Assembly admissibility criteria
• Firmware workload placement
• Throttling thresholds
• Future validation conditions

However, bounded gate authority must decide whether the evidence is mature enough to change policy. Otherwise, the system risks overcorrecting a local symptom and creating a new global instability.

Example 4: ECC events under workload and temperature

ECC events are another important fleet signal. An isolated ECC event may not indicate a major issue. But patterns across workload, temperature, voltage, memory stack, package lot, board configuration, or aging profile may reveal a deeper convergence problem. The source may be memory behavior, power noise, package stress, thermal gradients, firmware scheduling, silicon aging, or a wafer-to-package interaction.

Fleet learning can detect that the event population is no longer random. Next, bounded gate authority must determine whether to remain open and collect more evidence.

• Reopen a validation assumption
• Escalate to memory, package, or system teams
• Approve a bounded firmware mitigation
• Block a release configuration
• Refine next-generation design constraints

Again, the value is not only anomaly detection; it’s also governed lifecycle authority.

Example 5: When local firmware action creates fleet-level drift

The firmware–hardware handshake allows local corrective action. That is necessary. But local action can create fleet-level consequences.

A firmware policy that throttles one tile may preserve local thermal margin but shift workload stress to another region. A voltage adjustment may stabilize one condition but accelerate aging under another workload. A SerDes retraining rule may improve link continuity but increase synchronization overhead, operational variability, or latency across a cluster.

So, fleet learning is needed to detect these second-order effects. And bounded gate authority is needed to prevent uncontrolled policy changes.

So, the system must ask:

• Is the local action preserving global convergence?
• Is the firmware response still inside the approved action envelope?
• Does the correction create hidden thermal, timing, power, or reliability debt?
• Should the action remain approved, be narrowed, be escalated, or be retired?

This is the lifecycle version of the firmware–hardware handshake. Runtime action is not enough, and it must remain governed as fleet evidence accumulates.

Realization in practice: Reopening a validation assumption

Consider a next-generation AI accelerator cluster that successfully cleared pre-silicon signoff, post-silicon validation, and package-level qualification. After several months of deployment, firmware on multiple independent racks begins executing repeated SerDes link retraining sequences. A standard facility log may classify these events as isolated thermal excursions or normal link maintenance.

A governed fleet learning system treats the events differently. It aggregates the retraining events across the fleet, normalizes timestamps, maps them against package lots and board configurations, and compares them with workload signatures, thermal maps, substrate data, and system operating conditions.

The pattern becomes clear: the retraining events occur after localized multi-core workload bursts that generate a thermal gradient across a specific package/substrate population. This is no longer random operational noise. It’s a possible validation escape where real-world multi-physics interaction has violated an original design or package guardband.

Fleet learning generates the recommendation. And bounded gate authority evaluates the evidence package, checks admissibility, verifies causality, and may issue a Reopen outcome on the affected configuration milestone.

The system should not blindly mask the issue through continuous retraining. Instead, it can approve a bounded mitigation for the affected population while sending convergence-authoritative evidence back to validation, package engineering, firmware teams, and pre-silicon architecture groups.

That is the lifecycle loop. Field evidence does not simply become a log; it becomes governed input for the next design, package, validation, and firmware policy decision.

Closing the loop back to design and validation

The most important output of fleet learning is not only field mitigation; it’s lifecycle refinement. Mature fleet evidence should flow back into pre-silicon design assumptions.

• Package constraints
• System EM corridor models
• PDN and CPAM assumptions
• Firmware policies
• Thermal guardbands
• Qualification thresholds
• Design for test (DFT) and observability planning
• Manufacturing tolerances
• Supplier and lot-level evidence models
• Next-generation architecture decisions

This is how the silicon governance loop closes and the field becomes a governed evidence source for the next design cycle. But only if the evidence is admissible.

That requires the SEGA-AI stack in which test case generator (TCG) protects trust and admissibility.

• Convergence evidence maturity hierarchy (CEMH) defines evidence maturity
• Fleet learning recommends lifecycle refinement
• Bounded gate authority approves the decision

Without this structure, field telemetry remains operational logging. With this structure, field telemetry becomes lifecycle convergence evidence.

The SEGA-AI view

From a SEGA-AI perspective, fleet learning is not an uncontrolled feedback loop. It’s a governed lifecycle refinement system; it does not replace engineering judgment.

• It does not replace firmware teams.
• It does not replace validation.
• It does not replace failure analysis.
• It does not independently close gates.

It connects runtime behavior to governed decision authority. That allows deployed systems to improve future realization decisions while preserving deterministic control. And that is the difference between learning from the fleet and being controlled by the fleet.

Closing the silicon governance loop

The semiconductor industry has moved beyond isolated design-time closure. In the era of hyperscale AI platforms, multi-die chiplets, HBM systems, advanced packages, and volatile workloads, no single signoff event can guarantee long-term physical convergence across thousands of deployed systems.

The answer is not unconstrained autonomous adaptation. The answer is governed lifecycle learning.

Fleet learning provides the analytical path to uncover systemic patterns, detect drift, and recommend refinement. Bounded gate authority provides the engineering boundary that determines whether those recommendations are mature, admissible, causally aligned, and safe enough to act upon.

Together, they close the silicon governance loop.

Dr. Moh Kolbehdari is senior director of IC/packaging at Socionext US.

Editor’s Note

This is Part 3 of the article series about silicon governance framework. Part 1 explained why data movement alone cannot explain system behavior in modern AI chip designs. Next, Part 2 described the firmware-hardware handshake in a silicon governance system.

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How it works: The teacher first scans their fingerprint to unlock the system. Students then scan their fingerprints. The system identifies the student using the fingerprint sensor. It records the student's attendance along with the exact date and time from the RTC module. The student's name and attendance status are displayed on the LCD. An SMS is automatically sent to the parent informing them that the student attended the lecture Attendance data is also sent to another number in a form hat can be stored digitally. Last year I built this , then i visited tech feast with this, people there showing AI language translators, automated water filling and packaging machines, computer vision systems, custom PCBs, and projects that looked like actual products. Meanwhile, my project was basically a small box with a fingerprint sensor and LCD Now I'm motivated to build something much bigger this year, but no good idea is coming in mind Can anyone share there project they might have built in there college times submitted by /u/PenComprehensive4721 [link] [comments]

Intelligent power and sensing technology firm onsemi of Scottsdale, AZ, USA has launched its GaNEXUS gallium nitride (GaN) power portfolio...

The ubiquity of the 4 to 20mA current loop in analog process monitoring and control creates possibilities for peculiar designs of circuits for unusual accessory functions.  Figure 1 shows an example.  It does precision conversion of 4—20mA to 0—20mA.  That’s useful for accommodating analog inputs that wouldn’t like a 4mA zero offset.

Wow the engineering world with your unique design: Design Ideas Submission Guide

Figure 1 This current conversion circuit’s function is define by the following equation: Iout = (IinR1 – 1.24v)/R2 = 1.25(Iin – 4mA).

The core of the circuit is the Vin = IR1 = 1.24v to 6.20v developed by the 4mA – 20mA input working into R1 and sensed by the Vref input of Z1. The principle in play is discussed here.

A potentially annoying shortcoming of the Figure 1 design, however, is its current sink output that’s referred not to ground but to the V+ source node, which needs to be at least 8v.  Figure 2 offers an accurate and straightforward fix: an active current mirror as described here. The input max overhead voltage is 8v.

Figure 2 This circuit adds an active current mirror to its predecessor to drive a grounded load.

Stephen Woodward‘s relationship with EDN’s DI column goes back quite a long way. Over 200 submissions have been accepted since his first contribution back in 1974.  They have included best Design Idea of the year in 1974 and 2001.

Related Content

• Full circle current loops: 4mA-20mA to 0mA-20mA
• Active two-way current mirror
• 4/20mA to 0/20mA loop current converter for grounded loads
• Simple but accurate 4 to 20 mA two-wire transmitter for PRTDs
• Positive analog feedback linearizes 4 to 20 mA PRTD transmitter

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Задля здолання бар'єрів на шляху якісного теплопостачання Інформація КП ср, 06/10/2026 - 13:21

Guerrilla RF Inc (GRF) of Greensboro, NC, USA — which provides radio-frequency integrated circuits (RFICs) and monolithic microwave integrated circuits (MMICs) for wireless applications — has announced an expanded focus on the fast-growing tactical radio market. Backed by a broad portfolio that ranges from low-noise small-signal devices to high-power RF amplifiers, Guerrilla RF now offers more than 60 high-performance RFIC solutions designed to strengthen communications links by enabling highly sensitive receivers and efficient, high-power transmit paths that protect link margin and maintain mission-critical connectivity...

Discrete device designer and manufacturer Nexperia B.V. of Nijmegen, the Netherlands (which operates wafer fabs in Hamburg, Germany, and Hazel Grove Manchester, UK) has released 1200V silicon carbide (SiC) MOSFETs in QDPAK packaging, extending its growing wide-bandgap (WBG) portfolio with a top-side-cooled surface-mount package optimized for high-power-density and thermally demanding applications...

ROHM has developed the TSC3PAK (14.00mm x 18.58mm x 3.50mm) package for silicon carbide (SiC) MOSFETs. Mass production began in June...

SemiQ Inc of Lake Forest, CA, USA — which designs, develops and manufactures silicon carbide (SiC) power semiconductors and 150mm SiC epitaxial wafers for high-voltage applications — has expanded its QSiC Dual3 family of half-bridge MOSFET modules, adding high-thermal-performance options with AlN (aluminium nitride) substrates and pre-applied TIM (thermal interface material), as well as new 1700V devices...

Wolfspeed Inc of Durham, NC, USA — which makes silicon carbide (SiC) materials and power semiconductor devices — has introduced its fifth-technology generation, demonstrating a substantial performance leap in efficiency for next-generation 1200V and 750V automotive and industrial applications...

In 2025, Innodisk launched the “AI beyond the edge” initiative at a forum that also hosted Intel, Nvidia, and Qualcomm, which shared details of their latest developments in edge AI. But what does “AI beyond the edge” really mean?

Don Yu, special assistant to the GM at Innodisk, said that “AI beyond the edge” is about enabling systems that operate autonomously, remain connected, and scale across real-world environments. He also mentioned two complementary domains as part of this initiative.

First, industry AI—built for smart manufacturing, automation, transportation, healthcare, retail, and smart cities—enhances on-site responsiveness through real-time recognition, predictive maintenance, and intelligent workflow optimization.

Second, enterprise AI—designed for data centers, on-premise AI, and advanced models such as large language models (LLMs) and visual language models (VLMs)—supports secure, intelligent decision-making across corporate, financial, medical, and public sectors. “That allows small and mid-size businesses (SMBs) to have their own AI engines locally instead of relying on the cloud,” Yu said.

But despite all the promise, deployment of edge AI has been a challenge so far. So, how are these edge AI initiatives faring so far, EDN asked Yu. And what is Innodisk doing to overcome these challenges in effectively implementing edge AI at scale?

Edge AI deployment challenges

Innodisk chairman Randy Chien acknowledges that the exponential rise of generative AI and LLMs has fundamentally changed the design equation at the edge. More specifically, as AI workloads grow in complexity, companies are facing increasing pressure in system integration, hardware-software coordination, and the ability to scale solutions across diverse deployment environments.

“Anticipating this shift early on, Innodisk has built on its strong hardware foundation by structuring its product portfolio into modular building blocks across memory, storage, camera modules, and a wide range of embedded peripherals,” Yu said. “On this foundation, the company has positioned itself as an AI architect, combining these building blocks to meet diverse industry requirements with tailored edge AI systems.”

So, edge AI developers can implement these solutions as individual modules or as fully integrated systems, depending on their application needs. Take the example of the APEX series of edge AI systems, which brings together key building blocks, including AI accelerators, DRAM modules, flash storage, industrial MIPI and GMSL camera modules, and embedded peripherals for networking and industrial I/O.

“The platform enables flexible system configuration based on specific use cases, while supporting customization to meet diverse deployment requirements,” Yu said.

Figure 1 Individual modules are fully integrated systems tailored according to edge AI application needs. Source: Innodisk

Yu added that Innodisk is heavily investing in firmware and software development to bolster its design ecosystem. Take vision-related AI, for instance, where Innodisk provides fully ported drivers for industrial camera modules, supporting both VLMs and computer-vision applications to streamline deployment and minimize integration friction.

Innodisk also provides specialized software toolkits to accelerate system integration. For example, it has introduced IQ Studio to support the development of Qualcomm-powered edge AI systems. IQ Studio is an open-source developer portal that provides essential board support packages (BSPs), reference code, and benchmarking tools.

How modular solutions aid system integrators

These modular solutions—segmented across five layers of compute, memory, storage, sensing and connectivity, and software—are aimed at addressing design challenges before the last mile of AI deployment in vertical markets. This cohesive system-level approach addresses common development challenges for system integrators and solution providers, enabling them to focus on developing their applications rather than managing integration.

Figure 2 Modular solutions handle integration complexity, which allows system integrators to focus on developing their applications. Source: Innodisk

Moreover, there is a wide range of pre-validated solutions that significantly shorten system integration development cycles. Case in point: AI on Arm series of computer-on-modules (COMs) are designed to be deployment-ready. “They can be directly integrated into customer systems with minimal development effort,” Yu said. “Additionally, they can be paired with Innodisk carrier boards and peripherals to support different system configurations.”

Figure 3 COM modules can be paired with carrier boards and peripherals to support different system configurations. Source: Innodisk

These deployment-ready solutions provide system integrators with practical reference points and inspiration for application design when applied in real-world scenarios. Take the APEX-X200 edge AI platform, for instance, which Innodisk showcased at Nvidia GTC 2026. This on-device inference platform analyzes X-ray and CT images in real time, generating draft medical reports and clinical insights through AI-assisted healthcare workflows.

APEX-X200, powered by an Intel Core Ultra 9 processor, also integrates an Nvidia RTX PRO 6000 Blackwell Server Edition GPU with 24,064 CUDA cores and 752 Tensor cores. Furthermore, it supports up to 96 GB of industrial-grade DDR5 memory and a 1 TB PCIe Gen5 x4 NVMe SSD.

Innodisk has also developed perception systems for heavy machinery and large vehicles in collaboration with its subsidiary Aetina. It integrates the Nvidia Jetson AGX Orin platform with up to eight GMSL2 camera modules alongside capture cards and extenders that support cable lengths up to 30 meters.

Figure 4 The edge AI-based perception system facilitates surround-view stitching, blind-spot detection, and driver-monitoring functions. Source: Innodisk

These perception systems enable surround-view stitching, blind-spot detection, and driver-monitoring functions, supporting real-time environmental awareness and helping identify potential risks such as fatigue or distraction under complex operating conditions. “It’s also an example of a modular architecture that supports future system upgrades without requiring major redesign efforts,” Yu said.

Eyeing U.S. and Europe

Innodisk, headquartered in New Taipei City, Taiwan, has global ambitions with more than 1,000 field-proven edge AI deployments worldwide. In Europe and the Unites States, it’s operating in close collaboration with regional distributors and partners in edge AI segments such as industrial automation, healthcare, aviation, and professional workstations.

Innodisk considers industry events a key tool for bolstering its presence in these crucial markets. It has showcased its edge AI solutions at Nvidia GTC 2026 in the United States, ICE Barcelona in Spain, and Embedded World 2026 and CloudFest 2026 in Germany.

Next, to support global deployment requirements, the company ensures its products comply with regional regulations. Its edge AI solutions meet CE and UKCA requirements for Europe and the U.K. and FCC regulations for the United States.

Also, in Europe, where cybersecurity requirements have become increasingly mandatory, Innodisk attained IEC 62443-4-1 certification in late 2025, embedding security throughout the product development lifecycle rather than treating it as a separate feature. It’s critical because the EU Cyber Resilience Act (CRA) is expected to be fully enforced by 2027.

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Im so happy that it even works! Took me about an hour. submitted by /u/Such_Network1389 [link] [comments]