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Surface resistance and resistivity testers are essential tools for evaluating materials used in electrostatic discharge (ESD) control. By quantifying how surfaces resist or conduct electrical charge, they enable engineers to verify compliance with industry standards and safeguard sensitive electronic components.

Because these measurements define whether a material behaves as conductive, dissipative, or insulative, they are central to effective ESD control and protection of high-value electronics.

Surface resistivity vs. surface resistance

It’s easy to confuse surface resistivity testers with surface resistance testers, but in principle they measure different properties. Surface resistivity testers determine a material’s inherent ability to resist charge flow, expressed in ohms per square (Ω/□), and are typically used for material characterization in laboratories.

Surface resistance testers, by contrast, measure the actual resistance between two points or between a surface and ground, expressed in ohms (Ω), making them more common in field audits of ESD workstations, mats, and floors. Recognizing this distinction ensures accurate measurements, proper classification of materials, and effective ESD program control.

In practice, the terms surface resistance and surface resistivity are often used interchangeably in device descriptions because both relate to how materials impede electrical charge across their surfaces. The overlap in measurement setups, industry shorthand, and the focus on ESD compliance ranges (10³–10¹² Ω) all contribute to this blurred usage. What matters most to engineers is whether a material or surface falls within conductive, dissipative, or insulative ranges, not the precise terminology.

This is where surface resistance test kits become especially significant: they provide portable, standardized tools for field audits of ESD workstations, mats, floors, and packaging, ensuring that surfaces meet compliance requirements and offer safe discharge paths for static electricity. By bridging laboratory concepts with real-world checks, these kits make ESD control practical and reliable.

Figure 1 This portable tester—Z203-100—measures surface resistivity and resistance in ESD applications. Source: Zeebeetronics

Sidenote: In ESD protection, surface resistivity (Ω/□) reflects a material’s intrinsic “DNA”—its inherent electrical properties independent of size. Surface resistance (Ω), by contrast, captures “real‑world” performance, shaped by geometry, installation, and grounding. Simply put, resistivity identifies the material; resistance verifies the protection.

The role of probe geometry

Getting again into the distinction between surface resistance and surface resistivity, the technical divergence often comes down to the test probe geometry used during the audit.

In a practical setting, a surface resistance tester is the essential “boots on the ground” tool for verifying if an ESD mat is functional. Unlike lab-based resistivity tests, it measures the actual path a charge takes from point A to point B (or to ground), accounting for real-world variables like surface wear, contamination, and grounding connections. While compact handheld meters are convenient for quick checks, official ANSI/ESD S20.20 audits require the superior accuracy of heavy, “5-pound weight” megohmmeter probes to ensure the environment is truly safe for sensitive electronics.

While a field technician might use two 5-pound weighted electrodes (pucks) to measure the point-to-point resistance of a specific floor or mat, a materials scientist might opt for a concentric ring probe to determine the material’s inherent resistivity.

Because the concentric ring’s circular design ensures the distance between electrodes is mathematically proportional to their size, the units of measurement effectively cancel out, leaving a value in ohms per square. This allows the meter to provide a reading that remains constant regardless of the material’s total surface area, whereas the 5-pound pucks provide a “real-world” measurement of how much resistance a charge actually encounters between two specific points.

Figure 2 Concentric ring probe measuring surface resistance; the geometric constant converts the value to surface resistivity. Source: Desco Europe

A practical pointer: when converting resistance measurements from the concentric ring probe method to equivalent resistivity, multiply the result by the conversion factor specified in the probe’s datasheet. This factor is derived from the specific geometry of the electrode assembly. Note, however, that these conversions may be invalid for non-homogeneous materials, such as those that are laminated, plated, or metallized with conductive layers.

So, while standard 5-pound weighted electrodes are used to measure point-to-point resistance, the concentric ring probe is the gold standard for measuring surface resistivity because its unique geometry—a center electrode surrounded by a circular outer ring—neutralizes surface area variables and orientation. By applying uniform pressure across a fixed distance, this probe allows a resistance tester to calculate true ohms per square (Ω/□), providing a precise material characterization that standard cylinders cannot.

Ultimately, in a professional audit, the 5-pound cylinders verify that the installed mat effectively dissipates charge to ground, while the concentric ring probe confirms that the material itself meets the manufacturer’s specific electrical requirements.

Applied test voltage and electrification period

The applied voltage functions as the electrical pressure that drives current across a material’s surface. On highly conductive surfaces, a 10-V output combined with a brief electrification period (typically around 15 seconds) is sufficient to establish a stable reading without overstressing the sample. As materials shift into dissipative or insulative ranges—where molecular structure resists electron flow—10 V lacks the drive needed to overcome surface impedance.

In these cases, the meter automatically steps up to 100 V, maintaining the same electrification period to ensure the signal penetrates the higher resistance and produces a reliable data point. Without this higher voltage, the instrument could misclassify a dissipative surface as a complete insulator (open circuit). The dual-voltage design, coupled with controlled electrification time, ensures that measurements reflect the material’s true protective properties rather than a limitation of the tester itself.

Note at this point that compliance standards require a 15-second electrification period to ensure stabilized readings. In contrast, many portable field meters are optimized for convenience, displaying results in as little as 2–5 seconds. While suitable for quick checks, these faster readings do not substitute for compliance-grade measurements.

Resistance ranges and material classification

Surface resistance values are categorized into three broad ranges that dictate a material’s electrostatic behavior. Conductive materials (10^3–10^6 Ω) allow charges to move freely, facilitating rapid equalization across the surface. Dissipative materials (10^6–10^11 Ω) provide a controlled pathway that regulates charge decay, preventing the danger of sudden discharge.

Conversely, insulative materials (>10^12 Ω) inhibit electron flow, causing charges to remain trapped on the surface. This framework ensures that test results serve as functional indicators of material performance in sensitive environments.

Maintenance, calibration, and environmental factors

To maintain precise measurements, the electrodes or weighted probes of a surface resistance or resistivity meter must be kept free of contaminants like oils, dust, or skin residue. Cleaning should be performed using a lint-free cloth moistened with 99% isopropyl alcohol, followed by sufficient time to allow the probes to dry completely to prevent solvent-induced measurement errors.

Beyond routine cleaning, periodic calibration—typically on an annual basis—is necessary to verify that the internal circuitry remains within the manufacturer’s specified tolerance using a high-megohm resistance box.

Furthermore, because relative humidity (RH) significantly influences surface resistance by creating a microscopic conductive layer on many materials that can artificially lower readings, it’s critical to always record the ambient RH alongside every measurement for proper context.

Scratching surface, revealing science

That is all for now. Obviously, we just scratched the resistive surface—and much remains hidden in the interplay of surfaces and charge.

In electronics and materials science, surface resistance and resistivity testers are indispensable for gauging reliability, safety, and performance. They help practitioners clearly distinguish between insulating, conductive, and static-dissipative surfaces.

For keen experimenters, building prototypes of such testers does not demand exotic or costly components. With curiosity and patience, the analog and digital design ideas are well within reach. When time permits, I intend to explore these concepts further—and perhaps craft a design of my own.

Now it’s your turn: share your design ideas, prototypes, and experiments—let us advance practical measurements together. Scratch the surface, reveal the science!

T. K. Hareendran is a self-taught electronics enthusiast with a strong passion for innovative circuit design and hands-on technology. He develops both experimental and practical electronic projects, documenting and sharing his work to support fellow tinkerers and learners. Beyond the workbench, he dedicates time to technical writing and hardware evaluations to contribute meaningfully to the maker community.

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• High-speed automotive electronics needs high-performance ESD protection

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I made up a schematic of the division unit for my recent calculator project, with some adjustments. I switched out a few chips with ones from the same family, but I tried to keep it as close to the original as I could. The original also only took 7 bits for the divisor as it only took up to 99 as an input due to the interface of the calculator. Definitely could be optimized. This is my first time translating a circuit of this size to a schematic, so it might be... messy. Hopefully I didn't miss anything; I checked it over a few times. A few adjustments might be required. "Start" must remain low until dividend and divisor are inputted. This signal must remain high until the XOR signal, from carryout and OR, is high, which then tells the circuit that the result is negative and to stop subtracting the divisor. I have a video of the division unit from when i was still testing it as well. I plan and am working on creating a whole schematic of my calculator without any changes, but do beware that my demonstration of the unit isn't 1:1 as it's from early on in testing, same with the second photo. https://youtu.be/GKElo5Bfb7c submitted by /u/duckquackquack__ [link] [comments]

First time trying something like this! submitted by /u/darthB4s [link] [comments]

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I'm a high school student who has an interest in point clouds and spatial data, so I made my own LiDAR scanner! This was my first time making a PCB, and the scanner runs on an esp32 & TMC2209 stepper drivers. You can see my Github with the KiCAD project files here. submitted by /u/thatonebckid [link] [comments]

Конкурс "Інтелект молоді. Раціональне природокористування та новітні енергоефективні технології" KPI4U-1 сб, 06/13/2026 - 00:09

У КПІ відкрили меморіальну дошку Герою України Андрію Гуцалу kpi пт, 06/12/2026 - 23:29

As one of like 3 people who absolutely loves cat whiskers when I stumbled upon a paper from the 1920s known as “the Crystodyne principle” I got real excited, then I realized I don’t own zincite and ya I know the paper itself says you can use galena and fools gold but I’ve over used fools gold and if I’m gonna buy galena why not spend that money on zincite, but then I had a genius idea “what if I made the crystal!” So then I got to work (spent like 5minutes finding out how zincite forms) and discovered it’s just the mineral equivalent to zinc oxide so I heat treated some zinc WITH A MASK NO ONE WANTS ZINC PLATED LUNGS, and to my surprise it worked 2nd try. The hardest part had to be actually making the circuit because “the Crystodyne principle” doesn’t tell you how to make an amplifier only that you can so like any responsible science fella I just started shoving crap together based on half complete knowledge till it worked and then when I got it to work I needed to figure out how to A. Remove unnecessary components B. Increase volume C. Decrease static. And this is the circuit I came up with. To test it I put the earpiece in my ear under a pair of headphones and tapped the mic against an auto transformer. I also managed to use it to amplify an electric kazoo. submitted by /u/antthatisverycool [link] [comments]

Upside-down mounting can deliver inductance upsides for surface mount passives and other components.

Please visualize the structure of a surface mount resistor as shown in the following Figure 1:

Figure 1 Surface mount resistor constituents include this writeup’s showcase electrical contacts.

Normally this part would be installed on a circuit board with the outer coating visible for inspection and with the substrate adjacent to the circuit board’s surface. However, if the circuit board’s goodies are operating at microwave frequencies, this might not be the best idea.

There is an alternative, however, as shown in Figure 2:

Figure 2 A surface mount resistor in its normal-service mounting orientation (a) may be re-positioned for optimal microwave-service operation (b).

If the surface mount resistor is installed on the circuit board “upside down”, the inductances presented by the electrical contacts will be much reduced versus that of the usual mounting. At microwave frequencies this can be significant, especially if the resistance is 50Ω in a matched impedance application.

John Dunn is an electronics consultant and a graduate of The Polytechnic Institute of Brooklyn (BSEE) and of New York University (MSEE).

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The post Surface mount and microwaves appeared first on EDN.

🧐 Конкурс учнівських проєктів “Автоматизація навколо нас” kpi пт, 06/12/2026 - 12:45

Photonic simulation CAD software developer Photon Design Ltd of Oxford, UK has added a silicon modulator design capability to its HAROLD semiconductor and laser simulation tool, across a range of geometries...

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This series of articles is written for system bring-up engineers, post-silicon validation engineers, platform firmware developers, kernel and driver integrators, and test architects who are—or will soon be—working with Compute Express Link (CXL) Type 3 memory expanders in real hardware. If your job involves taking a server from first power-on to production-ready memory expansion, reconciling what firmware advertises with what the operating system actually consumes, or explaining why a workload is “slow on CXL” when link training looks clean, this material is aimed at you.

This mini-series assumes you already understand PCIe fundamentals and have a working mental model of CXL device types and topologies. It does not re-teach CXL from first principles; instead, it focuses on the practical cross-layer problems that dominate bring-up and validation; discovery versus usability, non-uniform memory access (NUMA) placement versus link health, and policy configuration versus silicon defects.

How will this mini-series help

CXL Type 3 memory is deceptively familiar. From software’s perspective, it looks like RAM; from a validation perspective, it behaves like a small distributed system spanning expander ASIC firmware, host BIOS, ACPI tables, kernel drivers, and user-space tooling. Failures at one layer often masquerade as symptoms at another—a missing NUMA node that is really an HDM validity problem, or a “slow” benchmark that is really default allocator placement on far memory.

This mini-series gives you a structured playbook to:

• Set performance and correctness expectations using the latency–capacity pyramid and NUMA topology, so you know when a workload should tolerate CXL-attached memory and when it will not.
• Verify platform prerequisites across CPU, BIOS, kernel, and device firmware before spending days on the wrong debug path.
• Use the standard Linux tooling chain—cxl, ndctl, daxctl, numactl, lspci—to distinguish “device not seen,” “device seen but not consumable,” and “device online but misconfigured”.
• Walk the boot timeline from slot power and DRAM training through DVSEC discovery, decode programming, CDAT delivery, and driver bind, with a validation mindset at each gate.
• Interpret transport-layer and CXL-specific configuration-space indicators, run targeted memory traffic, and separate link issues from NUMA policy and memory-mode configuration faults.

The goal is to reduce time spent debugging the wrong layer and to give you checklists and command-level examples you can adapt into lab gates, CI smoke tests, and field triage runbooks.

What each part covers

Part 1: Why CXL Type 3 memory matters, and what your platform must provide

Part 1 establishes the system context. It explains why AI and data-intensive workloads are driving interest in memory expanders, how CXL Type 3 devices differ from local DIMMs even when they appear as ordinary RAM, and where expander memory sits in the latency–capacity pyramid relative to socket-local DRAM and storage.

It then walks through platform prerequisites—CPU enablement, BIOS/firmware, kernel support, device firmware, and RAS—and explains why features such as CXL IDE or tiered memory only work when every layer is aligned. The part closes with the NUMA story on Linux: how cxl_pci binds Type 3 endpoints, why expander memory often appears as a separate or “far” NUMA node, and why many CXL issues show up as placement and bandwidth imbalance rather than hard functional failures.

Part 2: Tooling and boot path from power-on to usable memory

Part 2 is the operational core. It introduces the user-space utilities that make CXL state visible beyond dmesg—cxl/libcxl for fabric topology, ndctl and daxctl for region and DAX/system-RAM modes, numactl for placement experiments, and lspci/hwloc for bus- and topology-level sanity checks.

It then traces the end-to-end boot sequence: power and clocks, on-device DRAM training and SPD discovery, gating of host-managed device memory (HDM) until mem_info_valid is asserted, PCIe/CXL link up and DVSEC-based discovery, decode programming and mem_enable, CDAT transport over DOE and mailbox health, ACPI handoff via CEDT/SRAT/HMAT, and final OS driver binding. Each stage is framed as an implied test with characteristic failure signatures, so you can map symptoms to the most likely layer quickly.

Part 3: Test, debug, and validation of CXL memory expanders

Part 3 turns theory into hands-on practice. It covers integration modes—system RAM versus device DAX—and when boot parameters such as efi=nosoftreserve or daxctl reconfigure-device apply.

It shows how to confirm expander memory as a distinct NUMA node with numactl, decode key lspci fields (link width/speed, CXL DVSEC capabilities, HDM range Valid/Active bits, cxl_pci binding), and drive traffic with numactl placement plus tools such as Intel MLC, stressapptest, and memtester. The series concludes with a cross-layer validation mindset, suggested future work for multi-device and pooled topologies, and references for deeper reading.

Read all three parts if you are new to CXL Type 3 bring-up; jump to Part 2 or Part 3 if you already have a booting system and need tooling or debug guidance.

Ameet Sanghavi works in post-silicon validation for PCIe and CXL at Nvidia with a focus on interface bring-up and validation on shipping products. He has worked on PCIe since 2005 (from PCIe 1.1 onward) and on CXL since 2020 (from CXL 1.1 onward).

Related Content

• Stripped Down CXL Scales Memory Wall
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• From GPUs to Memory Pools: Why AI Needs Compute Express Link (CXL)

The post Bring-up and testing of systems with CXL Type 3 memory expanders appeared first on EDN.

Je travail sur un projet d'arrosage de plante autonome souhaite moi bonne chance 😂😉 submitted by /u/InternationalCod3981 [link] [comments]

All thanks to one single person who believed in me & pushed me to do it! submitted by /u/FoundationOk3176 [link] [comments]

Mining exploration company Nimy Resources Ltd of Perth, Western Australia and Perth-based Curtin University are to undertake what is described as a pioneering research program into processing gallium...

Epitaxial deposition and process equipment maker Veeco Instruments Inc of Plainview, NY, USA has announced the first commercial acceptance and qualification of its LUMINA+ metal-organic chemical vapor deposition (MOCVD) system by Ennostar Corp of Hsinchu, Taiwan (a provider of integrated optoelectronic solutions, specializing in R&D and manufacturing III-V materials). The order is said to set a new benchmark for high-volume arsenide and phosphide (As/P) production...

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