Збирач потоків

Договір про співпрацю із Полтавським державним аграрним університетом kpi чт, 07/16/2026 - 18:45

🔗 Проєкт положення про систему забезпечення академічної доброчесності в Національному технічному університеті України «Київський політехнічний інститут імені Ігоря Сікорського» kpi чт, 07/16/2026 - 17:49

Following a non-binding preliminary memorandum of terms (PMT) signed in December 2024, Germany-based tier-1 automotive supplier Bosch has announced a definitive agreement with the Trump Administration for up to $225m in direct funding from the US Department of Commerce’s CHIPS Program Office to support the up to $2bn that Bosch is investing to transform its fabrication plant in Roseville, California — acquired as silicon-based application-specific integrated circuit (ASIC) foundry TSI Semiconductors in August 2023 — for the production and testing of silicon carbide (SiC) semiconductors. The Roseville facility has nearly 40 years of experience in the production of semiconductors for automotive and industrial applications, which it will now apply to the production of SiC chips...

USB-C will be 22 years old next month, from a published-specification standpoint. Yet it’s still rife with implementation imperfections. Why? Start with the words “published specification”.

One of the many upsides to my now-dual roles as both contributing and associate editor at EDN is deeper-than-prior insight into what topics, and what content pieces focused on those topics, perform particularly well from various website metrics standpoints. This includes my own stuff, of course; I’m not going to share how it does, either in an absolute sense or relative to my colleagues’ contributions, and I’ll also leave you to decide for yourselves whether that silence is driven by humility, embarrassment, or some combination of the two

I begin with this background information by means of introducing one particular piece of EDN content whose enduring stellar performance I will share with you. Week after week, I’m amazed to repeatedly see the article USB Pinout, Wiring and How It Works perpetually parked at the upper stratum of the site traffic spectrum. What’s particularly mind-blowing to me is that the article’s original publication date was January 26, 2010. Clearly, USB is a topic of enduring interest to you, our treasured readership, for oft-obvious reasons!

The latest generation

The date of this article’s initial appearance in EDN is intriguing for another reason; it arrived 4.5 years ahead of the publication of the version 1.0 specification for USB Type‑C, aka USB-C, and therefore doesn’t include mention of this latest generation of the standard. USB-C usage has subsequently become pervasive, courtesy of factors such as its two-fold rotational (and broader two-end) connector symmetry, in combination with higher data bandwidth (extended beyond USB 3.0, introduced in prior USB connector form factors) and higher power (Power Delivery, i.e., USB-PD, building on a proprietary Qualcomm Quick Charge foundation) transfer capabilities.

Yours truly, for example, has crafted three USB-C-focused pieces in recent years (along with innumerable other more minor mentions), the first one focused on the technology, including its generational development history, and the latter two sharing my personal (underwhelming, to be precise) experiences with it:

• USB: Deciphering the signaling, connector, and power delivery differences
• USB Power Delivery: incompatibility-derived foibles and failures
• USB 3: How did it end up being so messy?

And speaking of popular writeups, my cohort Bill Schweber followed up my USB-PD piece with his own technology treatise:

• USB-C and Power Delivery: Too much of a good thing?

We’re now more than two decades beyond that initial publication date for USB Type‑C Specification 1.0, and I’d love to be able to say that all (or even most) initial implementation warts have been effectively mitigated at this point. I’d love to be able to say that…but I’d be lying if I did. All three of my earlier noted USB-C advancements—connector symmetry, data bandwidth, and power carriage—will unfortunately be demonstrated as enduringly imperfect in the following paragraphs, in fact. Without further ado…

Identity indecision

Let’s start with the fundamentals. Does a particular USB-C cable carry only power? Or power plus data? How much power? And at what peak data transfer rate, if any? Sadly, the answer to these few elementary questions is often consistently unsatisfying, along the lines of “Duh…I dunno. Plug it in, test it and find out for yourself. Then stick an info label on it so you don’t forget.”

Take, for example, this cable:

which came bundled with an inexpensive computer docking station I recently acquired, specifically to test out (and then tear down) its touted DisplayLink capabilities:

By means of association with the specs of its docking station companion, I can make the following cable feature set assumptions:

• Power-plus-data support
• 100W peak power carriage
• 5 Mbps peak data transfer rate

So, if I only use it with the docking station going forward, I’ll inherently likely know what it can (and can’t) do. But what if the dock dies or the cable more broadly get separated and tossed in a drawer with others? It’s unmarked in its entirety, thereby providing no visual notification of its capabilities (and limitations). This unfortunately quite common anonymity rationalizes the recent unveil of the open-source, albeit MacOS-only (and Apple Silicon-only) from a compiled-code standpoint, WhatCable utility, for example:

And even if I was able to retain the original packaging and documentation associated with the cable, those info supplements might still not suffice. Take this cable, which I’d purchased as part of a six-pack from Woot in March 2022 for $17.97, as illustration of the concept:

The cable itself is again a blank slate, specification-wise. And although in this case the connectors are embossed, they’re still meaningfully information-deficient:

What about the box? It’s of little-to-no assistance, either. The front panel claims that it’s “USB 2.0”, which infers (at least to folks with sufficient technical “chops” to decode the terminology, a scant sliver of the overall consumer community, and still not definitively) that it also supports power-plus-data, albeit the latter only rudimentarily, with a 480 Mbps transfer rate.

And what about power carriage? For that we need to turn to the back panel of the box:

Note the “5V⎓3A” terminology at the top, which translates to a 15W peak power spec. That multiplicative exercise outcome stands in stark contrast to the product page, which states that the cable is 60W-capable (therefore explaining the four-plus-year old scribble from yours truly that you’ll see in the picture). I’ve never encountered a 15W USB-C to USB-C cable, in fact, only 60W ones (along with higher-power variants such as 100W, 140W and 240W), although plenty of 15W USB-A (the current-limiting connector) to USB-C cables alternatively exist.

When I reported the discrepancy to Woot after receiving the initial six-cable (three-box) shipment, customer support told me to keep ‘em and sent me free replacements, whose packaging was labeled in exactly the same (incorrect) way. Eventually, I got a full refund and ended up with 12 gratis, albeit power carriage-dubious, cables for my trouble. In revisiting the product page just now while writing this section, I noticed that Woot eventually appended a correction (albeit, the engineer in me is compelled to point out, using the “=” symbol instead of the correct “⎓”…current and voltage being completely different things, don’cha know):

Please note the Amazon Basics box might state “5V=3A”. This is just a standard industry specification for USB-C cables. HOWEVER, these cables do support charging up to 60W (20V=3A) if paired with a charging brick capable of supporting 60W charging and a device capable of receiving 60W charging.

Beware the upside down

This last case study for today also originated in a several-year-old personal experience. As USB-C approached critical marketplace mass, peripheral equipment (mass storage devices, headsets and other audio equipment, etc.) increasingly shipped by default with integrated USB-C connectors versus USB-A with predecessor gear variants. Sometimes, the manufacturer also bundled a USB-C to USB-A adapter for connection to legacy computers and the like, albeit with tradeoffs such as:

• 5 Mbps (USB 3.0) peak transfer speeds, and
• Negation of USB-PD support that might be minimally beneficial, if not functionally flat-out necessary, since only USB-C includes the necessary communication channel (CC) signals for initial protocol handshaking. Strictly speaking, per the USB-PD specification, modulation on the USB-A-supported Vbus and Vgnd signals could also be used for this purpose, but real-life adoption of this alternative technique is scant-to-nonexistent.

Other times, however, to save a few bill-of-materials cents (not to mention avoiding additional expensive technical support sessions), the peripheral manufacturer would dispense with the backwards-compatible adapter, requiring the customer to as-needed alternatively purchase it standalone. So it was that I picked up a set of two inexpensive ($8.09 total) XAOSUN USB-C female to USB-A male adapters from Amazon, since at the time (and, to a lesser degree, even today), the majority of the computers in my stable met the “legacy” (USB-C-less) criteria:

Good news: they support up-to-10 Mbps peak transfer rates, versus the nominal 5 Mbps speed spec’d for others’ adapters. Bad news: this happens only when the peripheral connector is inserted in one of USB-C’s two possible orientations. In the other (also unmarked) orientation, the adapter will pass through data at only USB 2-compatible 480 Mbps peak speeds:

Please note that this USB-C to USB Adapter only supports single-sided 10Gbps high-speed transmission. The Type-C female port allows you to switch between USB 3.1 speed and USB 2.0 speed with a simple flip of the Type C plug. Now you can enjoy unparalleled transmission quality from your devices!

The manufacturer classifies this explanation under an “Easy to Use” category on the Amazon product page listing. I profoundly disagree. Again, as a “techie” I have awareness from past experience of how 10 Mbps (or even 5 Mbps, for that matter) speeds should be perceived by a user, so if things are proceeding slower than expected, I’ll instinctively realize that I need to:

• Cancel the current in-process operation
• Disconnect the peripheral
• Flip the connector by 180° and re-insert, and
• Restart the operation

Conversely, even fundamentally knowing that there’s a problem, far from remembering what’s causing it and how to recover from it, is well beyond the capabilities of the average consumer.

And stepping back, why is this even happening? The answer’s in the “single-sided 10 Gbps” phrasing. As discussed at length in Reddit threads (for example) such as the following:

• What does “single-sided” 10Gbps mean in this adapter?
• Any reliable USB-C (female) to USB-A (male) adapters yet?

this limitation is fundamentally driven by cost-reduction moves made by the manufacturer, specifically in passively routing only one set of SuperSpeed differential source pins to the USB-A destination. Routing both sets of source pins, thereby enabling SuperSpeed operation in both possible USB-C orientations, necessitates active circuitry such as Via Labs’ VL160 or a successor or competitor.

Certification vs compliance

Why do situations like the ones described in this writeup, along with those in prior USB-C coverage from me (reminder: listed at the beginning of this piece, as well as the end), occur at all? Isn’t this something that the USB-IF (Implementers Forum) should be dealing with? The answer to this question lies in the differentiation between “compliance” and “certification”. Although USB-IF encourages compliance (via member workshops, testing by independent labs and other means) to “provide reasonable measures of acceptability”, the organization’s specifications are freely published and available for download and implementation by everyone.

Strictly speaking, manufacturers (and products from those companies) are allowed to license and use the USB-IF logo set only if they’ve successfully passed compliance testing. But by now we’ve all likely come across companies that stick the FCC logo on devices and their packaging even though it’s highly unlikely that those products have even applied for FCC certification, far from achieving it (with an omitted FCC certification ID one obvious tip-off). USB logos are presumably also being used in a similarly cavalier manner.

Retailers can also put pressure to bear on suppliers; some require proof of USB-IF compliance determination before they’re willing to stock a particular product (not to mention a broader manufacturer full product suite), for example. And an excessive return rate can also be effective in compelling a retailer to drop a product, not to mention the company that developed it. Still, at the end of the day this fundamentally remains a caveat emptor situation for consumers.

I’ve got one more notable USB-C-related implementation-challenge situation to discuss, but after just passing through 2,000 words, I’m going to save it for next week’s part-two post. Until then, I welcome your thoughts in the comments on anything I’ve so far discussed!

—Brian Dipert is the associate editor, as well as a contributing editor, at EDN.

Related Content

• USB Pinout, Wiring and How It Works
• USB: Deciphering the signaling, connector, and power delivery differences
• USB Power Delivery: incompatibility-derived foibles and failures
• USB 3: How did it end up being so messy?
• USB-C and Power Delivery: Too much of a good thing?

The post USB-C’s lingering incompatibilities and other complexities, part 1: Direct-connect complications appeared first on EDN.

Texas Instruments (TI) India today announced the conclusion of its fifth
edition of the Women in Semiconductors and Hardware (WiSH) program, TI India’s flagship initiative to
inspire, mentor, and accelerate the careers of women engineering students in semiconductors, hardware,
and embedded systems. During the program, participants engage in hands-on experiments, technical
simulations, lab visits and engineering projects that expose them to real-world semiconductor applications
and product development workflows.

Since its inception five years ago, the program has empowered 685 women engineering students through
mentorship by TI engineers and facilitated more than 300 internship opportunities, helping create a
sustained pipeline of female talent into one of the world’s fastest-growing technology sectors. Building on
the momentum of previous editions, the 2026 WiSH program recorded a 33% increase in registrations,
close to 2,600 applications last year, reflecting growing aspiration among women students across India to
pursue semiconductor careers.

“At Texas Instruments, we believe early exposure to industry and mentorship can play an important role
in shaping future engineers. While women account for 43% of STEM graduates in India, one of the
highest rates globally, they continue to be underrepresented in technical roles,” said Arbab Kausar, HR
director, Texas Instruments India. “Over the past five years, the WiSH program has helped women
engineering students gain practical skills in semiconductor and hardware engineering while building their
technical capabilities. The significant increase in registrations this year is encouraging and reflects the
growing interest in semiconductor careers among female engineering students across India.”

While the program’s core architecture remains consistent, the 2026 cohort has been meaningfully
strengthened. Pre-work learning modules and streamlined sessions significantly expanded the time
participants spent on hands-on problem-solving, brainstorming, and collaborative design thinking.
Students continue to engage with TI mentors, former WiSH participants, interns, and early-career
engineers, gaining practical insights into what a career in semiconductor engineering truly looks like.

“The WiSH program gave me an opportunity to learn directly from experienced hardware engineers and
gain valuable insights into the semiconductor industry,” said Ashmita Das, who joined TI India as a
digital intern after participating in the WiSH program. “Returning to TI as a summer intern feels like a
dream come true and marks the beginning of an exciting new chapter in my journey. Deepening my
technical expertise while gaining first-hand experience of working with teams that collaborate, innovate,
and drive impactful engineering solutions has been incredibly rewarding.”

Through WiSH and its broader talent development initiatives, TI India continues to invest in
strengthening the long-term growth of India’s semiconductor ecosystem by nurturing the next generation
of women engineers.

 

The post Texas Instruments India reports 33% rise in women seeking semiconductor career exposure through its WiSH program appeared first on ELE Times.

While accelerating towards manufacturing modern semiconductor technologies,
India has achieved another milestone by reducing the Basic Custom Duty (BCD) to 0%
on 85 categories of electronics components and manufacturing equipment by issuing
three official notifications through the Finance Ministry and the Central Board of
Indirect Taxes and Customs (CBIC). This policy removes the previous 5% to 7.5%
import taxes to make it cheaper to manufacture electronics inside the country. It also
simplifies supply chains by lowering landed costs, which boosts local component
sourcing and accelerates the country’s ambition of becoming a global electronics and
manufacturing hub.

The duty exemption primarily covers components, machinery, and equipment that
are not manufactured in sufficient quantities within India but are essential for the
production of smartphones, laptops, consumer electronics, telecom equipment,
industrial electronics, automotive electronics, and semiconductor-related products.
This elimination of costs on import duties in semiconductor manufacturing lowers
production costs, making electronics cheaper to build, and attracting global
investments by lowering their global supply chain expenses.

Industry experts believe that reduction in import duty will practically benefit
manufacturers by directly lowering production costs. Manufacturing electronic
products that rely on advanced electronic components, precision manufacturing
equipment, semiconductor materials, and testing systems that are currently
unavailable or produced only in limited quantities will be able to source these critical
inputs at lower costs.

Combined with ongoing investments under the India Semiconductor Mission, PLI
schemes, and expanding semiconductor manufacturing projects, the cost-cutting of
import duties is expected to strengthen India’s position as a preferred destination for
electronics production and innovation. As the semiconductor market grows, the
zero-duty policy on electronics input is expected to improve export competitiveness
and the development of a resilient semiconductor ecosystem, supporting India’s
emergence as a key player in the global semiconductor industry.

The post India Cuts Duty to 0% on 85 Electronics Categories, Leading Global Manufacturers to Invest in India appeared first on ELE Times.

The Ministry of Electronics and Information Technology (MeitY) with Drone
Federation of India, has introduced NIDAR 2.0 (2026-27) under the SwaYaan initiative to
build indigenous drones and flight controllers powered by India’s homegrown VEGA
processor. This innovation reduces reliance on foreign chips, strengthen the
domestic drone and electronics manufacturing ecosystem. This initiative aims to
accelerate the development of next-generation unmanned aerial system (UAS) by
encouraging startups, researchers, and industry to build drones using domestically
manufactured electronic components.

NIDAR 2.0 stands for National Innovation Challenge for Drone Application and
Research that aligns with government’s vision of Atmanirbhar Bharat, the India
Semiconductor Mission (ISM), and the Designed Linked Incentive (DLI) Scheme. The
goal of this hackathon is to provide a valuable opportunity for students and working
professionals to build flight controller and autopilot hardware powered by India’s
indigenous VEGA microchip.

According to MeitY release, NIDAR 2.0 offers a prize pool of more than 65 lakh that
not only promote innovation but also supports startups, nurtures young talents, and
accelerate the development of domestic drones and semiconductor technologies
through incubation, technical mentorship, and industry collaboration.

Launching the challenge, MeitY Secretary S Krishnan said, “NIDAR 2.0 takes our
students from just flying drones to building the drone’s brain. When the drone’s
brain runs on India’s own VEGA processor, we are not just training engineers. We are
laying the foundation of a self-reliant drone industry.”

The primary focus of this hackathon is to build autonomous swarm drones capable of
locating survivors and delivering medical supplies in disaster-hit areas without an
external communication network, and developing GPS-denied drones for indoor
industrial inspection. By collaborating as a coordinated fleet, swarm drones can
rapidly survey large areas, identify victims using onboard sensors and AI-based image
processing, and optimizing search-and-rescue operations without relying on constant
human intervention.

The post NIDAR 2.0: MeitY Boosts Indigenous Drone Innovation with India’s homegrown chips appeared first on ELE Times.

Cadence (Nasdaq: CDNS) today introduced the AuraStack AI Super
Agent on Cadence Allegro AI Studio, the world’s first agentic AI platform for printed circuit board
(PCB) and advanced packaging design, taking designers from system planning to final product in a
single AI-native environment. The Cadence AuraStack AI Super Agent, accelerated by NVIDIA
Blackwell and NVIDIA CUDA-X, coordinates domain-specific AI agents across planning,
implementation and tightly integrated multiphysics analysis domains to compress the system-design
cycle through manufacturing. With the AuraStack AI Super Agent, Cadence is now the only provider
with agentic AI solutions spanning the full electronic system design flow, from digital and analog
silicon design, advanced packaging, through to PCB design, building on its ChipStack, InnoStack
and ViraStack AI Super Agents.

“The next era of AI infrastructure—spanning data centers, automotive, aerospace and physical
AI—will be defined not only by silicon, but by the systems that connect, power and cool it,” said
Michael Jackson, corporate vice president of R&D for System Design and Analysis at
Cadence. “As hyperscale data centers deploy massive AI clusters and other industries advance
increasingly intelligent, high-performance systems, engineering teams face growing complexity in
PCB and advanced package design. Agentic AI orchestration, combined with trusted EDA and SDA
tools, enables customers to move from manual iteration to intelligent, automated design realization.”

Agentic AI for Packaging and PCB Design

Building on the same architecture as Cadence’s ChipStack AI Super Agent, agentic AI is combined with principled simulation and optimization tools, leveraging a mental model of the design intent, to automate and orchestrate the design exploration, realization and signoff. The AuraStack AI Super Agent brings together automation and optimization for system planning, constraints management, physical structure definition, IP creation and reuse, place and route, design for manufacturability and multiphysics analysis across Cadence’s system design and analysis portfolio. It introduces a unified, AI-driven multiphysics foundation that concurrently models and optimizes electrical, thermal and mechanical behavior—including SI/PI, thermal, mechanical stress, drop, vibration and fatigue analysis—within a closed-loop environment, enabling earlier tradeoff evaluation and product-level optimization across the entire design flow. This continuous multiphysics feedback loop enables real- time design convergence, reducing late-stage surprises and improving overall system reliability.

The AuraStack AI Super Agent’s key benefits include:

• Accelerating time to market by 2X, with 15X productivity and multiphysics-driven
  quality—automating complex tasks, expanding design exploration.
• Unifying separate engineering teams around a shared, multiphysics-aware design
  environment with a single source of truth across domains.
• Advancing early and continuous multiphysics co-optimization to reduce late-stage
  rework and costly design iterations. Unifies Cadence multiphysics signoff solutions, such as
  Celsius Thermal Solver, Clarity 3D Solver for 3D-EM, MSC Nastran and Marc Linear
  and Non-Linear Finite Element Analysis Solvers for mechanical analysis, and Sigrity X
  Platform for signal and power integrity.
• Limiting expensive respins by identifying system issues earlier in development.
• Enabling product-level optimization, including co-optimization with advanced packaging
  approaches.

Industry Leaders Advancing Agentic AI with Cadence
Cadence is collaborating with industry leaders to deploy AuraStack AI Super Agent workflows for real-
world advanced IC packaging and PCB design challenges.

NVIDIA is using Cadence to help automate and optimize increasingly complex system design
workflows for its engineering teams.

“The scale and complexity of modern AI infrastructure demands a new design approach,” said Tim
Costa, vice president and general manager of computational engineering at NVIDIA. “NVIDIA’s
collaboration with Cadence is advancing AI-powered engineering workflows that accelerate design
convergence and innovation across the industry. The Cadence AuraStack AI Super Agent and the
Millennium M2000 Supercomputer deliver up to 20X faster multiphysics performance, giving our
engineers the capability to tackle the most demanding design challenges and bring the next
generation of AI infrastructure to life.”

Cadence is partnering with TSMC to help customers accelerate advanced package implementation
through AI-driven automation, enabling timely design convergence for increasingly complex multi-die
systems.

“As advanced packaging complexity grows, customers need new levels of automation to achieve
timely design convergence,” said Aveek Sarkar, director of the Ecosystem and Alliance
Management Division at TSMC. “Our long-standing partnership with Open Innovation Platform
(OIP) ecosystem partners like Cadence to deliver advanced package design and verification solutions
for TSMC 3DFabric technologies helps customers accelerate the realization of next-generation
multi-die systems for AI and high-performance computing applications. Through our multi-year
collaboration on substrate auto routing, we are already enabling customers to boost productivity by
100X while delivering quality of results similar to manual routing.”

Socionext is leveraging Cadence to accelerate the automation and optimization of increasingly
complex semiconductor package and PCB design workflows.

“AI-driven agents are set to transform IC package and PCB design by automating SI, PI and thermal
workflows and enabling generative design,” said Iwasaki Toshifumi, lead design execution leading
unit, Global Leading Group at Socionext Inc. “This acceleration allows our engineers to focus on
higher-value work like architecture exploration, margin optimization, and multiphysics tradeoffs, while
capabilities such as automated routing and chip-package-board co-design accelerate convergence
and reduce manual effort.”

FORVIA HELLA continues to advance intelligent, sustainable mobility solutions that will define the
future of automotive technology.

“Working closely with Cadence has fundamentally changed the way FORVIA HELLA develops
advanced automotive electronics. Using AI-assisted placement technology, a task involving the
placement of 300 components that previously took up to four days can now be completed in just four
minutes,” said Sven Hoenecke, president & CEO, Electronics NSA at FORVIA HELLA. “This step
change in productivity allows our engineers to evaluate more design alternatives, optimize layouts
earlier in the development process, and accelerate the development of innovative products without
compromising quality. By automating repetitive work, our teams can focus more time on solving
complex engineering challenges and bringing new technologies to market faster.”

Schneider Electric is collaborating with Cadence to apply AI-driven design automation and
engineering expertise to accelerate electronic design workflows and scale institutional knowledge
across engineering teams.

“At Schneider Electric, we see AI as much more than a productivity tool. Our collaboration with
Cadence has demonstrated the potential of AI to accelerate design activities and improve engineer
efficiency,” said Daniel Gheno, senior vice president, Innovation and Technology EM at
Schneider Electric. “The next frontier is to combine design automation with engineering expertise,
enabling companies to capture decades of know-how and make robust design decisions available to
every engineer. We believe this is where AI can truly transform electronic design.”

The post Cadence Introduces AuraStack AI Super Agent, the World’s First Agentic AI Platform for PCB and Advanced Packaging appeared first on ELE Times.

Keysight Technologies, Inc. has been selected by the European Space Agency (ESA)
to lead a three‑year development program focused on creating secure, blockchain‑enabled
anomaly detection for 5G non‑terrestrial networks (NTN). Keysight will serve as the prime
contractor, collaborating with Sateliot to support key technical development and satellite mission
integration.

As more satellite communication constellations are deployed, space‑based networks are
becoming increasingly complex, with growing interactions between satellites, ground systems,
and terrestrial 5G infrastructure. This introduces new challenges related to quality of service,
anomaly management, operational security, and confidence in network behavior once deployed.
Looking ahead to 6G, where non-terrestrial infrastructure will play a central role, ensuring
access to trusted, verifiable data will be critical to enabling autonomous and artificial intelligence
(AI)-driven network operations.

The project, which benefits from the support of ESA’s Space for 5G/6G & Sustainable
Connectivity program line within the Agency’s Advanced Research in Telecommunications
Systems (ARTES), is designed to address these challenges by establishing a secure, verifiable
trust framework for NTN environments. Keysight will leverage its design, test, and measurement
expertise to explore how blockchain, AI, machine learning (ML), and digital calibration
certificates can be applied across the full NTN lifecycle, from satellite manufacturing and
calibration to in‑orbit operation and service delivery.

Albert Pujol, Chief Innovation Officer at Sateliot, stated: “This program represents a
definitive shift toward integrating space-based assets into a secure, unified 5G ecosystem. By
anchoring blockchain within our orbital operations, we are creating a transparent validation layer
that allows massive IoT networks to scale globally while consistently ensuring security and
performance.”

Antonio Franchi, Head of the Space for 5G/6G & Sustainable Connectivity programme at
ESA, said: “The future of Europe’s connectivity depends on networks that are not only
advanced, but trusted, resilient and secure. Supporting this project, which benefits from
Keysight’s leadership and Sateliot’s expertise, underscores ESA’s commitment to helping
pioneer the technologies required to safeguard the integration of non-terrestrial and terrestrial
networks. Together, we’re not only taking a step towards defending Europe’s communications
against spoofing and tampering, but we’re also ensuring that our Member States remain at the
forefront of secure 5G and future 6G communications.”

Eric Taylor, Vice President, Aerospace, Defense and Government Solutions at Keysight,
said: “This initiative represents a major step toward securing hybrid space–terrestrial networks
at a time when global NTN deployments are accelerating. By combining test and measurement
expertise with AI-driven assurance and blockchain technologies, this work will demonstrate how
trust can be embedded across the full NTN lifecycle – from design and validation through in-orbit
operation.”

By integrating these technologies, the program aims to enhance the integrity and reliability of
space‑based IoT, 5G, and future 6G communications, helping to protect networks from
spoofing, tampering, and other cyber threats. Over the course of the program, development will
progress from laboratory research and prototyping to a full in‑orbit demonstration, validating
how blockchain‑anchored trust, autonomous anomaly detection, and secure telemetry can be
applied in operational satellite environments.

The ESA‑funded program is expected to inform future NTN operations, strengthen Europe’s
position in secure satellite connectivity, and accelerate the adoption of trusted space‑based
5G/6G networks worldwide.

The post Keysight and Sateliot Selected by European Space Agency to Develop Blockchain‑Enabled Framework for 5G Non‑Terrestrial Networks appeared first on ELE Times.

BluGlass Ltd of Silverwater, Australia — which develops and manufactures gallium nitride (GaN) visible laser diodes based on its proprietary low-temperature, low-hydrogen remote-plasma chemical vapor deposition (RPCVD) technology — has secured a AUS$1.4m (US$1m) commitment from Uviquity of Raleigh, NC, USA (a venture-backed start-up pioneering wide-bandgap integrated photonics) for Phase II of its joint development agreement (JDA)...

КПІ ім. Ігоря Сікорського — серед лідерів Консолідованого рейтингу закладів вищої освіти України 2026! KPI4U-2 чт, 07/16/2026 - 11:45

WeEn Semiconductors of Shanghai, China — a joint venture company formed by NXP Semiconductors and Beijing JianGuang Asset Management Co Ltd (JAC Capital) in 2015 that develops and manufactures bipolar power semiconductor products — has launched a new family of AC–DC and DC–DC silicon carbide (SiC) power modules to target the growing range of solid-state transformer (SST) applications, as well as electric vehicle (EV) super-chargers and smart-grid/renewable applications...

submitted by /u/BlownUpCapacitor [link] [comments]

Ignore the rock drawer I didn't have a better place for my cool rocks submitted by /u/Sprucehouse [link] [comments]

Infineon’s RIC70115 GaN HEMT gate driver provides the radiation hardness and long-term reliability required for satellite and space applications. Supporting both silicon FETs and GaN HEMTs in low-side and high-side configurations, the device helps ease the transition from silicon to GaN.

Operating over a temperature range of -55°C to +125°C, the RIC70115 is characterized for single-event effects up to a linear energy transfer (LET) of 81.9 MeV·cm²/mg and a total ionizing dose (TID) of up to 100 krad(Si). Its independent Miller clamp prevents parasitic-induced turn-on while maintaining switching speed, reducing switching losses. Truly differential input logic rejects common-mode noise and minimizes the effects of EMI and RFI.

An integrated low-dropout regulator generates a tightly regulated 4.8-V drive voltage from a 5-V or 12-V source, supporting a supply voltage range of 4.75 V to 15 V. The RIC70115 provides a 1.5-A source current and a 2.5-A sink current, with propagation delay matching of up to 2.9 ns.

The RIC70115 is offered in a hermetically sealed 16-pin LCC package or in die form. 

RIC70115 product page 

Infineon Technologies  

The post Rad-hard gate driver enables GaN adoption appeared first on EDN.

Tomocube’s HT-T1D is a desktop holotomography system for high-resolution, non-destructive 3D defect analysis of glass substrates used in semiconductor packaging. It images internal defects and other fine features with a lateral resolution of 161 nm and an axial resolution of 1.298 µm.

Glass core substrates and glass interposers are gaining traction as key enabling materials for AI accelerators, high-bandwidth memory, and other advanced packaging applications. Manufacturers need to identify the root causes of micro-defects and quickly translate inspection data into process improvements.

The HT-T1D system applies visible-light holotomography to visualize the three-dimensional refractive-index distribution inside glass with refractive-index sensitivity down to ~10⁻⁴ Δn. Its non-destructive measurements enable repeated analysis of the same location across successive process stages, allowing users to track when and how defects form, propagate, or enlarge.

When conventional in-line panel inspection tools such as automated optical inspection (AOI) systems flag a potential defect, the HT-T1D uses the corresponding coordinates to reconstruct the interior of the glass substrate in three dimensions. It resolves the defect’s location, morphology, and depth profile that surface inspection alone cannot reveal.

HT-T1D product page 

Tomocube

The post Holotomography system analyzes glass defects appeared first on EDN.

Two TVS diode series from Littelfuse, the TP5.0SMD-FL and TP1KSMB-FL, protect 48-V automotive electronics from voltage transients. Based on the FlatSuppressX TVS architecture, the devices exhibit a flatter clamping characteristic with a significantly lower clamping voltage than conventional TVS components. Their foldback/snapback function tightly controls transient response while avoiding latch-up risk.

The TP5.0SMD-FL series has a peak pulse power rating of up to 5 kW in a DO-214AB (SMC) package. The TP1KSMB-FL series has a peak pulse power rating of up to 1 kW in a DO-214AA (SMB) package. Devices in both series are AEC-Q101 qualified, providing scalable protection options for varying system requirements. Their architecture enhances system efficiency, enabling the use of lower-rated downstream components.

Optimized for protecting I/O interfaces, power buses, and other vulnerable circuits in automotive electronics, particularly 48-V architectures, these TVS diodes provide a fast transient response, typically in less than 1 ps.

The TP5.0SMD-FL and TP1KSMB-FL series are available in tape and reel format in quantities of 3,000. Sample requests are accepted through authorized Littelfuse distributors worldwide. 

Littelfuse

The post TVS diodes clamp automotive transients appeared first on EDN.

MPLAB XC Pro Compilers and the MPLAB Machine Learning Development Suite from Microchip are now available at no cost. Unlimited installations give users free access to advanced optimization capabilities and integrated embedded machine learning workflows, whether working individually or as part of a development team.

Previously available through paid license tiers, the MPLAB XC Pro Compilers reduce code size, lower memory usage, improve execution speed, and generate architecture-optimized code for embedded applications. These capabilities support software development across Microchip’s 8-bit, 16-bit, and 32-bit MCU and MPU portfolio.

The MPLAB Machine Learning Development Suite includes the Model Builder plug-in for MPLAB X IDE and Microsoft Visual Studio Code. It generates optimized AI and IoT sensor recognition code to support embedded machine learning development on resource-constrained devices.

MPLAB XC Compilers and the MPLAB Machine Learning Development Suite are now available as free, unrestricted-use downloads.

Microchip Technology

The post Microchip offers free MPLAB compilers, AI tools appeared first on EDN.

The Rambus DDR5 9600 server RDIMM chipset supports DDR5 RDIMMs operating at up to 9600 MT/s in CPU-based server platforms. The chipset is built around the RCD06 sixth-generation registering clock driver, which increases bandwidth by 20% over the previous generation. As a key control-plane chip, the registering clock driver distributes command/address, chip-select, and clock signals to the DRAM devices on the RDIMM.

In addition to the RCD06, the chipset includes the PMIC5030 power management IC and a serial presence detect (SPD) hub with an integrated temperature sensor. The SPD hub communicates via the I3C bus for system configuration and thermal management. Two dedicated temperature sensors per DIMM provide precision thermal sensing and, in combination with the SPD hub, enable three points of thermal telemetry for the memory module.

By integrating clocking, control, and power management functions, the chipset helps ensure signal and power integrity at high data rates while simplifying the design of DDR5 RDIMMs. This level of integration becomes increasingly important as server architectures scale to support higher processor core counts, larger memory capacities, and the sustained demands of continuously running AI workloads.

Learn more about the DDR5 9600 Server RDIMM chipset here.

Rambus

The post RDIMM chipset boosts server memory bandwidth appeared first on EDN.

Vector Photonics Ltd of the West of Scotland Science Park (which was spun off from the University of Glasgow in 2020, based on research led by professor Richard Hogg) has begun a new program that addresses a critical and growing challenge in advanced photonics manufacturing: the lack of scalable, thermally efficient and resource-effective packaging for photonic crystal surface-emitting lasers (PCSELs)...