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Analog and mixed-signal design at sub-5 nm nodes has reached a threshold where deterministic corner-based signoff and brute-force Monte Carlo can no longer simultaneously satisfy convergence speed, tail-yield condense, and engineering interpretability.

This paper examines QUINSIM’s Analog Uncertainty-Aware Design (AUAD) platform—a physics-informed, surrogate-driven uncertainty quantification engine that wraps existing SPICE and TCAD simulators as black boxes.

We characterize the mathematical architecture (sparse polynomial chaos expansion, R-Vine copula process modeling, Sobol variance decomposition, and efficient global optimization), quantify performance across six canonical analog verification benchmarks (SRAM, LNA/VCO, SAR ADC, automotive power IC, TCAD/GAA nanosheet, and timing closure), and analyze the structural transformation AUAD imposes on analog design economics, organizational workflows, and EDA ecosystem dynamics.

We conclude that AUAD is not an incremental acceleration of existing flows; it constitutes a new design epistemology in which uncertainty is a first-class object—characterized, propagated, decomposed, and optimized—rather than a late-cycle verification penalty.

Analog variability crisis at advanced nodes

Analog and mixed-signal design at sub-5 nm nodes has entered a regime where the statistical toolkit inherited from the 1990s—Gaussian corner models and brute-force Monte Carlo—can no longer simultaneously satisfy industrial signoff requirements. Three overlapping crises converge: non-Gaussian process physics, exponentially expensive tail convergence, and opacity of failure attribution. Together they constitute the analog variability crisis, a condition in which the standard toolkit cannot adequately address tail-yield confidence at acceptable engineering cost.

The physics of non-Gaussian variation

Classical statistical IC design rests on a Gaussian assumption inherited from diffusion-dominated transistor physics of the 1980s. In that regime, bulk MOSFET threshold voltage Vth was well-approximated as normally distributed, making a standard deviation σ extracted from wafer data a sufficient design lever. At sub-10 nm nodes, this approximation breaks down for fundamental physical reasons.

Random discrete dopant (RDD) fluctuations produce heavy-tailed, skewed Vth distributions whose kurtosis significantly exceeds the Gaussian value of three. Line-edge roughness (LER) in EUV-patterned FinFET fins creates systematic spatial correlations between adjacent devices that no single-transistor Gaussian model can express. FDSOI back-gate coupling creates strong nonlinear co-dependence between Vth and DVT0W parameters that Gaussian copulas severely underestimate.

The consequence is stark: every PDK σ value that rests on a Gaussian marginal is a physically incorrect model for the circuit’s actual failure space. Corner models compound the problem by treating process parameters as independently varying—an assumption falsified by the correlated etch and deposition physics of modern advanced nodes. A corner labeled “SS” (slow-slow) is a specification convenience, not a probabilistic claim about the failure boundary.

The convergence economics of deep-tail analysis

Monte Carlo convergence follows the 1/√ N law: to halve the estimation error on a yield metric, four times as many simulations are required. For SRAM static noise margin (SNM) qualification at 5σ—the product-level target for leading-edge memory—direct Monte Carlo requires on the order of 107 SPICE evaluations.

At a conservative 3 seconds per simulation on modern hardware, this translates to approximately 347 days of wall-clock compute per circuit per operating corner. Modern SRAM products span multiple corners, temperatures, and supply voltages, multiplying this burden by a factor of 10–50.

The attribution gap

Perhaps the least-discussed failure of conventional flows is epistemic. Monte Carlo can answer “what is the yield?” but not “which parameters are responsible, and by how much?” Answering the latter requires a highly-designed factorial experiment or auxiliary regression—both expensive and approximate.

In a 57-parameter FinFET PDK, attributing yield loss to a specific root cause without attributing yield loss to a specific root cause without analytical sensitivity tools means teams spend weeks on iterative knob-turning that is effectively uninformed trial and error.

This attribution gap directly inflates design cycle time. When the nominal design fails Monte Carlo signoff without variance decomposition, the team must rely on engineering intuition and costly re-simulation campaigns to identify root causes—a process that can consume months at advanced nodes.

Figure 1 In simulation budget comparison, see QUINSIM sPCE (~350 calls) vs. direct Monte Carlo (~10,000 shown; 107 for full 5σ) for a 57-parameter 5 nm FinFET SRAM SNM characterization. Source: QUINSIM

Why corners cannot patch the gap

For uncorrelated Gaussian parameters, an SS corner is geometrically remote from the actual 6σ failure hyperplane in a high-dimensional parameter space. For non-Gaussian parameters with nonlinear correlations, the SS corner may not even represent the worst-case direction—the actual failure mode may lie in a cross-parameter interaction that no PVT corner captures.

AUAD: Architecture and mathematical foundations

QUINSIM’s Analog Uncertainty-Aware Design platform is structured as a four-stage pipeline that treats the existing SPICE or TCAD simulator as an opaque black box—preserving compatibility with Cadence Spectre, Synopsys HSPICE, Mentor Eldo, and Synopsys Sentaurus without modification. As shown in Figure 2, uncertainty inputs are characterized from foundry data; adaptive sampling builds a sparse surrogate; sensitivity and yield surfaces are extracted analytically; and robust optimization acts directly on the uncertainty-aware objective.

Figure 2 In AUAD four-stage pipeline, each stage is analytically connected to the next: foundry data flows through copula characterization into sPCE training, then into zero-cost Sobol decomposition, and finally into EGO-based robust optimization—all without a single additional SPICE call beyond the initial adaptive sample set. Source: QUINSIM

Stage 1: Non-Gaussian joint distribution characterization

Real foundry measurement data for parameters such as Vth, Tox, Leff, and inter-device mismatch do not conform to Gaussian distributions. QUINSIM fits marginals using non-parametric kernel density estimation (KDE) or parametric heavy-tail distributions (Student-t, skew-normal). Joint dependence between parameters is captured using R-vine copulas—pair-copula constructions that model arbitrary bivariate relationships in a recursive tree structure, capturing nonlinear co-dependence that Gaussian or elliptical copulas systematically miss.

The Rosenblatt transformation maps correlated, non-Gaussian samples into independent uniform (then Gaussian) space where Polynomial Chaos Expansion is analytically valid. This is the technical key that makes sPCE applicable to real foundry data with correlated, non-Gaussian parameters, a capability absent from conventional Gaussian-input PCE tools.

Stage 2: Sparse polynomial chaos expansion surrogate

The circuit performance metric Y (SNM, ENOB, NF, efficiency…) is approximated as a polynomial functional of standardised process inputs Z:

Physical sparsity—circuits respond strongly to a small subset of parameters even in 50+ dimensional PDK spaces—combined with active-learning sample placement concentrates 100–500 simulator calls in the regions that maximally reduce surrogate error. The trained surrogate then evaluates in microseconds, enabling post-hoc Monte Carlo with 106–108 samples at negligible additional cost.

Stage 3: Analytical Sobol sensitivity and yield surface extraction

Global sensitivity indices—Sobol first-order and total-effect—are computed analytically from the PCE coefficients at zero additional simulation cost:

Figure 3 Example Sobol-derived metric importance ranking across six performance dimensions (efficiency, output swing, peak current, power factor, THD, EMI) for a power converter design. PF and Eff dominate the variance budget, immediately directing robust design effort to the parameters that matter most. The ranking costs zero additional simulations. Source: QUINSIM

Stage 4: Efficient global optimization (EGO)

With the surrogate trained and sensitivity indices computed, QUINSIM applies efficient global optimization (EGO) to maximize yield over the design parameter space. EGO uses a Kriging (Gaussian process) meta-model of the yield surface together with an expected improvement (EI) acquisition function: EI(x) = E[max(f(x) − f*, 0)]. This Bayesian optimization approach locates yield-maximizing design parameters in fewer than 200 evaluations for 50+ dimensional spaces—unachievable with classical gradient-based methods when the yield surface is non-convex or multimodal.

Benchmark use cases: Demonstrating AUAD impact

QUINSIM has constructed six canonical AUAD benchmarks spanning memory, RF, data conversion, automotive power electronics, and device-level TCAD calibration. These demonstrators collectively define the platform’s technical scope and establish its performance claims against reference instances from published literature and ICCAD benchmarks.

Figure 4 In this 6T SRAM bit-cell schematic at 5-nm FinFET, static noise margin (SNM) and write-margin jointly depend on all six transistors’ Vth, Tox, Leff, and mismatch. QUINSIM’s sPCE characterizes the full 5σ SNM failure surface from 350 adaptive Spectre calls, versus 107 for direct Monte Carlo. Source: QUINSIM

SRAM bit-cell: 5σ SNM in 350 simulations

The canonical AUAD challenge is SNM qualification for 5 nm 6T/8T SRAM. QUINSIM constructs a 57 parameter sPCE surrogate using 350 adaptive Spectre calls, recovers the full SNM probability density function including the 5σ tail, identifies three dominant failure drivers analytically (Tox, Vth_PMOS, Leff), and completes in under 4 hours on standard workstation hardware. The Sobol decomposition reveals Tox alone accounts for 38% of SNM variance—enabling targeted process control recommendations to the foundry that would be invisible to any Monte Carlo approach.

RF LNA/VCO: Capturing bimodal failure distributions

In 28/22 nm FDSOI, QUINSIM employs a Student-t copula to model the Vth–DVT0W co-dependence from back-gate coupling. The result is accurate prediction of a bimodal noise-figure distribution—an artifact of nonlinear coupling that Gaussian-assumption tools miss entirely. QUINSIMʼs design centering identifies a 15% yield improvement and locates the real 6σ worst-case operating point. Multimodal output distributions imply correlated input failure modes that only copula-based process models can resolve.

Figure 5 In FDSOI LNA and the resulting bimodal noise-figure distribution, the back-gate voltage VBG creates nonlinear Vth–DVT0W dependence. QUINSIM’s Student-t copula reveals a second failure mode (Mode 2) that a Gaussian process model misses, a production-impact failure invisible to conventional statistical signoff. Source: QUINSIM

High-speed SAR ADC: 150-parameter ENOB characterization

ENOB degradation in a SAR ADC arises from a correlated combination of capacitor mismatch, comparator offset, jitter, and reference noise. QUINSIMʼs structured high-dimensional sPCE handles 150 correlated parameters from 600 adaptive simulations, delivering the full ENOB probability density function and per-specification tail failure probability in 8 hours.

An equivalent Monte Carlo campaign spanning this 150-parameter space to 6σ confidence would require 3–4 weeks. The surrogate’s full distributional output also exposes ENOB distribution shape—skew, kurtosis, multi-mode structure—that pass/fail counting cannot reveal.

Automotive power IC: Joint process-temperature surrogates

Automotive-grade ICs (AEC-Q100 Grade 0) must operate from −40°C to +175°C. QUINSIM extends the uncertain parameter space to treat temperature as a continuous uncertain dimension, building joint process-temperature surrogates that deliver 100× cost reduction relative to a conventional Monte Carlo × PVT sweep. This is particularly relevant for SiC power stages, gate drivers, current sensors, and high voltage control loops, where tail-yield and reliability must be jointly evaluated across the full operating envelope, not at isolated corners.

TCAD/GAA nanosheet: Bayesian process calibration in 48 hours

TCAD calibration for a new process node currently requires 2–4 weeks of manual deterministic iteration to fit compact model parameters (BSIM-CMG, PSP) to measured I-V characteristics. QUINSIMʼs Bayesian calibration engine applies active learning to TCAD simulation scheduling, fits a posterior distribution over the full set of physical model parameters rather than a point estimate, and propagates that posterior uncertainty through the compact model extraction chain into a UQ-aware PDK (UQ-PDK). The result: 48-hour calibration cycles with honest uncertainty bounds on every PDK parameter.

Capabilities unlocked by AUAD

Beyond benchmark-level performance numbers, AUAD unlocks capabilities that are qualitatively unavailable within the Monte Carlo paradigm regardless of the compute budget applied.

Analytical variance budget decomposition

For a 57-parameter PDK space, conventional Monte Carlo can determine that yield is 97.2%—but not which parameters explain the 2.8% failure variance. QUINSIMʼs Sobol decomposition provides a ranked list of first-order and total-effect indices for every process parameter, computed analytically from sPCE coefficients at zero simulation cost. This transforms failure analysis from “simulate more” to “fix these three parameters in this priority order.”

Full probability density output instead of pass/fail counting

Surrogate-based UQ produces the full PDF of any circuit metric as a live design object. For a SAR ADC, this means designers see not just “mean ENOB = 11.2 bits, σ = 0.15 bits” but the complete distributional shape—whether it’s symmetric, heavy-tailed, or bimodal. This changes specification verification from a Gaussian-approximation exercise to a physics-honest probability assessment.

Robust design centering and optimization via EGO

EGO-based robust optimization acts on the yield surface, not the nominal performance surface. A design point that is optimal in nominal performance may sit on a steep yield cliff; a slightly sub-optimal nominal design may command a wide, flat yield basin. AUAD makes this trade-off visible and optimizable: in the FDSOI LNA benchmark, EGO-guided centering recovered 15% yield improvement that was invisible to nominal optimization. In timing-closure benchmarks, robust optimization produced higher shipping frequency with tighter but better-justified margins than guard-banding.

Partner-ready traceability and auditability

QUINSIMʼs analytical UQ framework produces structured, reproducible outputs: specific PCE coefficients, Sobol index tables, yield surface plots, failure-mode rankings—all derived from a documented mathematical procedure. For foundry partnerships, IP qualification packages, and AEC-Q100 automotive compliance dossiers, auditability of the statistical analysis is increasingly a contractual requirement. AUADʼs analytical traceability directly satisfies this requirement in a way that a random-seed-dependent Monte Carlo run cannot.

The irreversible transformation of analog IC design

AUAD is not a feature addition to existing EDA flows. It constitutes a structural transformation of how analog design decisions are made, justified, and communicated. Once a design team inhabits an environment where uncertainty is analytically characterized and continuously actionable, the prior workflow—simulate, margin, and iterate—becomes evidently inferior and institutionally difficult to defend.

From “simulate and margin” to “characterize, rank, optimize, explain”

The existing design-verification loop treats Monte Carlo as a late-stage checksum applied after nominal design completion. When the gate fails, the team iterates blindly without analytical guidance. In an AUAD workflow, the uncertainty model is active from the first design iteration: parameters are characterized from foundry data, the surrogate is trained after 100–500 simulation calls, and Sobol rankings immediately direct design effort. The loop compresses from months to days not because the simulator runs faster, but because engineering judgment is guided by quantitative attribution rather than intuition.

Figure 6 In traditional simulation-centric design loop (red) vs. AUAD design loop (blue/green), the structural difference is that AUAD delivers actionable attribution at every stage. Where the traditional loop requires months of blind re-simulation on signoff failure, AUAD’s Sobol-guided EGO reaches tape-out readiness in days. Source: QUINSIM

Economic consequences for design organizations

The commercial implications of a 1000× simulation reduction extend beyond throughput. Fewer SPICE simulations mean fewer licensed EDA seat-hours consumed, directly reducing the variable cost of advanced-node verification.

Faster yield diagnosis compresses design cycles currently measured in 18-24 months for leading-edge analog. Better yield prediction reduces unnecessary margin padding, and in volume production, even 1–2% yield recovery at advanced nodes translates to tens of millions of dollars in recaptured wafer value per year. QUINSIM positions these not as incremental improvements but as step-function changes in the economics of analog design.

EDA ecosystem dynamics: The intelligence layer

QUINSIMʼs black-box simulator wrapper positions it as an intelligence layer on top of, not in competition with, the SPICE simulation cores of Cadence, Synopsys, and Siemens EDA. Incumbents can embed the UQ engine as a differentiated variation-analysis module without displacing their core circuit simulation products. The roadmap QUINSIM publishes explicitly names a “Cloud SaaS, UQ-PDK marketplace” and positions the platform as an acquisition target in the €100–200M range—a signal of deliberate ecosystem positioning rather than standalone scaling.

Foundries and IP providers face an analogous opportunity. A UQ-PDK that exposes calibrated non-Gaussian marginals, copula dependence models, and Bayesian parameter posteriors is qualitatively richer than a conventional σ-table, enabling customers to achieve better first-silicon yield with fewer iterations—a tangible competitive differentiator in a market where design starts are competed on tool quality.

The transformation is irreversible

The historical pattern in EDA adoption suggests that once a design team experiences analytical yield attribution—knowing which parameters are responsible for yield loss and by how much, derivable in hours—returning to uninformed Monte Carlo iteration is institutionally unacceptable. The same dynamic played out when formal verification replaced simulation-only digital signoff, and when place-and-route tools supplanted manual floorplanning.

AUAD represents the analog equivalent of that transition: a shift from a compute-intensive empirical paradigm to a mathematically structured, interpretable, and continuously optimizable uncertainty framework.

The chips shipping in 2029 and beyond will be designed by teams who characterize, rank, optimize, and explain the uncertainty in their analog blocks from the first simulation run. Those teams will converge faster, yield higher, and signoff with tail-probability confidence that today’s Monte Carlo paradigm can not match. QUINSIM AUAD is the platform enabling this transition today.

Christophe Bianchi is CEO and founder of QUINSIM.

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The post Analog uncertainty-aware design: How it replaces Monte Carlo with certifiable yield intelligence appeared first on EDN.

submitted by /u/1Davide [link] [comments]

A novel switch architecture caters to extended battery range coupled with robust protection and diagnostic strategies.

For automotive control units, the smart output switches operating contactor coils, lamps, solenoids, PTC (positive temperature coefficient) heater coils and the like form an indispensable “last mile” interface to the external world. Legacy solutions available from global automotive semiconductor companies suffer from the following weaknesses:

• No off-the-shelf power switch IC is currently available beyond 24 volts, whereas upcoming vehicle architectures are envisioning 48 VDC or higher buses to reduce the weight of associated copper wiring.
• They consume a minimum of two interface CPU pins per switch; one for the command output and another for the status input.
• “Short to power bus” protection is based on current limiting followed by a thermal trip, in the process often exceeding the absolute maximum junction temperature prior to the actual tripping event.
• The on-chip power device often has limited overvoltage and inductive transient capabilities, requiring external protection components.

Wow the engineering world with your unique design: Design Ideas Submission Guide

The circuit in Figure 1 illustrates a solution that resolves all of these issues.

Figure 1 This design idea is primarily intended to depict a novel switch architecture that can cater to extended battery range coupled with robust protection and diagnostic strategies. It also uses only a single CPU pin-per-switch, as opposed to two CPU pins for legacy architectures. The load coil can be typically rated as a 48V DC, 122 mA contactor coil used for EV/HEV circuits for a 48 volt bus. A typical 12 volt automotive relay coil may draw 95 mA, while a 24 volt version can draw approximately 68 mA.

In this example circuit:

• Q1 = MMBTA 92-q
• Q2 = 2N2222
• Q3 = MMBTA 42-q
• D1,D2 = 1N4004
• D3 = 1N4148
• R1 = 47K ohm
• R2,R3 = 47K ohm
• R4 = 2.2 ohm
• R5 = 10K ohm
• R6 = 1K ohm
• C1 = C2 = 0.1 microfarad, 25 volts

The selection of components, resistor values etc. may need to be tailored to address the expected range of application loads, along with CPU and other logic voltage/current characteristics.

The heart of the circuit is the Q1-plus-Q3 latch. Q2 acts as constant current limit that prevents momentary thermal runaway that would otherwise destroy Q1 during a “short to power bus” event. In automotive application, a service engineer or production technician might accidentally short-circuit the output point (Q1 collector) to the power bus. Automotive norms dictate that the power switch must incorporate built-in short circuit protection to cover this and other scenarios.

When the CPU wants to switch on the load, it issues a rising-edge command through the C1-plus-R1 edge trigger circuit to the Q1-plus-Q3 latch. This command sets the latch output to its active low level, thus turning on the contactor coil load. The CPU pin can now reconfigure itself as a diagnostic status input, since the Q1-plus-Q3 latch now self-sustains at the “on” state without needing any further base current assistance from the CPU. The CPU pin, now acting as a diagnostic input, reads a “logic high status”, indicating that the latch output is healthy and powering the load as intended.

In case of an accidental short to power-bus event—in other words, the load coil facing a short circuit across itself—Q3 being a PNP transistor switches off due to its base emitter circuit in effect getting short-circuited (Figure 2). This “resets” the latch by turning off Q1, also saving it from the over-current condition.

Figure 2 This short-circuit protection field performance plot of the circuit shows its near-instantaneous trip mechanism for the output switch, which resets the associated latch.

Transistor Q2 limits the momentary rise in Q1 current at the short-circuit instant to a value of around 318 mA (700 mV/2.2 ohms). This abrupt current limit saves Q1 from destruction due to a thermal runaway before Q3 transistor’s turn-off can safely place it in an “off” state. The CPU diagnostic status input pin now reads a “logic low” level indicating that the latch is turned off, due to a short circuit fault at the output. Capacitor C2 provides ESD protection, along with noise interference filtering that may accidentally operate the latch.

Whenever the CPU needs to issue a turn-off command to a latched switch which is in an “on” state, it presents a logic low level at its output interface pin. This low-level voltage turns off the latch through diode D1. Diode D6 and resistor R1 suppress the inductive flyback transient. Diode D1 may be replaced by a suitable Schottky diode to ensure a robust turn-off of the latched switch.

Unlike legacy smart switch solutions, this circuit does not depend on thermal trip-based protection, hence its junction temperature remains absolutely stable. At the time of a short circuit, there will be an instantaneous current-limited spike. The architecture unburdens software from repeatedly monitoring and turning off the smart switch for short-circuit protection (in order to ensure a safe turn-off even before a thermal trip) as may be required for a legacy switch architecture. It instead repartitions the instant short-circuit protection task to the hardware trip circuit, leaving software to monitor and detect the the short-circuit event on an as-possible basis without worry about any real-time protection deadlines.

The circuit can alternatively be implemented in integrated circuit (IC) form, at least to a degree. A power switch element may alternatively be located at and connected to the IC from the outside if it can’t be packaged within the chip, which can still integrate the remainder of the low current driving, protection and diagnostic logic.

Vishwas Vaidya is a graduate of the Indian Institute of Technology in Delhi, India. Currently, he is self-employed as an engineering consultant and industry faculty member in the field of embedded systems for global automotive clients and high-repute academic institutions. Vishwas’ articles and research reports have appeared in many worldwide engineering publications.

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The post Automotive low side output switch architecture suitable for 8 to 48 volt buses and beyond appeared first on EDN.

The South Wales-based compound semiconductor cluster CSconnected Ltd has announced the successful applicants to the fourth and final funding call of its £1m Supply Chain Development Programme, delivered in partnership with Cardiff Capital Region (CCR). The program provides grants of up to £100,000 to help strengthen the compound semiconductor supply chain in South Wales by supporting capability and capacity development, increasing productivity, competitiveness and creating new commercial opportunities...

Thought this might be interesting to some of you. This is the inside of a failed Fuji Electric 6MBI75SS-120 IGBT module (1200 V / 75 A). It’s quite impressive to see the number of aluminum bonding wires used to connect the dies to the power terminals. The module was already dead, so I decided to open it up rather than throw it away. submitted by /u/No-Childhood320 [link] [comments]

Gallium nitride (GaN) power IC and silicon carbide (SiC) technology firm Navitas Semiconductor Corp of Torrance, CA, USA has filed a patent infringement lawsuit against Renesas Electronics Corp of Tokyo, Japan in the US District Court for the Eastern District of Texas...

Indian defence technology start-up Constelli is bolstering the nation’s home-grown defence electronics ecosystem through its dedicated hardware and software for testing, developing, and validating high-performance radar and electronic-warfare (EW) systems. Headquartered in Hyderabad, Constelli’s technologies are deployed within organisations such as the Defence Research and Development Organisation (DRDO) in India and are licensed to defence firms in overseas markets.

The company also produces high-speed radar processing chips and sub-systems to provide situational awareness and detection of airborne and sea-borne targets or threats. Modern defence platforms require the ability to quickly classify and identify counter signals. These capabilities will become more relevant if they cannot be recognised in real-time. The development also signals the growing use of RF signal processing, FPGA-based computing embedded systems, digital signal processing, and software-defined architecture for defence purposes, within India’s electronics industry.

As Radar and EW technology grows increasingly advanced, robust test and simulation infrastructure will be indispensable in cutting the development cycle and increasing the robustness of such systems. India’s rising interest in private sector tech firms such as Constelli is directly indicative of a wider trend and increasing investment from India’s indigenous private tech firms in developing India’s future defence electronics.

Constelli’s range of technologies spans radar signal processors (RSPs), ELINT systems, ESM equipment, RTA simulators, RIA simulators, and EW test solutions. ELINT systems, ESM equipment, RTA simulators. RIA simulators, and EW test solutions. Engineers can create synthetic battle signals and determine how radar and EW equipment will behave in a particular operating mode.

The post Constelli’s Advanced Radar and EW Technology to Strengthen India’s Defence Electronics Ecosystem appeared first on ELE Times.

Predictive, generative, and agentic AI are not successive generations. They coexist inside enterprise systems, each placing fundamentally different demands on the underlying compute infrastructure.

• Predictive AI classifies, forecasts, and detects within defined boundaries (for instance, identifying a tumor or detecting fraud). GPUs and fixed-function accelerators handle these bounded workloads efficiently.
• Generative AI broadened this scope to text, code, and reasoning. Processor designers responded with a race for floating-point throughput, memory bandwidth, and high-speed interconnects under the assumption that inference was relatively simple: accept a prompt, run the model, and emit tokens.
• Agentic AI breaks that model-centric paradigm. A single task is partitioned among cooperating agents—one retrieves data, another analyzes it, a third writes code, and a fourth verifies policy compliance. The workload shifts from pure matrix multiplication to planning, branching, scheduling, synchronization, and repeated tool execution.
• Enterprise AI applies predictive, generative, and agentic capabilities to real-world business problems using proprietary data, strict access controls, and strict governance. It’s not merely a larger version of consumer generative AI; it is a distinct operating environment that fundamentally reshapes system architecture.

The enterprise context layer

A consumer chatbot relies primarily on pretraining weight memory and optional web search. An enterprise system must operate against information absent from pretraining: engineering specifications, financial ledgers, manufacturing logs, code repositories, and regulatory filings. It must simultaneously enforce who is authorized to see that information, which actions are permitted, and how the interaction is logged for audit.

To accomplish this, enterprise systems combine foundation models with retrieval-augmented generation (RAG), vector databases, knowledge graphs, identity management, policy engines, and workflow orchestration. Collectively, this forms an enterprise context layer, an architectural abstraction whose role is to retrieve relevant organizational knowledge, apply access rules, and ground model output in current operational facts.

An AI software stack is used to manage AI enterprise workloads and reshape AI system architectures. Source: Author

As a result, the question moves from “What does the model know?” to “What does the organization know, what is relevant to this task, and what is this user authorized to execute?“ This shift marks the transition from Inference 1.0 to Inference 2.0.

Comparing the differences between model-centric inference versus workload-centric inference illustrates the transition from Inference 1.0 to Inference 2.0. Source: Author

Consider an engineer at an automotive semiconductor company asking: “Which version of our Ethernet controller complies with ISO 26262 ASIL-D, and does it meet our latest customer requirements?”

The answer does not exist in a single model’s weights. Before reasoning begins, the system must perform vector searches across document management platforms, query a failure modes and effects (FMEDA) database, inspect product lifecycle management (PLM) systems, check source-code repositories, and parse customer change requests. Conventional software services, policy checkers, and foundation models then analyze compliance evidence and flag inconsistencies before an orchestration layer assembles a defensible response.

One query triggers multiple database accesses, security validations, model invocations, and tool executions. Inference is no longer a single forward pass; it’s an orchestrated, multi-domain workflow.

Redefining performance: “Time to a useful answer”

Inference 2.0 alters the practical definition of performance. Model training is throughput-driven, running parallel jobs across thousands of accelerators for weeks. Enterprise users, by contrast, demand rapid, context-accurate responses. A physician reviewing an urgent diagnostic report or an engineer analyzing a production fault cannot benefit from peak token throughput if the system spends seconds waiting on database queries, context loading, or security authorization.

If platform A generates tokens twice as fast as platform B, but platform B retrieves corporate context and coordinates agents with far less overhead, platform B will deliver the end result faster. The meaningful system metric becomes time to a useful answer.

In an enterprise environment, “useful” is strictly constrained by three factors:

1. Correctness: Output meets application-specific domain quality thresholds.
2. Authorization: Access and security rules are strictly enforced.
3. Traceability: Intermediate reasoning steps and supporting evidence are preserved for auditing.

Hardware and system-level bottlenecks

Accelerating matrix multiplication alone yields diminishing returns when non-tensor tasks dominate overall execution time (Amdahl’s Law). Inference 2.0 shifts bottlenecks to working memory management and systemic data movement.

Managing shared working context (KV cache)

LLM inference decode is inherently memory-bound: hardware spends more time moving weights and key-value (KV) cache tensors than performing math. Agentic workflows amplify this problem. A single agent request can fan out into dozens of model calls that share identical system prompts, tool definitions, governance rules, and retrieved context.

Reprocessing this common prefix on every call wastes compute and introduces massive latency. So, systems must implement advanced memory management strategies:

• Paged attention and virtual memory (for instance, vLLM): Allocating KV cache dynamically in non-contiguous memory blocks eliminates internal fragmentation and enables efficient prefix sharing across multiple parallel agents.
• Radix tree prefix caching: Retaining prompt prefixes, system policies, and retrieved documents in memory across requests allows intermediate calls to skip the prefill stage entirely.
• Speculative decoding: Leveraging smaller draft models to propose tokens while using large foundation models for verification reduces latency and conserves high-bandwidth memory (HBM) capacity. As context windows extend to millions of tokens, managing the KV cache hierarchy—deciding what stays in HBM, what offloads to system DDR5, and what gets evicted—becomes as critical to system capacity as peak FLOPS.

Interconnects, DPUs, and heterogeneous memory

Moving data across storage, host memory, and accelerators represents the primary energy and latency penalty in Inference 2.0. Addressing this requires moving beyond traditional PCIe topologies:

• Compute Express Link (CXL): It enables cache-coherent memory sharing and expansion between CPUs, accelerators, and pooled memory devices. By allowing accelerators to access main system memory or shared pools without traditional host-copy overhead, CXL eases HBM capacity pressure during massive multi-agent context retention.
• Data processing units (DPUs) and smart NICs: Offloading line-rate security filtering, identity checks, data encryption, and network serialization to DPUs frees host CPUs and GPUs to focus strictly on orchestration and tensor workloads.
• High-speed scale-Up fabrics: Technologies such as NVLink or Ultra Accelerator Link (UALink) are increasingly vital not just for model parallelism during training, but for rapid KV cache migration and intermediate state transfer between heterogeneous accelerators during inference routing.

The runtime and system orchestration challenge

Inference 2.0 requires the system runtime to act as a distributed resource manager:

• Heterogeneous scheduling: Runtimes must dynamically partition tasks—routing vector searches to specialized vector engines or CPUs, scheduling dense linear algebra on GPUs/ASICs, and executing policy checks on host cores.
• Multi-model serving and isolation: Enterprise runtimes must serve large foundation reasoning models concurrently with smaller, fine-tuned domain models. This demands strict spatial and temporal isolation to prevent low-priority background tasks from degrading real-time user requests.
• Network latency in the compute path: In training, networks synchronize gradient tensors across worker nodes. In Inference 2.0, the network carries prompts, embeddings, RAG chunks, tool outputs, and agent states directly in the critical path. Network latency directly translates to user-perceived response time.

Evolving benchmarks: Measuring what actually matters

Traditional benchmarks like MLPerf inference excel at isolating raw accelerator capability (for example, batch-1 token latency or offline throughput). However, they fail to capture retrieval delay, context switching overhead, network transport, security enforcement, or multi-agent orchestration.

Just as database evaluation evolved from raw CPU clock speeds to holistic transaction benchmarks (like TPC-C and TPC-H), AI benchmarking must evolve to evaluate complete enterprise workflows.

The Inference 2.0 benchmark suite concept

An enterprise-grade benchmark suite should evaluate system performance across realistic operational profiles:

1. End-to-end task completion time: Total elapsed time from initial query input to a fully formatted, authorized response.
2. Context reuse efficiency index: Measures how effectively a system reuses KV cache across multi-turn agentic fan-outs without re-executing prefill phases.
3. Traceability and audit overhead: Evaluates system degradation when capturing complete chain-of-thought, tool invocation, and data provenance logs required for enterprise compliance.
4. Mixed-workload quality-of-service (QoS): Tail-latency (p99) performance when running concurrent workloads (for instance, background vector indexing alongside interactive multi-agent reasoning). Quality and correctness must be reported alongside execution time to ensure speed is never prioritized at the expense of accuracy or security.

Beyond GPU: Building balanced AI systems

Matrix multiplication will remain a core computational requirement, and GPUs will continue to play a central role in AI infrastructure. Modern GPUs have evolved significantly, incorporating lower-precision formats, sparsity support, larger memory footprints, and advanced inference runtimes.

However, accelerating tensor execution alone is no longer sufficient when an increasing fraction of system time and energy is consumed by data movement, context management, network transport, and security validation.

The leading platforms of the Inference 2.0 era will be those engineered for system-level balance. Whether centered on GPUs, specialized ASICs, dynamic CPU-accelerator clusters, or CXL-enabled memory pools, the winning architectures will be judged on a single unified criterion: how efficiently the complete system transforms organizational knowledge into trusted, actionable decisions.

That is the architectural imperative of Inference 2.0.

Lauro Rizzatti is a business development executive with VSORA, a technology company offering silicon semiconductor solutions that aim to redefine silicon performance. He is a noted chip design verification consultant and industry expert on hardware emulation.

Related Content

• Custom AI Inference Has Platform Vendor Living on the Edge
• Partitioning to optimize AI inference for multi-core platforms
• Analog in-memory compute tackles the AI inference conundrum
• As AI Moves from Training to Inference, Optics Moves Closer to the Chip
• The truth about AI inference costs: Why cost-per-token isn’t what it seems

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The electric vehicle industry in India continues to witness large investments as manufacturers scale up their production capacity. The rapid increase in production is also driven by emerging customer demand and increasing competitiveness in the market. With support from the government, improving charging infrastructure and greater adoption of electric mobility, Indian and foreign investors continue to infuse confidence in several emerging Indian EV companies. River Mobility, an electric scooter manufacturing company based in Bengaluru, raised $120 million in its Series C round to scale manufacturing capacity, improve its research and development, and finance new products in electric mobility.

The funding round was led by Yamaha Motor Co., Ltd with participation from existing investors, marking another significant investment in the fast-emerging electric two-wheeler segment in India. The funds will enable River Mobility to boost its production output and expand its retail network across the country, strengthen its supply chain, and invest in next-generation technologies in electric vehicles.

A significant part of the investment will be used to increase the manufacturing capacity of the company in Karnataka. River plans to set up an increased production facility that could produce up to 80,000 electric scooters per month, thus increasing the production capacity by a great extent to cater to the increasing demand of electric scooters in the domestic market and then to export as well.

River Mobility’s successful $120 million funding represents another important step in contributing to the ever-growing EV industry in India. A focus on manufacturing capacity expansion, product innovation, and customer experience will further consolidate its place in the competitive electric two-wheeler market. With growing consumer interest and a maturing EV ecosystem in India, the latest funding for River is a promising development for local manufacturing, technical innovation, and a faster transition toward a sustainable India.

The post River Mobility Raises US$120 Million to Expand EV Manufacturing and Accelerate Product Development appeared first on ELE Times.

The user trial run of India’s Agni-4 medium-range ballestic missile was held on August 6 and was fully successful on Thursday. Missiles are operated from the Integrated Test Range in Chandipur, Odisha. The test run was conducted by the Strategic Force Command with the cooperation of the Defence Research and Development Organisation (DRDO) for the purpose of checking operational and technical aspects of the missiles.

This successful trial demonstrates India’s continued progress in indigenous strategic systems. DRDO (Defence Research and Development Organization) is India’s premier defence R&D organization, and is accountable for several strategic systems including the Agni series of missiles. From an electronics point of view, such systems (Agni-4 in this case) require some cutting-edge electronics like the Guidance, Navigation, and Control Electronics, onboard computing and sensors, and telemetry for their performance.

The missile also has to operate under severe vibration, acceleration, and temperature environments that necessitate high reliability electronics and semiconductor components. Hence, the present test is an achievement much greater than the successful test-firing of the missile. It shows India has advanced further in developing sophisticated indigenous technologies in the domain areas of embedded systems, navigation and control electronics and aerospace engineering.

The success of DRDO further places them in the forefront to boost the country’s strategic powers, and further to accelerate India’s overarching aim to be technologically self-sufficient.

The post Agni-4 Test-Fire Highlights India’s Advances in Strategic Missile Technology appeared first on ELE Times.

With the advancement of technology in the electric vehicle industry, several companies are focusing on building next-generation electric vehicles by pushing for fast charging, longer driving range, and higher power efficiency. Supplying power to electric vehicles has become a key role in shaping the future of electric mobility as it converts the available stored energy into useful kinetic energy and determines the vehicle range, charging speed, and battery lifespan.

To enhance the efficiency of power distribution in electric vehicles, BYD which is a Chinese manufacturer, has launched its latest-generation 1500V automotive-grade silicon carbide (SiC) power technology built for high-voltage applications that would offer higher efficiency and higher thermal capabilities along with super-fast charging technologies.

The new SiC technology is intended to work with BYD’s Super e-Platform (a 1000V high-voltage system integrating batteries, EV Motors and power electronics) which offers megawatt-level charging performance. The company claims that with a voltage rating of 1500V, this is currently the highest voltage rating for mass-produced automotive-grade SiC power chips (capable of high electrical loads).

Car manufacturers are increasingly turning to silicon carbide (SiC) instead of conventional silicon for electric vehicle power electronics. This type of semiconductor technology is characterized by significant improvements in electrical parameters compared with traditional silicon systems offering greatly reduced switching losses, ability to withstand high temperatures, and higher energy efficiency. This enables automotive companies to achieve greater compactness and weight reduction, and reducing cooling systems requirements in their inverters.

The post BYD Introduces 1,500V Silicon Carbide Power Technology to Advance Next-Gen EVs appeared first on ELE Times.

Research on the futuristic defence application of photonic radar is underway in the defence establishment, especially at the Electronic and Radar Development Establishment (LRDE), Defence Research and Development Organisation (DRDO). The DRDO’s technology portfolio includes, among others, photonic radar signal generation, photonic down-converter, photonic analogue-to-digital converter, Optical beam forming array and photonic integrated circuits, which DRDO-LRDE is pursuing, according to an entry on the DRDO website.

These applications rely on photonics for generating and manipulating high-frequency radio signals and may lead to radar systems with enhanced bandwidth, signal processing and sensing features. Several sophisticated technological fields, such as RF engineering, photonic integrated circuits, semiconductor devices, digital signal processing and electronic warfare, merge for this development.

LRDE is collaborating with industry to develop new radar hardware technology too. For instance, MoD procurement data shows an LRDE project scheduled for delivery by July 2026, relating to the design, production, installation and integration of high resolution radar hardware, signifying an increasing industry presence in the Indian radar ecosystem. India’s defence-electronics sector sees the photonic radar as a viable future technology platform for use on future ground-based or aerial sensor suites, and its progress here signifies a parallel advancement in India’s self-reliance endeavours on complex radar technology as well as its semiconductor capabilities.

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​With the increasing demand for software-based design, manufacturing units, and product lifecycle management in the electric mobility industry, EV manufacturers are increasingly adopting advanced digital engineering tools such as Product Lifecycle Management (PLM) and Computer-Aided Design (CAD) to accelerate product development with the highest precision in design and also make the manufacturing process more effective.

These technologies enable engineers to manage complex systems like electric powertrains, batteries, electronics, and software through an interconnected digital engineering workflow. To meet these criteria and stand out in the competitive electric mobility market, Bengaluru-based EV manufacturer Simple Energy has enhanced its digital engineering setup with Siemens PLM technology to support faster product development and efficient manufacturing.

Simple Energy has made partnership with Siemens Digital Industries software and will be using Siemens’ cloud-based Product Lifecycle Management (PLM) software platform Teamcenter X, to facilitate collaboration among engineering team and establishes a connected digital workflow across the product lifecycle.

Simple Energy’s collaboration with Siemens demonstrates how India’s EV startups can adopt cloud-powered engineering and PLM tools to build structured digital workflows. Simple Energy’s current on-going projects ​include the Simple One, OneS and Ultra electric scooters which offer a combination of modern design, connected features, performance and electric powertrain technology.

The adoption of Siemens Teamcenter X by Simple Energy reflects the broader shift toward digital product development. It symbolizes the overall trend towards digital product development in the Indian EV industry. It shows how technologies such as connected engineering tools, cloud PLM, and simulation-driven design (SDD) will be critical to development and supporting the next generation development of electric mobility.

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Wanted to try out these CH32V203 (144MHz RISC-V) chips for a while, so I've decided to make some nice USB gadgets for USB HID injection and just for studying the USB protocol. It has 2 leds and 4 captive touch buttons. It fits nicely into a USB-A port and is very easy to carry around. And with it I've had tons of fun messing around with a bare-metal USB stack, and just in general learning the whole USB protocol. It was really fun trying to make a bare-metal USB bootloader for this chip, but I've managed to fit everything in 2KiB. (Source here) For comparison the official bootloader is nearly 24KiB in size. As a bonus, I've also re-designed the V203 USB stack for ch32fun and sent in a pr :D The PCB is also open source, check out the KiCAD files here: https://github.com/cheyao/comu (kicanvas) I plan on just using them for HID injection and as a quick devboard when I need very few I/O pins (4 main ones, but I've exposed some more via testpoints) (Name and form inspired by the *omu series) submitted by /u/cyao12 [link] [comments]

The UK Semiconductor Centre (UKSC) will lead a delegation of UK semiconductor companies and organizations to SEMICON Taiwan 2026 at TaiNEX in Taipei (2–4 September), reinforcing its role as the gateway to the UK semiconductor ecosystem and strengthening strategic partnerships between the UK and Taiwan...

It’s not uncommon for a midsection to become soft and distended with advancing age. That said, when it happens to a battery, it’s potentially quite problematic.

In last week’s part 1, I took apart a third-party BLX-1 battery which had come with my Olympus (now OM System) OM-1 digital camera and which the manufacturer’s own BCX-1 charger refused to recognize as a valid recharge partner. Also recently augmenting my burgeoning gear inventory are two enthusiast-prized Olympus PEN-F Micro Four Thirds bodies (once again digital, not the film-based precursor), one in each color option offered by the manufacturer a decade ago when they were new.

Each came with a third-party BLN-1 battery (7.6 V, 1220 mAh). Supplier names differed but their physical appearances were identical, therefore suggestive of a common manufacturing source. I’ll be taking them both apart today to test my hypothesis. But why am I dissecting them at all?

Unlike the BLX-1, they seemingly still work fine, but they both arrived slightly swollen, with further distension likely after additional use and recharge cycles. The last thing I want is for an inexpensive, replaceable cell to end up permanently lodged in the battery compartment of an expensive, irreplaceable camera, so retirement and replacement was a priority for both!

Trust me when I say that all the cameras showcased in this two-part series are Micro Four Thirds models, Olympus-now-OM System to boot, is only a coincidence. I’ve had no shortage of mixed-at-best success in the past with third-party batteries for other manufacturers’ cameras, too.

Some Wasabi with your sushi?

I randomly picked the one from Wasabi Power, a common “clone” cell supplier, to disassemble first. As usual, I’ll start with some overview shots, accompanied by a 0.75′′ (19.1 mm) diameter U.S. penny for size comparison purposes. Top.

Bottom.

Four of the BLN-1 contacts—”+”, “-“, “I” and “T”—are marked the same (albeit in different ordering) as with the BLX-1. As I mentioned last time, published specifications for batteries like these are hard-to-impossible to come by, given that for various reasons the camera manufacturer doesn’t want to encourage third-party cloning.

That said, once again the functions of “+” and “-“ are likely related to the applied voltage and current involved in the fundamental cell-charging and -discharging (for camera powering) functions. “I”, typically standing for “information” or “identification”, references the interrogation initially done by both charger and camera after battery insertion and power-on, and ongoing from that point on, presumably implemented by a bidirectional single-data-pin serial communications protocol of some sort.

“T” typically references “temperature”, with the contact connected to an embedded negative temperature coefficient (NTC) thermistor or other sensor that monitors the internal cell(s) and alerts the charger to potential overheating. And this time there’s a fifth electrical contact, “S”. User research suggests that it was added in response to Japanese standards body guideline revisions that mandated a fuller shut-off of the accompanying charger after the battery reported it was “full”, thereby minimizing subsequent “vampire” power draw.

The BLX-1 battery disassembled in part 1 of this series is significantly newer in generation than the BLN-1 and presumably integrates this function along with others already supported over the “I” interface, thereby negating the ongoing need for a dedicated “S” contact.

Onward, redux. Once again, the other end is much less exciting, as are the sides.

Ongoing unexciting-dissection aspirations

And once again, a Sirens-like tempting, albeit ultrasonic-welded, seam around the battery’s circumference seems to be the most feasible pathway inside, the potential for sparks, smoke, flame, and other calamities aside. Danger, Will Robinson!

Phew!

This time, the batteries’ form factors aren’t cylindrical and plastic-covered as before, but rectangular and metallic; niftily-named prismatic, to be exact. Once again throwing caution to the wind, I pressed forward determinedly (albeit cautiously) with the disassembly.

Rubber strips again, this time tape- and paper-accompanied, to insulate the mini-PCB from the batteries’ terminals both mechanically and electrically.

Enough with the teasing; I know this is what you’re most interested in seeing, right?

The design is much more elementary than with the BLX-1 circuit board we saw in part 1. The eight-lead IC PCB-labeled as U2 is stamped as follows on top, below a cryptic company logo.

8822
E6H01

It’s another dual N-channel MOSFET. And then there’s six-lead U1 to its right, marked as follows.

CGKU

As with the BLX-1, per an earlier-referenced discussion, I’m guessing it’s a rudimentary battery-protection IC. Apparently recharge-balancing the two cells isn’t of concern in this specific case.

Speaking of which, let’s take a closer look at the markings on the two cells’ prismatic cases, which you’ve already glimpsed in prior images.

They match each other, and I suspect the last eight characters of each reference a September 2016 manufacturing date. Nearing 10 years old, I’m willing to forgive a bit of old-age swelling, no matter that it obviates any further use (that I’m comfortable taking a chance on, at least). No voltage or capacity specs; that said, I suspect they’re the relatively common 4.2 V (3.7 V nominal) variant in a serial-interconnect topology.

Testing a common-sourcing hypothesis

Now for its Newmowa-branded counterpart (is that a clever company logo, or what?), complete with scribbling on top from its prior owner (who apparently, like me, is also blessed to own a diversity of camera hardware models from various manufacturers, and needs to keep his batteries straight).

Trust me when I say that had I decided to keep the battery in service, cleaning off those contacts would have been my very next step!

Once more unto the breach, dear friends.

This time, interestingly, both cells’ cases are completely marking-free on both sides.

Although the means by which the cells are adhesively bonded both to each other and to the surrounding halves of the enclosure differ, there’s visually obvious commonality with respect to the respective mini-PCB layouts.

That said, the components are seemingly divergent from a sourcing standpoint (albeit functionally identical, at least likely). Here’s what’s atop eight-lead U2 this time:

SNE
5N20V
7H09 (don’t quote me on the accuracy of this last line; it’s pretty fuzzy)

Once again, it’s a dual N-channel power MOSFET. And six-lead IC U1 to its right? Again, don’t quote me definitively, but here’s my best shot post-cleanup with rubbing alcohol.

20DD
L607

And with that, after wrapping up all four cells (two from each of the two batteries) in insulating masking tape to ensure safe storage until after my writeup is published.

I’ll also wrap up for today. Shout out with your thoughts in the comments, please!

—Brian Dipert is the associate editor, as well as a contributing editor, at EDN.

Related Content

• Dissecting third-party camera batteries, part 1: Misbehavior
• Engineering tradeoffs: a camera case study
• Single-battery failures in multi-battery arrangements: diagnosing selective cell derangements

The post Dissecting third-party camera batteries, part 2: Swelling appeared first on EDN.

India’s medical device industry is expected to emerge as a global powerhouse with a projected market size of $250 billion by 2047, according to FICCI-DUA Consulting White Paper on ‘Service and Maintenance of Medical Equipment in Indian Healthcare – Towards a Safe, Reliable and Sustainable Medical Device Maintenance Ecosystem’.

The White Paper released during the inaugural session of the 9th edition of ‘India Medical Device 2026’, organised by the Department of Pharmaceuticals in association with FICCI today says that India’s medical device sector, currently valued at around $14 billion, is projected to reach $30-50 billion within this decade, and likely to reach $250 billion by 2047. It says rising healthcare demand, increased adoption of advanced medical technologies, government support for indigenous manufacturing, and the country’s ambition to become a global MedTech hub likely to drive the rapid growth.

According to the White Paper, India has made significant progress through initiatives such as the Production Linked Incentive (PLI) Scheme and the Strengthening of Medical Devices Industry Scheme, which have enhanced domestic manufacturing capabilities and improved India’s global competitiveness. However, the report stresses that sustained growth of the sector will depend not only on manufacturing but also on creating a world-class ecosystem for servicing, maintenance, calibration and lifecycle management of medical equipment.

The report highlights that medical equipment today forms the backbone of modern healthcare, supporting timely diagnosis, emergency response, surgeries and advanced treatment. It argues that the value of these technologies extends well beyond procurement and depends on reliable servicing throughout their operational lifecycle. Proper maintenance, the report says, improves patient safety, enhances clinical effectiveness, reduces equipment downtime, extends equipment life and optimises healthcare investments.

To address these issues, the White Paper proposes a risk-tiered hybrid maintenance framework anchored in the Central Drugs Standard Control Organisation (CDSCO) device classification system. It recommends maintenance protocols based on device risk categories, creation of a national certification architecture for service engineers, strengthening technical training, encouraging commercial model innovation, and rationalising the fiscal framework to promote compliant maintenance practices. The report also advocates wider adoption of digital technologies, including predictive maintenance, digital monitoring and lifecycle management systems, to improve equipment reliability and minimise downtime.

The post India’s Medical Device Sector Projected to Reach $250 billion by 2047: FICCI-DUA Consulting Report appeared first on ELE Times.

For first-half 2026, deposition equipment maker Aixtron SE of Herzogenrath, near Aachen, Germany has reported revenue of €174.5m, down 30% on first-half 2025’s €249.9m...

The access control industry is rapidly moving to the cloud. The global Access Control as a Service (ACaaS) market is expected to nearly double in size from 2025 to 2029 1 , driven by organizations seeking simpler deployment, centralized management, and lower maintenance costs.

At the same time, they are managing more employees, visitors, and locations than ever before, making access control administration increasingly complex.

This is where cloud access control, also known as ACaaS, comes in.

What is cloud access control

Cloud access control connects devices directly to a cloud platform, allowing administrators to manage access permissions, attendance, and elevator control from a single interface.

Instead of maintaining servers and software infrastructure, organizations can manage users, doors, schedules, and permissions remotely while ensuring the right people access the right places at the right time.

Introducing Hik-Connect Team
Hik-Connect Team is Hikvision’s cloud-based platform, helping organizations have access control through a unified web and mobile experience. It brings the following core benefits.

• No servers required: Connect devices to power and internet, and they’re online and fully operational within minutes. No server, no configuration, no high maintenance costs.
• Remote management: Administrators manage devices and users from wherever they are without relying on VPNs — whether they are at headquarters, a branch office, or working remotely.
• Stable performance: Network outages don’t cause downtime. Edge processing, local storage, and cross-device communication keep doors operational even when connectivity is interrupted.
• Scale as you need: From a single door to an unlimited number of access points, the system grows without friction.
• SMB-ready free capacity*: Hik-Connect Team includes free door and user capacity to meet the needs of SMBs.
• Always up to date: New features and capabilities are released through updates. There’s no extra on-site deployment or maintenance work.
• Unified management with open integration: All three functions — access, attendance, and elevator control — are managed in one place. For organizations that already use third-party payroll or HR platforms, open API support makes integration straightforward.
• Enterprise-grade security: Data privacy and security are not concerns. Hik-Connect Team is built on top-tier cybersecurity infrastructure to protect sensitive data.

Designed for diverse business scenarios

Cloud-based access control is suitable for SMB scenarios:

• Small offices and single-site businesses seeking simple and cost-effective management
• Multi-site offices and chain stores requiring centralized operations
• Residential communities looking for more convenient and secure access experiences

The shift to cloud service

The shift from on-premise to cloud isn’t just a technology trend. It’s a fundamental change in how organizations think about access, operations, and cost. Hik-Connect Team is designed for that shift — flexible enough for a startup, robust enough for a multi-site enterprise, and secure enough for environments where data protection is non-negotiable.

 

The post Why Businesses Are Choosing Cloud Access Control appeared first on ELE Times.

Over the last two months, we mapped out how USB-C, Power Delivery (PD), vehicle-to-load (V2L), and high common-mode transit immunity (CMTI) are reshaping the landscapes of test and measurement and electric vehicles (EVs). The next challenge is practical: how do you translate those high-level architectural requirements into a schematic that works and a PCB layout that passes?

This post delivers the essential design clues—the component choices, layout constraints, and rule-of-thumb practices—that bridge concept to copper. It’s about moving from theory to implementation, giving engineers the confidence to build USB-C and PD systems that meet compliance while surviving real-world stress.

Designing for high CMTI: Turning ratings into real layout rules

To maintain high CMTI on a real board, the isolation barrier is non-negotiable. Specialized digital isolators—either capacitive-based or magnetic-based—are engineered to withstand the brutal transient voltage spikes in the range of kV/𝜇s without corrupting USB data streams. These devices form the shield that keeps common-mode noise from bleeding across domains.

Placement is equally critical: the isolator must straddle a deliberate, wide physical gap on the PCB. That gap is a true keep-out zone; no copper traces, power planes, or ground planes are allowed to cross it. The isolator alone bridges the divide, ensuring that the high-speed USB signals remain intact even under aggressive switching events. This disciplined layout practice is what turns theoretical CMTI ratings into reliable, repeatable board-level immunity.

Figure 1 Application diagram of ISOUSB211 reveals how the isolation barrier prevents data corruption caused by ground loops and power-stage switching noise. Source: Texas Instruments

Implementing USB-C and PD controllers: The schematic clues

Moving from standard USB to USB-C with Power Delivery—and even V2L—requires dedicated silicon. At the simplest level, configuring a USB-C port hinges on the CC pins. If the design is a power sink, such as a basic test and measurement instrument, you must place 5.1 kΩ pull-down resistors (Rd) on both CC1 and CC2 pins.

Conversely, if the design is a source, pull-up resistors (Rp) are required to advertise available current. For higher-power PD or bidirectional V2L applications, engineers should resist the temptation to code the complex negotiation state machines inside a general MCU.

Instead, a standalone USB-PD controller IC is the right choice—it encapsulates the protocol logic, manages the timing, and ensures compliance, freeing the system MCU to focus on application-level tasks. This division of labor is what makes USB-C and PD designs robust and certifiable in practice.

Figure 2 This simplified block diagram of the MAX77958 IC details the USB Type-C CC detection and Power Delivery protocol implementation. Source: Analog Devices

The 90-Ω differential layout: The PCB clues

High-speed USB signaling in USB 3.x and USB4 behaves much more like RF than low-speed digital. If the layout is off, compliance failures are inevitable. The first design clue is impedance control: the D+/D– or TX/RX traces must be routed as a matched differential pair with a strict target of 90 Ω. Deviations here directly translate into eye-diagram collapse and failed certification.

The second clue is geometry for ESD protection. In harsh EV and lab environments, transient voltage suppressor (TVS) diodes must sit physically as close as possible to the USB-C connector pins. The ESD spike must be absorbed at the connector entry point—before it can travel down the trace and reach sensitive silicon. This placement discipline ensures that compliance isn’t just theoretical but survives the real-world surge events that USB-C designs inevitably face.

Figure 3 Hand-drawn illustration of an eye diagram highlights the mask keep-out zone at the center. This stylized ‘open eye’ demonstrates the compliant signal quality expected in USB 2.0 links when the differential pair achieves routing near the 90-Ω target. Source: Author

Tips from the bench: What datasheets don’t mention

While mapping out your schematic and tracking your traces, keep these three notorious real-world layout traps in mind. They are the most common culprits behind first-revision PCB failures:

• Guard the CC pins against high-voltage shorts

Inside the microscopic geometry of a USB-C receptacle, the Configuration Channel (CC) pins sit directly adjacent to the high-voltage VBUS power pins. A slightly tilted cable insertion, a worn-out connector, or a bit of metallic debris can instantly short a 20-V VBUS line straight into a CC pin. Standard 3.3-V or 5 V-MCU inputs will instantly fry.

The fix: Always specify standalone USB-PD controllers featuring integrated 24 V short-to-VBUS protection on the CC lines.

• Tame the VBUS hot-plug voltage ringing

When a user hot-plugs a live Power Delivery adapter into your board, the parasitic inductance of the USB-C cable slams into the input capacitance of your PCB. This creates an LC circuit that can ring up to twice the nominal voltage, turning a standard 20-V PD profile into a destructive 40-V spike that easily ruptures downstream buck regulators.

The fix: Anchor the VBUS entry point with a heavy-duty, high-voltage TVS diode or an over-voltage protection (OVP) eFuse paired with a minimum of 10 uF of bulk ceramic capacitance to dampen the surge.

• Ban via stubs on your 90-Ω pairs

Achieving a strict 90 Ω target impedance requires flawless trace geometry. Every time a high-speed TX/RX or D+/D- pair hops between PCB layers through a via, it hits an impedance speed bump. Worse yet, if a trace transitions from the top layer to a middle layer, the remaining unused barrel of the via hangs off the signal path like an antenna. This “via stub” creates severe RF reflections that can collapse your eye diagram entirely.

The fix: Route high-speed USB lines on a single layer whenever possible. If layer transitions are absolutely non-negotiable, limit them to a maximum of two, place adjacent ground return vias right next to them to preserve the return path, and enforce back-drilling on multi-layer boards to eliminate the stubs.

This bench-level awareness is what keeps your first spin from becoming a costly lesson in overlooked physics.

Closing 3-month power and signal loop

Month 1 and month 2 set the destination, showing how USB-C, Power Delivery, V2L, and high CMTI are reshaping test and measurement and EV platforms. Month 3 provided the map: the schematic clues, resistor choices, isolation gaps, and PCB layout rules that turn concepts into copper.

The takeaway is clear: these design rules tie the journey together, moving from vision to verified hardware. By closing the loop with practical guidance, engineers are equipped not just to understand USB-C and PD, but to implement them with confidence in real boards and systems.

Carry these power and signal rules into your next design cycle; apply the resistor networks, enforce the isolation gaps, and route those 90-Ω pairs with precision. Share your own board-level lessons with peers and keep expanding the collective toolkit that transforms ambitious USB-C and PD concepts into reliable, compliant hardware.

T. K. Hareendran is a self-taught electronics enthusiast with a strong passion for innovative circuit design and hands-on technology. He develops both experimental and practical electronic projects, documenting and sharing his work to support fellow tinkerers and learners. Beyond the workbench, he dedicates time to technical writing and hardware evaluations to contribute meaningfully to the maker community.

Related Content

• USB Keypad Reference Design
• USB Proves Ready for T&M Tasks
• Top 10 innovative USBs and peripherals
• Take off with Simplified USB Type-C Development
• The USB takeover: Why modern T&M is moving to your pocket
• A quick and practical view of USB Power Delivery (USB-PD) design

The post Component and layout rules for USB-C, PD, and CMTI appeared first on EDN.