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If you periodically need to see the frequency response of a circuit, this easy, inexpensive project can help you out.

Editor’s note: This is a two-part series on how to create a noise generator with an adjustable bandwidth and a consistent amplitude. The previous entry: 

• Making noise with a BANG, part 1: Concept and hardware

The operation and firmware

As I mentioned last time, I was able to reuse much of the firmware from a previous Design Idea project. The Arduino C code consists of three files. One is the initialization code for the DAC, while another contains code for the LCD/touch screen operations. The third is the main code. Let’s look at these one at a time.

Wow the engineering world with your unique design: Design Ideas Submission Guide

The DAC initialization code does just what it says and is designed to get a DAC output as fast as possible. The LCD/touch screen code is the largest piece of the software puzzle. Before discussing it “under the hood”, let’s take a quick look at the some of the LCD/touch screen display outputs. Figure 1 shows most of the screens used in the BANG.

Figure 1 The BANG LCD screens are designed to be both intuitive and informative.

The first screen you see after the power-up splash screen is what I call the main screen. It allows you to select an output, but let’s hold off discussing this implementation aspect in detail until later. For now, just understand that on power-up, it will default to the noise output on the AC and DC BNC connectors.

Also on the main screen is the “Change Bandwidth” selection that will allow you to set the bandwidth for the noise (noise bandwidth is measured from 0 Hz). When you press “Change Bandwidth”, the screen will change to the keypad and allow you to enter your desired number. Note that if you exceed the maximum 225 kHz it will default to 225 kHz. Similarly, if you enter a number less than the minimum of 500 Hz it will default to 500 Hz. After hitting “ENTER” you will return to the main screen.

On the main screen, selecting “About” will take you to a screen showing lots of interesting information such as your selected bandwidth and the gain it will apply to the noise during filtering. You’ll also see the sample rate (which is fixed), firmware version, and (for those that are interested) your current IIR filter’s coefficients. Next, it shows the battery voltage and charge level. (If you do not have a battery installed you may see fully charged numbers as it is instead reporting the charger voltage. There is a #define in the top portion of the main code that you can set to “false” instead, in which case this line won’t be displayed if you don’t have a battery installed.) The last item shown is the incoming USB voltage.

The last screen shown in Figure 1 is the one displayed when “RUN” is selected on the main screen. If you see this screen, the noise signal is being generated and is being output to the BNC connectors.

Let’s talk a little about the code for creating these screens. It’s a bit long and mostly involves setting colors, drawing boxes, selecting fonts, aligning text in the box, and capturing positions of key presses. Almost all of this is done using higher level calls to the downloadable “Adafruit GFX Graphics Library”. Here’s a short example of the code showing how to display the word “BANG” in red against a grey background:

tft.fillScreen(tft.color565(0xe0, 0xe0, 0xe0)); // Grey tft.setFont(&FreeSansBoldOblique50pt7b); tft.setTextColor(ILI9341_RED); tft.setTextSize(1); tft.setCursor(13, 100); tft.print("BANG");

The third C file is the main code, which mostly directs calls to the correct LCD screen, executes miscellaneous housekeeping operations, and (of course) generates the noise signal, the latter starting with the bandwidth selected from the touchscreen. Using this value, we generate the coefficients for a digital 2-pole low-pass Butterworth IIR filter. The next step is to get a value for the gain we will be using on the noise signal. This is done by calling a function that has the bandwidth as an input and returns a gain number. Here is the code for that function:

//****************************************************** // AGC * // Does an automatic gain adjust to the * // random number amplitude. Run once after * // startup or a change in the LP filter. * //****************************************************** float AGC(float cutoff_freq) { float agcGain = 1; // Calculate agc gain based on the set bandwidth if (cutoff_freq >= 50000) agcGain = 31.0 * pow(cutoff_freq, -0.292); // for 225kHz to 50kHz else agcGain = 393.769851 * pow((cutoff_freq - 97.8961702), -0.524598029); // Curve fit of freq vs. amplitude data gainOffset = 1024.0f * (2.0f - agcGain); // Adjustment for shift in DC level return agcGain; }

You’ll see that there are two different formulas used for agcGain, based on whether the bandwidth selected is greater than 50 kHz. This dual-equation method makes curve fitting more accurate. These formulas were derived from data I generated by setting a bandwidth and then adjusting the gain in code to get a desired amplitude. The data was then used to generate curve-fitted equations (kudos to Standards Applied Engineering Tools, whose Curve Fitting Online utility gave by far the most accurate curve fit of all the tools I found and tried). Later, I’ll also detail how AI did (or, maybe more accurately, didn’t) with generating the same curve fit equation(s).

You can see from the second equation that the power function is based on -0.52; roughly the square root of 2 as we talked about at the beginning of part 1 of this series. The reason it is not exactly a square root of 2 function is because some noise, beyond the cutoff frequency of the 2-pole digital IIR filter, still exists in this roll-off portion of the filtered signal – i.e., it is not a brick wall filter.

Figure 2 shows a graph of this gain vs. bandwidth selected.

Figure 2 This graph shows the linear gain vs. bandwidth result for the equations used in this design.

With the bandwidth entered and the gain calculated, it is then incorporated into the coefficients of the lowpass IIR filter. This approach optimizes the calculations; we don’t need to add another multiplier inside the speed-optimized output loop.

Ok: we’re now ready to generate the noise signal. When the user selects “RUN”, the code enters a tight loop. In it, we get a random number from the true random number generator (TRNG). Next, we run the number through the IIR filter, which also applies the gain. Then, the lower 12 bits of this number are sent out of the DAC. (A note: the DAC has a slew rate of somewhere around 1 µS per volt to minimize the effect. The number is scaled to keep the signal mean coming from the DAC to around 1/2 Vcc.) This loop continues until the user selects “STOP”.

Those of you following closely may be thinking something along the lines of the following right now: “Another way to generate a noise signal of a given amplitude is to simply generate the random samples at a lower sample rate”. The downside of this alternative approach is that the analog reconstruction filter would need to be adjusted to follow the sample rate, which seems like a much more difficult analog design task. Also, we would still need to perform the digital low-pass filtering for anti-aliasing.

It’s time to look at the output of the BANG. Figure 3’s scope display shows the AC output time domain signal on the left and the FFT on the right. The BANG is set to give an output with a 25 kHz bandwidth.

Figure 3 This scope plot shows the BANG output with a 25 kHz bandwidth setting.

The enclosure

The BANG’s enclosure derives from a custom 3D-printable model (see later for a file-download link). It includes three parts: the main body, the base/PCB mount, and a stylus for the touchscreen. The main body’s download is modeled with two filament colors but can alternatively be printed in one color. If printed in a single color, the text is still readable, as it is also embossed. The base holds a 120 mm x 80 mm PCB. I used a protoboard as there were a minimal number of parts and was faster to build than designing and waiting for a custom PCB.

Wait, there’s more

While TRNGs are common in larger processors, they’re more rare in smaller micros. Most compilers therefore use pseudo-random number generators instead. But since this system was generating 32-bit true random numbers, it occurred to me that such a data stream may also have other uses, such as in cryptography systems, input data for testing code, a “seed” for pseudo-random number generators, or even helping you select “picks” for playing the lottery.

More broadly, it seemed like a waste to not have a way to output these generated numbers. So, I included support for this feature, via USB, in two format options – ASCII data or binary data. The desired format can be chosen from the “Select Output” LCD page shown in Figure 4 (as mentioned earlier, the power-up default is the noise generator output via the analog BNC connectors).

Figure 4 The design includes support for outputting the 32-bit true random numbers generated, over USB and in two format options.

Note that although the data is 32 bits, it can be sliced or appended to form any size random number you require. For example, you can use one bit of the 32-bit source, which will still be random, or you can append two 32-bit output numbers to create a truly random 64-bit number.

Comments on AI use

I only used AI (and then only experimentally) for one part of the project, the curve fitting of test data to create the equation(s) for the AGC. The result was…interesting. I’d already developed the earlier discussed frequency-to-gain equations for the AGC algorithm, but I thought I should also try AI to see what it came up with. I fired up Microsoft Copilot and gave it the frequency vs gain data that I’d already created by iteratively setting a frequency and then adjusting gain in the code until I got the fixed amplitude I was looking for.

Copilot noted that it looked like a power equation – good. Then it gave me a very simple equation: gain = 1.96 * freq-0.52 . Wow, I thought, much simpler than the equations I’d came up with. But it seemed too good to be true, so I got out a calculator. At a frequency of 10 kHz the gain should be around 3. When you make the calculation on the AI’s formula you get around 0.016. When I asked Copilot to use its equation on 10 kHz, it said the gain would be 3.68. Another AI with a case of cognitive dissonance. Perhaps obviously, I used the other formula instead!

Conclusion

This is a fairly easy and inexpensive project to build. If you periodically have the need to see the frequency response of a circuit, it may help you out.

Note that the schematic, code, 3D print files, Arduino software, links related to various parts of the project, and additional notes and pictures on the project’s design and construction can be downloaded for free at the MakerWorld website.

Damian Bonicatto is a consulting engineer with decades of experience in embedded hardware, firmware, and system design. He holds over 30 patents.

Phoenix Bonicatto is a freelance writer.

Related Content

• Making noise with a BANG, part 1: Concept and hardware
• A digital filter system (DFS), Part 1
• A digital filter system (DFS), Part 2

The post Making noise with a BANG, part 2: Software, integration and operating results appeared first on EDN.

At the beginning of July, epiwafer and substrate maker IQE plc of Cardiff, Wales, UK appointed Robert Dennehy and David O’Carroll as non-executive directors, representative of MACOM Technology Solutions Inc of Lowell, MA, USA under the board appointment agreement between the two firms announced on 28 May. MACOM has a beneficial interest in IQE, representing 11.5% of IQE’s issued share capital...

Epiwafer and substrate maker IQE plc of Cardiff, Wales, UK has secured a multi-year production order worth $14m from a strategic global technology customer...

Conflicting application requirements can turn system-on-chip (SoC) design into a hall of mirrors. In particular, choosing a process technology can become a maze of contradictions and puzzles.

Then there is higher speed, which generally requires more power. Next, the technology that delivers the necessary performance and power efficiency may be unacceptable due to cost or supply-chain constraints.

However, a design partner who can customize foundational IP—logic cell libraries or memories—and shepherd the custom cells through the design flow, manufacturing, and testing can often bring an SoC design safely through the maze.

One recent engagement with a crypto-mining client illustrates the importance of custom foundational IP in resolving these trade-offs. And it also shows how the impact of custom cells can ripple through the design flow, from tape-out and beyond, emphasizing the need for a design partner with expertise in both IP creation and SoC implementation.

A unique application

Crypto mining is the process of generating new coins in a cryptocurrency. For many such currencies, including the ubiquitous Bitcoin, the process requires a so-called proof-of-effort: a computationally intensive task with no known shortcut.

Factoring a huge number is an example: the only way to find the prime factors is to keep trying new prime numbers. In principle, the cryptocurrency’s governors would publish a large number, the crypto miners would set to work searching for factors, and the first miner to publish all the factors would receive a new coin.

Obviously—luck aside—the miners with the most computing power will get the most coins. That leads to a computing arms race. Less obviously, this game consumes a tremendous amount of energy—one reason China attempted to ban crypto mining in 2021. To make the enterprise profitable, the miners need to stay on the leading edge of computing performance while minimizing capital investment and operating costs. These costs are dominated by power consumption.

Under those pressures, crypto miners quickly migrated from farms of CPU-based server boards to FPGAs, and then to vast arrays of ASIC hardware. Today, miners demand high computing performance, very low power consumption, very low front-end investment, and low unit cost—a set of contradictory requirements.

The mining SoC

This was the scenario presented to us by our crypto-mining client. Together, we determined that the lowest-cost approach that met their performance and power requirements would be a FinFET process with an extremely low operating voltage.

In fact, we had fully characterized 0.5-V logic libraries for this process. There was just one problem. The library could not meet the client’s speed requirements. The problem, it turned out, was the registers. This library, like virtually all standard logic libraries, uses a conventional master-slave D-type flip-flop. But it could not operate reliably at the required clock frequency. So, we decided to create a custom D-type flip-flop cell.

The D flip-flop

The D-type flip-flop has been a fundamental element in digital design for decades, used for everything from state machines to registers (Figure 1).

Figure 1 Schematic highlights a 32-bit D-flip-flop used to implement D-type registers. Source: Faraday Technology

The cell’s performance and stability are vital to any RTL design. The conventional cell design uses two stages and two clock phases. The first stage captures the input data on one clock edge, and the second stage latches the captured data on the second clock edge. In most designs, this requires routing two very accurately timed clock phases to every flip-flop cell.

We believed we could eliminate one of these clock signals and achieve a higher operating speed. Eliminating one clock would also substantially reduce the cell’s power dissipation and could reduce area and routing congestion.

But could we accomplish this, and hit the required frequency? And could we do all that while sacrificing the inherent stability of the dual-phase clock approach and still have a device that is resistant to process variations and electrical upset?

The TSPC flip-flop

Our exploration of circuit designs led to the development of the true single-phase clock (TSPC) D-type flip-flop (Figure 2).

Figure 2 Schematic of a traditional positive-edge triggered TSPC flip-flop showing how a TSPC flip-flop would meet the customer’s power requirements. Our proposed circuit design allowed the TSPC flip-flop to also operate over the necessary frequency range. Source: Faraday Technology

However, circuit design and proof of concept were just the beginning. We fully simulated the circuit in SPICE to understand the layout and sensitivities of this novel cell. We needed to characterize the TSPC flip-flop not only in isolation but also in a dense layout surrounded by other cells, under marginal, noisy clocks, and process variations. At last, we reached our goals for both performance and reliability.

The SoC design using our TSPC flip-flop met our crypto-mining client’s speed requirements. The cell also achieved a 40% reduction in power at rated speed compared to the conventional D-type flip-flop cell it replaced. It reduced the area by about 7%. And from a functional perspective, the TSPC cell was simply a normal D-type flip-flop.

But our detailed characterization of the cell revealed differences in the new device’s operating characteristics. These differences would influence the implementation flow for the SoC.

The cell in use

One unique characteristic of the TSPC cell influences front-end design, specifically power management planning. The single-phase clock for the TSPC flip-flop must not stop during operation, or the flip-flop state may be lost. This places significant limits on the use of power-management techniques such as clock gating and clock throttling. A design that interrupts the register clock must tolerate an unpredictable state when the clock resumes.

Other special characteristics of the cell further influence downstream design. For example, the cell is quite sensitive to clock signal integrity. This requires careful, skilled planning of clock networks from the outset and equally careful routing of clock trees. Conventional clock-tree synthesis tools may not deliver the necessary signal quality across all flip-flop instances, resulting in unreliable operation.

The cell is also sensitive to process variations, even at a local level. This issue can impact yield, but it can be overcome by careful placement during logic layout. We generally use manual insertion to instantiate the TSPC cells, as we have found them unsuitable for use with synthesis tools. Once the cells are placed, routing constraints are relatively minimal. The foremost issue is to maintain signal integrity on the clock lines.

Timing analysis is straightforward, of course, using the TSPC cell’s timing data. Signoff is also conventional—with the enhanced attention to clock integrity. Thanks to our exhaustive characterization and refinement of the cell design, there are no special process corners to be investigated. During test, some changes to the test vectors may be helpful to inspect the unique behavior of the cells.

A new degree of freedom

SoC designers are used to trading off power, speed, and process to meet design requirements. But sometimes no setting of these knobs will achieve the desired result. Our crypto-mining client faced this challenge: running an affordable, available FinFET process at 0.5 V would achieve all design goals except maximum speed. But consuming more power or moving to a more advanced process node in exchange for more speed was not an acceptable trade-off.

The solution was to move outside the power-performance process box with customized foundational logic. Faraday determined that we could meet the client’s needs with only one custom cell—a novel D-type flip-flop design. But once characterized, we found that the cell would place significant demands on the implementation team, from power planning through test design (Figure 3).

Figure 3 To reduce power consumption, we used a TSPC circuit to replace a master-slave flip-flop; but TSPC has an operating frequency limit, so we proposed a solution to this limitation. Source: Faraday Technology

The TSPC flip-flop thus could have become only academic exercise. However, it became an out of the box solution here. Today, the crypto-mining SoC is in volume production and meets all design requirements. The chips are out there, searching for coins and earning their living.

Jason Kang is director of IP technology at Faraday Technology. He has over 20 years of experience in fundamental IP development, PDK integration, and IP model characterization. His expertise lies at the intersection of advanced-node design flows, device modeling, and EDA methodologies, with a strategic focus on silicon implementation and the emerging field of AI-driven design automation.

Related Content

• Bitcoin ASIC in Chips-to-$ Race
• Design Houses Bank on AI, Bitcoin
• Crypto Mining ASIC Goes Deep Sub-Threshold On 3 nm

The post Crypto mining SoC unearths a need for custom IP appeared first on EDN.

The Indian Army has initiated the process to acquire indigenous long-range, one-way attack drones capable of striking targets up to 1,000 km away, as it looks to strengthen its deep-strike capabilities with AI-enabled systems. The procurement is being pursued under the Long Range Loiter Munition (LRLM) programme through the Make-II route of the defence acquisition policy.

The procurement is being pursued under the Long Range Loiter Munition (LRLM) programme through the Make-II route of the defence acquisition policy. The Army is looking for drones that can accurately engage targets at a range of 1,000 km, operate in GPS-denied environments and feature artificial intelligence-enabled targeting capabilities. The platform should be capable of carrying a 25-kg warhead with a 50-metre kill radius, fly at altitudes above 5,000 metres and achieve speeds of at least 400 kmph.

Under this framework, private companies will fund their own research and development, while the Army will procure the systems if they meet the required technical specifications. While the exact order size has not been finalised, the armed forces are expected to require thousands of one-way attack drones across different operational ranges.

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India has launched an ambitious programme to build indigenous high-altitude airships capable of conducting long-duration surveillance and intelligence-gathering missions, with several private companies expected to compete for the project. The project is being executed under the government’s Make-I procurement framework, which allows the Centre to fund up to 70% of research and development costs for selected industry partners.

The project is being executed under the government’s Make-I procurement framework, which allows the Centre to fund up to 70 percent of research and development costs for selected industry partners. As per The Economic Times, the Defence Acquisition Council (DAC) approved the programme in February, with the overall project estimated to cost around Rs 15,000 crore, including prototype development and procurement of multiple systems.

The proposed airships are expected to remain airborne for months at a time, enabling persistent intelligence, surveillance and reconnaissance (ISR) operations. The Indian Air Force’s Directorate of Operations (Remote) is overseeing the initiative and aims to develop Air Ship-based High Altitude Pseudo Satellites (AS-HAPS). The platforms are expected to operate at altitudes exceeding 20 kilometres, carrying advanced payloads for optical surveillance, electronic intelligence (ELINT) and long-range communications.

Alongside the airship initiative, the Defence Ministry is also pursuing the development of fixed-wing High Altitude Pseudo Satellites that can take off conventionally and undertake extended surveillance missions.

The post India Launches Rs 15,000 Crore Project to Build Indigenous Stratospheric Airships for High-Altitude Surveillance appeared first on ELE Times.

Continuing its aggressive order book expansion, Bharat Electronics Limited (BEL) has secured fresh contracts worth Rs 572 Crore. This order outlines BEL’s sustained order inflow. The Rs 572 Crore win highlights BEL’s dominance in the domestic defense electronics segment. This announcement highlights BEL’s strategic alignment with the country’s defense roadmap.

BEL remains a primary beneficiary of the ‘Atmanirbhar Bharat’ initiative in the defense sector. The dual triggers of steady order inflow and an upcoming earnings report place the defence PSU in a critical watch zone for institutional and retail investors alike. This multi-crore order effectively underscores the consistent demand for its core products.

BEL’s ability to secure mid-sized orders consistently outside of major multi-billion-dollar platform contracts is a testament to its diversified electronics portfolio. While the market often focuses on mega-orders, these recurring sub-Rs 1,000 Crore wins provide high-margin stability. We view the timing of this order—just two weeks before earnings—as a positive sentiment booster, though the core focus remains on execution efficiency which will be detailed in the Q1 disclosures.

The Indian defense electronics market is evolving from basic radio communication to advanced electronic warfare and radar systems. BEL, as a dominant PSU, holds nearly 60% of the market share in electronics for the tri-services. Competitors from the private sector are emerging, but BEL’s manufacturing scale and R&D integration with DRDO provide a significant moat.

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Випускниця ФМФ Олександра Парій: "Фізика навчила мене не боятися складних систем" kpi вт, 07/14/2026 - 12:00

In a bid to create India’s first backward-integrated private-sector capability of its kind, Adani Defence & Aerospace, the defence and aerospace arm of Adani Enterprises Limited (AEL) has announced a defence infrastructure project worth Rs 2,500 crore to establish South Asia’s largest missile manufacturing plant in Shivpuri, Madhya Pradesh. This project will design and develop an advanced missile ecosystem with composite propellant and Trinitrotoluene (TNT) production at a single location.

Strengthening India’s defence manufacturing ambitions and the vision of Aatmanirbhar Bharat, this project marks one of the most significant private investments in India’s defence sector. It will enhance India’s capabilities in missile production, advanced weapon systems, precision-guided munitions, and defence technologies.

The facility will strengthen India’s indigenous missile capabilities, supporting the operational requirements of the Indian Armed Forces while advancing long-term defence preparedness. It is slated to accelerate the transition of DRDO-developed indigenous missile systems from successful trials to serial production.

The investment is predicted to generate 5,000 direct and indirect skilled jobs in India, providing employment opportunities across different areas such as engineering, quality assurance, logistics, testing, maintenance, and support services. Beyond employment, the investment is likely to accelerate the supply of precision engineering products, electronic components, advanced materials, tooling, software, and testing equipment.

Since 2020, Adani Defence & Aerospace has developed a robust small arms ecosystem in Gwalior, improving the state’s contribution to India’s defence manufacturing capabilities. From this manufacturing facility, weaponry like pistols, light machine guns, carbines, assault rifles, and other advanced small arms systems are being supplied to the Indian Armed Forces. Backed by the support and guidance of the state government, the Gwalior complex has emerged as a key pillar in India’s drive for self-reliance in defence production.

This announced project under defence will combine advanced manufacturing technologies, automated production systems and globally benchmarked safety standards to support multiple missile programmes simultaneously. Designed to meet the requirements of the Indian Armed Forces as well as trusted international partners, it will strengthen India’s strategic defence industrial capabilities while reinforcing the country’s position as a reliable supplier of precision-guided munitions.

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Інтелект молоді. Раціональне природокористування та новітні енергоефективні технології Інформація КП вт, 07/14/2026 - 11:04

29-й випуск офіцерів ІСЗЗІ КПІ ім.Ігоря Сікорського kpi вт, 07/14/2026 - 11:04

Texas Instruments (TI) (Nasdaq: TXN) today introduced the industry’s
highest-cell-count battery monitor with an integrated electrochemical impedance spectroscopy
(EIS) engine, bringing predictive intelligence, comprehensive data and real-time diagnostics to
battery monitoring in electric vehicles (EV) and energy storage system (ESS) applications.
The BQ79826Z-Q1 battery monitor enhances safety and extends battery life by detecting
potential failures from within battery cells. The single chip delivers the highest-cell-count
monitoring in its class, tracking up to 44% more channels than previous generations. With this
increase in channels, the device significantly decreases the number of components required in a
battery pack, reducing system complexity and cost without compromising reliability. TI is
showcasing this innovation at the 2026 Power Conversion, Intelligent Motion Expo and
Conference (PCIM), June 9-11, in Nuremberg, Germany.

“The electrification of transportation and the rapid expansion of energy storage are redefining
what battery performance must deliver, and as a leader in battery management technology, TI is
uniquely positioned to meet that challenge,” said Wenjia Liu, vice president and general
manager, battery management systems (BMS) at TI. “Our high-cell-count battery monitor with a
built-in EIS engine helps ‘shine a light’ inside battery cells, delivering rich chemical-state data
that enables systems’ software to make informed, real-time decisions on safety and performance
of the battery pack, allowing engineers to address the most critical challenges in battery
management.”

Delivering safety and performance with EIS technology
Just as an electrocardiogram (EKG) monitors the heart, EIS monitors a battery. It delivers
continuous, real-time insight that reveals the battery’s health and warns of issues before they
become critical. Integrated EIS technology enables the BQ78926Z-Q1 to detect fault conditions
earlier – from inside the cells – helping maintain safety and notifying passengers of potential
vehicle hazards such as thermal runaway.

These same benefits extend to ESSs, where reliable battery monitoring is critical to meeting the
growing power demands of artificial intelligence data centers. As effective storage solutions
become increasingly vital in the grid-to-gate ecosystem, EIS gives engineers real-time visibility
into the state of charge and state of health of each battery cell, regardless of system size.

Maximizing efficiency with industry-leading cell count
The performance of an EV or ESS is fundamentally affected by the quality and efficiency of its
batteries. The BQ79826Z-Q1 supports up to 26 cells per device, eight more than any competing
solution, setting a new industry standard. Fewer monitoring devices means a lower bill of
materials, simplified architecture and reduced board space requirements, translating to
meaningful cost savings per channel without sacrificing quality or reliability.
When paired with the BQ79881-Q1 pack monitor and optional TI communications bridge, these
devices create a powerful chipset that works across different module sizes, battery chemistries
and mechanical designs, giving engineers the flexibility to design once and deploy everywhere.
This scalability reduces engineering overhead and accelerates time to market for automotive and
energy storage designers.

Calculating charge readings with the best-in-class accuracy
With a voltage accuracy of <2mV across a full temperature range of –40°C to +125°C, higher
resolution analog-to-digital converters and ultra-low noise, the BQ78926Z-Q1 enables more
accurate state-of-charge calculations, directly addressing one of the biggest concerns for EV
drivers: range anxiety. Utilizing EIS technology, this device enables more accurate temperature
and state-of-charge estimation, helping designers achieve longer battery life and faster charging
without compromising battery health. With an EIS measurement time that is five times faster
than previous solutions, this device delivers the highest functional safety voltage reading per cell.
Compliance with Automotive Safety Integrity Level D and International Organization for Standardization 26262 gives designers a smarter, more efficient path to safer, longer-lasting
batteries.

Innovating what’s next in power at PCIM 2026
Visitors to PCIM can see new products and solutions from TI that are enabling engineers to
innovate what’s next in power in Hall 7, Booth No. 652. The new BQ79826Z-Q1 battery monitor
will be featured in an EIS-enabled BMS reference design, alongside other innovations such as an
11kW single-stage bidirectional onboard charger, a 50kVA solid-state transformer cell stack with
Ethernet and Fast Serial Interface communication and short-circuit protection for silicon carbide
power metal-oxide semiconductor field-effect transistors with technology from Flex.

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Infineon Technologies AG (FSE: IFX / OTCQX: IFNNY) and
LS ELECTRIC have signed a Memorandum of Understanding (MoU) to collaborate on high-
efficiency direct current (DC) power infrastructure solutions for AI data centers and next-
generation power grids.

Rapid advancements in AI, the resulting increase in data center power demand and the
expansion of digital infrastructure are driving the need for efficient power distribution
technologies. At the same time, power grids are evolving into increasingly complex,
distributed networks, accelerating the adoption of DC-based power systems. Accordingly,
the two companies will collaborate on key technologies to enhance energy efficiency,
system performance and scalability in next-generation power infrastructure.

“The increasing electricity demand, especially from AI data centers, is reshaping the way
power is generated, distributed and consumed," said Andreas Weisl, Executive Vice
President and Chief Sales Officer of Industrial & Infrastructure at Infineon. "High-efficiency
DC architectures will play a key role in addressing increased energy demand while
improving overall system performance and sustainability. By combining Infineon's
semiconductor expertise with LS ELECTRIC's strength in system integration, we are well
positioned to accelerate the development and deployment of next-generation DC power
infrastructure.”

“The importance of high-efficiency DC power technologies is growing more than ever with
the expansion of AI data centers and next-generation power grids," said Kil Young Ahn, Vice
President and Head of Production and R&BD at LS ELECTRIC. "Through our collaboration
with Infineon, which possesses worldwide-leading power semiconductor technologies, we will strengthen our competitiveness in core DC power infrastructure solutions and will evolve
into a total solutions provider leading the global AI data center market and future power
markets.”

The collaboration will focus on key DC infrastructure areas, including power conversion
systems for energy storage systems, solid-state transformers (SSTs) and solid-state circuit
breakers (SSCBs). SSTs are advanced, semiconductor-based power conversion devices
that can be up to 30 percent 1 smaller and lighter while offering higher efficiency compared to
conventional copper and iron-based transformers. SSCBs use semiconductors and smart
algorithms to protect electrical circuits from damage caused by short circuits or overloads.
They interrupt the flow of current and operate on the microsecond scale to improve system
stability and protection. These semiconductor-based solutions are becoming increasingly
important in high-density power environments such as AI data centers. The collaboration
aims to improve power and voltage conversion efficiency while enhancing the stability and
reliability of next-generation DC power systems.

Under the provisions of the MoU, Infineon will support the development of high-efficiency,
high-performance DC power infrastructure systems with its broad semiconductor portfolio
that includes power semiconductors, microcontrollers and power control solutions. LS
ELECTRIC will leverage its expertise in power systems and industrial automation to drive
system-level integration and implementation. Together, the two companies will align
technology roadmaps and advance co-development efforts to capture growth opportunities
in the next-generation energy infrastructure market.

The post Infineon and LS ELECTRIC collaborate to advance high- efficiency direct current power solutions for AI data centers appeared first on ELE Times.

📢 Стартував прийом заявок на XV Конкурс стартапів «Sikorsky Challenge 2026»! kpi пн, 07/13/2026 - 17:05

💎 Фізико-математичний факультет КПІ ім. Ігоря Сікорського запрошує на AI SkyRun Hackathon kpi пн, 07/13/2026 - 16:22

Whether it actually accomplishes the function intended (or at least asserted), the low price tag and enduring controversy sufficed to motivate a look inside.

Electronic pest control devices have a longstanding reputation (largely-to-completely justified, my own research of others’ studies has concluded) for being ineffective at encouraging mice and other rodents, along with a variety of insects and arachnids, to flee in their actively broadcasting presence. Sometimes it’s because they don’t work at all; the speaker inside might be a flat-out “dummy”, or at minimum nonfunctional over the claimed operating frequency range, for example (all conveniently obscured by the fact that you’re not supposed to be able to hear them anyway). And even when working as designed, there’s little to no evidence that ultrasonic pummeling does anything meaningful to deter pests, particularly after long-term use.

That all said, a teardown video from fellow teardown-er “Big Clive” that I recently came across still piqued my interest.

Clive, like me, made no definitive judgement as to the functional viability of the device, while still noting the overall skepticism derived by studies from others. That said, observations such as the following would, I felt, be unexpected in a product solely intended as a scam:

The PCB in this unit looks very competently designed, with good clearances and logical design. The bulk of the unit’s magic is in the software, and they’ve been quite clever in creating a swept ultrasonic output, while also pulse width modulating the indicator LED. It could even be said that the programmer may have been showboating.

So, when I subsequently came across a set of six ultrasonic pest repellers selling for $14.99 total, I couldn’t resist (nor could others, apparently, as inventory eventually sold out). They’re AC-powered, and each unit is claimed to cover up to 1,600 square feet. I’ll start with some “stock” shots, several of which include “creative” grammar and spelling terms. Can you spot them?

Dual smart chip? Inquiring minds want to know.

I’m not going to proactively point out all of the “creative” English language examples in these, to avoid ruining your investigatory fun, but “Desinsectisation” is just…awesome.

A half dozen for a bit more than a dozen (dollars)

Now for some real-life shots, as usual beginning with the outer box, also as usual accompanied by a 0.75″ (19.1 mm) diameter U.S. penny for size comparison purposes:

I couldn’t resist:

Now let’s peer inside:

Remove one of the still-wrapped devices:

and the sliver of literature below them comes into view:

which, of course, I promptly tore while getting it out:

English on one side I’d expected. German on the other? Unexpected.

Here’s our now-“unclothed” patient:

When I first glanced at the screw heads on the back side, their seeming deviation had me wondering whether this was some sort of crude intrusion-prevention security scheme.

Turns out the bottom one had just come into my possession already partially stripped:

And have you yet noticed a curious omission both from the outer packaging and the device itself? Ponder for a bit…I’m not going anywhere…

…time’s up! Although there’s a FCC logo on the back of the box, there’s no actual FCC certification ID to be found anywhere. Even though…y’know…it’s a broadcast device. Anyhoo, onward:

Let’s plug ‘er in before taking ‘er apart. Thar she glows, just like in the stock photos:

For what it’s worth, my Collie seemingly wasn’t phased in the slightest by the supposed ultrasonic broadcast!

Getting to the guts

And now let’s dive inside:

Here’s the supposed ultrasonic-frequency transducer:

and the diminutive PCB:

See that screw, identical to the other two you’ve already seen, at the bottom? Interestingly, at least to me, there’s another screw hole, this one unpopulated, above the PCB. Apparently, the chassis was designed for multiple PCB variants, including one larger than this one. Regardless, removing the screw led to subsequent easy removal of the PCB itself.

Leaving nothing particularly exciting behind.

Let’s start with the PCB front side, which you’ve already seen in several past photos:

There are indeed two main ICs here, to the earlier “dual chip” reference, although still stretching the association. The upper four-lead one, toward the left side of the photo, is faintly marked “MB6F” and appears to be a bridge rectifier, with the “BD1” PCB mark presumably standing for “bridge diode” (not, in this case at least, ferrite bead). Its presumed-by-me function, as we’ve seen before, is to act as a crude AC/DC converter in conjunction with a yet-to-be-seen low pass filter (capacitor).

The other IC, labeled U1, eight-lead and below and to the right of its companion, is absent any topside mark and therefore something of a mystery, although if I was a betting man, I’d lay odds it’s an inexpensive MCU, akin to the one in Big Clive’s teardown victim. What about those glowing LEDs you saw in the earlier plugged-in device photo? They’re at the far upper right and left, with their PCB markings on the other side, which you’ll see next.

They operate somewhat oddly. When I preview them through my smartphone’s camera and display in “still” image capture mode, they generally blink at what I’m guessing is a 60-Hz rate. That said, they also occasionally dim and then return to their prior illumination intensity, and sometimes the blinking also temporarily ceases. When previewed in “video” mode on the smartphone (which I know because I tried to capture a clip of the aforementioned behavior), they exhibit constant illumination. Mysterious!

You might have also noticed PCB sites for two other LEDs, LED3 and LED4, although they seem to be unpopulated, along with multiple other unpopulated locations on this side of the PCB. Chassis placeholders for multiple PCBs…placeholders for additional components on this PCB variant…once again, all very mysterious!

In closing, let’s flip the PCB over.

At top is capacitor C2 which, given its proximity both to the AC inputs to the PCB and to the bridge rectifier, I’m guessing is our aforementioned low-pass filter. The resistor below is specifically labeled “FR1”, presumably referencing its augmented fuse function.

Aside from one other electrolytic capacitor, along with pass-through holes to solder sites on the other side of the PCB for the dual two-wire harnesses (one going to the “ultrasonic speaker”, the other to the AC plug), that’s it of note.

And with that, I’ll conclude for today. At some point after this teardown is published, as usual allowing time for reader questions, I’ll put the device back together, presumably still functional afterward (to whatever degree that term is relevant in this particular case).

But what do I do then? Donate the lot to some pest-plagued recipient hoping against hope for a miracle? Or donate all of ’em to the dump? Let me know your thoughts on this ethical quagmire, or anything else I’ve discussed here, in the comments!

—Brian Dipert is the associate editor, as well as a contributing editor, at EDN.

Related Content

• Automatic Ultrasonic Yard Guard
• Ultrasonic Frequencies For Repelling Insects & Pests
• Electronic Mosquito Repellent Circuit
• Dissecting an underwhelming dog bark controller
• Dog Repellent Circuit
• Dog Repellent Ultrasonic Circuit 2

The post Ultrasonic device claims to repel pests appeared first on EDN.

Nippon Paint participated in SMARTCOR 2026 – 1 st International Conference on Materials for Corrosion Resistance and Smart Control, held on July 10–11, 2026 at CSIR–Institute of Minerals and Materials Technology (CSIR-IMMT),
Bhubaneswar, highlighting Advanced Coil Coatings for a sustainable future.
The premier, global platform united researchers, academia, industry, and innovators to
collaborate and advance corrosion-resistant materials and smart control technologies for a
sustainable future.

Representing the company, Subash Gaijes Selvaraj, President – Industrial Coatings, Nippon
Paint India, delivered a technical presentation on ‘High-Performance Coil Coating Solutions
for Pre-painted Steel’, highlighting the evolving role of advanced coating technologies in
improving durability, corrosion protection, weather resistance, sustainability and lifecycle
performance.
Mr. Gaijes’ Presentation highlighted Nippon Paint’s global R&D capabilities, advanced
exposure testing across diverse climatic conditions and an innovation-led approach to
developing customised coating solutions. He also spoke about next-generation
fluoropolymer technologies, high-performance primer systems, functional coatings and
sustainable solutions, including low-VOC, lead- and chromate-free coatings, cool roof
technologies, and energy-efficient coating systems designed to meet the evolving needs of
modern infrastructure.

Speaking at the conference, Subash Gaijes Selvaraj, President – Industrial Coatings,
Nippon Paint India, said: “Industrial coatings have evolved beyond surface protection to
become strategic enablers of asset performance, sustainability and lifecycle value. At Nippon
Paint, we continue to leverage our global innovation legacy, R&D expertise and customer-
centric approach to develop future-ready coating solutions that support India’s growing
infrastructure and manufacturing sectors.”
Mr. Gaijes also participated in an expert panel discussion on ‘Rust, Risk and Resolution:
Advanced Practices in Industrial Corrosion Management’, where industry leaders discussed
emerging technologies and best practices for enhancing asset protection and lifecycle
performance.

SMARTCOR 2026 brought together researchers, industry experts and technology leaders to
discuss advancements in corrosion prevention, materials science, and sustainable industrial
technologies.

The post Nippon Paint highlights Advanced Coil Coatings for a sustainable future at SMARTCOR 2026 appeared first on ELE Times.

Keysight Technologies, Inc. (NYSE: KEYS) today announced the APS-ONE-400, a modular network cybersecurity test platform. This new 4x100GE platform significantly boosts performance for Layer 4-7 traffic, encrypted traffic, and Elephant Flow traffic all within a 1 rack unit (RU) system. It enables network equipment manufacturers (NEMs), service providers, and data center operators to validate demanding scenarios while lowering overall infrastructure requirements.

The growing complexity and volume of network loads — including legitimate and malicious traffic, post-quantum cryptography (PQC)-encrypted traffic, Zero Trust Network Access (ZTNA), and the Elephant Flow transmissions common in AI and large language model (LLM) workloads — require network equipment manufacturers (NEMs), service providers, and data center operators to validate that their solutions can withstand these demands prior to deployment. However, this often requires multiple specialized test tools that can drive up costs and consume limited lab resources.

To address this challenge, Keysight developed the APS-ONE-400 appliance, an addition to its APS-100/400GE hardware family. The new modular, scalable 4x100GE network application and cybersecurity test platform generates hyperscale Layer 4-7 traffic, PQC-encrypted Transport Layer Security (TLS) throughput, security strikes, and ZTNA test capabilities — all within a compact 1RU footprint that improves lab efficiency.

The APS-ONE-400 4x100GE test platform offers the following benefits:

• Increased performance and efficiency: Delivers 400 gigabits per second (Gbps) Layer 4-7 throughput, 380 Gbps of hardware-accelerated encrypted TLS throughput, 95 Gbps Elephant Flow throughput, and the latest security strikes in a compact 1RU platform that minimizes rack space, cooling, and power consumption.
• Compatibility and flexibility: Deploy as a stand-alone appliance or seamlessly integrate with existing deployments of Keysight’s APS-100/400GE series, including APS-M8400, APS-M1010, and APS-ONE-100. With APS-ONE-400’s fanout support for 100/25/10GE, the platform accommodates a range of critical network speeds.
• Hyperscale performance: When paired with the APS-M8400 appliance or APS-M1010 management controller, the APS-ONE-400 enables hyperscale testbeds that emulate the rigorous demands of data center and service provider environments. The platform can generate up to 16 terabits per second (Tbps) of Layer 4-7 traffic, 20 billion concurrent connections, 15 Tbps of TLS traffic, and 25 million TLS connections per second.
• Modular, scalable solution: Designed as a “pay-as-you-grow” solution, the APS-ONE-400 lets users support current test needs while retaining the flexibility to scale up capacity as requirements evolve.

Ram Periakaruppan, Vice President and General Manager, Keysight’s Network Test and Security Solutions, said: “The exponential growth of data transfers and bandwidth demands generated by AI and machine learning workloads is putting unprecedented strain on data center, service provider, and enterprise network infrastructures. Continuously validating that networks can handle these challenges without compromising security requires realistic, hyperscale traffic emulation capabilities. Keysight’s modular APS-ONE-400 compute node delivers new heights in realism, emulating the traffic flows associated with generative AI models and agentic applications at hyperscale, including the huge Elephant Flow datasets common to LLM training use cases and PQC-encrypted traffic flows, all in a compact form factor that conserves critical lab resources.”

The post Keysight Delivers New High-Performance 4x100GE Network Cybersecurity Test Platform appeared first on ELE Times.

In a bid to provide safer drinking water to thousands across Delhi’s largest informal
settlements, 16-year-old Devika Raj Batra, has developed a community water-safety initiative
built around a patent-pending submersible UV-C LED sterilisation device. The unit disinfects
stored household drinking water in about fifteen minutes. Running on a standard USB cable,
this purification solution is designed to be placed directly into the buckets, matkas, and drums
families already use.

The device works with a single button and emits an audible cue when the sterilisation cycle is
complete. The users do not need to follow any user’s manual or read any instruction guide
before using this device. What’s more, they can carry on with the household’s existing water-
storage habits while making the most of this technology.

As part of the developmental process, Devika and her team has conducted microbiological testing, adhering to
IS and WHO standards on household water samples before and after treatment. The device
was claimed to be tested for total coliforms, E. coli, faecal coliforms, Staphylococcus aureus,
Salmonella, and Shigella. Every tested indicator pathogen was successfully inactivated.
With this initiative, Devika intends to target India’s urban informal settlements, where the act
of collecting, storing, boiling, filtering, and protecting household water is a strenuous task. A
class 12 student from New Delhi, Devika has designed this unit from scratch. This portable
sterilisation device is part of Project Amrit, which already reaches more than 10,000 residents
across nearly 2,000 households in the Kusumpur Pahari region of South Delhi.

This initiative has showcased documented health improvements across 300 households till
date. The design choices behind Project Amrit, says Devika, are not specific to Delhi, but
across all applicable informal settlements, which feature a submersible form factor, chemical-
free operation, low maintenance, compatibility with existing storage vessels, and usability for
households with limited literacy or time. This makes the model scalable across urban
settlements in South Asia, Sub-Saharan Africa, and Southeast Asia, where stored drinking
water remains a major site of contamination.

The post 16-Year-Old Develops Innovative Water Sterilisation Technology appeared first on ELE Times.

What looks like a simple port is in fact a silent architect—quietly shaping how energy and data flow between your car and your mobile world. Hidden inside that small rectangle of metal and plastic is a choreography of power regulation, signal integrity, and protocol negotiation.

It’s the unseen engineering that turns a “plug” into a lifeline, ensuring your EV and your phone don’t just connect, but truly communicate.

From socket to smart port

Once upon a dashboard, the humble “cigarette lighter” socket was nothing more than a dumb power tap—12 volts, no questions asked. Fast forward to today, and the USB-C port in your EV is no longer a passive outlet; it’s an intelligent node in a vast digital ecosystem. That tiny connector is the handshake between two massive computers: your phone and your car.

It juggles a delicate balance, delivering high-wattage energy to keep devices alive while simultaneously orchestrating millisecond-sensitive data streams that define navigation, entertainment, and even safety. In short, your USB port is not just a plug; it’s a bridge, a translator, and a silent engineer behind the scenes of modern mobility.

Power architecture: From traction to tablet

Unlike traditional cars, EVs don’t carry an alternator humming under the hood. Instead, they rely on a DC-DC converter—a silent workhorse that steps down the traction battery’s 400-V or even 800-V supply to the familiar 12-V rail that powers the cabin. That same rail feeds the USB ports, infotainment systems, and auxiliary electronics.

Think of it as an “infinite power bank”: charging your phone at 15 W for an hour consumes only about 0.015 kWh. Put that in perspective, a 75 kWh Tesla battery could technically recharge an iPhone 15 Pro Max more than 4,000 times. In other words, your EV’s energy reserves make mobile charging almost trivial, yet the engineering behind that seamless handoff is anything but.

Figure 1 Onboard DC-DC converter services the low-voltage auxiliary rail by extracting energy from the high-voltage traction battery. Source: Brogen EV Solution

Sidenote: Instead of combustion fuel, the high-voltage traction pack stores electrical energy at hundreds of volts, driving the motor and, through the DC-DC converter, sustaining the 12-V system.

The “signal” side: The handshake

If the power architecture is the muscle, the signal side is the brain. In USB-C, no current flows until a negotiation takes place. That negotiation happens over the Configuration Channel (CC) pins, where your EV and your phone exchange digital hellos before any electrons move.

Through this handshake, they decide critical roles: Who is the host? (almost always the car), and how much voltage can the phone safely accept?—whether it’s 5 V for legacy devices, 9 V or 15 V for fast-charging, or even 20 V for high-power modes. Only after this millisecond-level dialogue does energy begin to flow, ensuring that what looks like a simple plug-in is actually a carefully choreographed agreement between two computers.

Figure 2 Integrated electronics drive a 60-W USB-C car power socket, providing native support for Power Delivery, Quick Charge, and other fast-charging protocols. Source: Pro Car

Once the roles and voltage levels are agreed, the conversation doesn’t stop—it deepens into data protocols. Over the very same power pins, USB Power Delivery (USB-PD) runs a digital dialogue, negotiating charging speed and ensuring both sides stay within safe limits.

Parallel to that, separate high-speed differential pairs carry the real payload: the streams of audio, video, and control signals that make Apple CarPlay and Android Auto feel seamless. In effect, your EV’s USB port is multitasking—one channel whispering about volts and watts, another racing to deliver maps, playlists, and messages—all in perfect sync.

The challenge: Noise and interference

Your EV’s cabin is far from electrically serene. High-frequency switching from motor inverters and power electronics creates a “dirty” environment filled with electromagnetic noise. To keep your USB connection clean, manufacturers rely on shielded twisted pairs (STP) cables designed to resist interference and preserve signal integrity, so your music and navigation don’t glitch under the influence of stray magnetic fields.

But shielding alone isn’t enough. The electronics inside the USB interface must also withstand sudden voltage spikes and magnetic surges. That’s where common-mode transient immunity (CMTI) comes in; it’s a design requirement that ensures the transceivers can survive and keep data flowing even when the EV’s power electronics throw out nanosecond-scale noise bursts. Without strong CMTI performance, those spikes could corrupt packets or drop connections.

Figure 3 Oscillogram illustrates an EV-style CMTI spike waveform during a high-speed transient event. Source: Author (AI-generated)

Sidenote: In high-performance EV architectures, the drive for faster switching efficiency can turn CMTI into a critical bottleneck. As platforms move to 800-V systems, the steep voltage transitions (dv/dt) from wide bandgap (WBG) semiconductors—notably SiC and GaN—produce intense high-frequency transients. These spikes can leak through parasitic capacitances in isolation barriers (in gate drivers or digital isolators), risking shoot-through events where both switches conduct simultaneously, a destructive failure mode for traction inverters.

Especially, GaN’s ultra-fast switching makes it more vulnerable. To protect control logic and safeguard costly WBG modules, modern EV designs now require isolated gate drivers with ultra-high CMTI ratings (often >150 kV/µs, specified for both positive-and negative-going transients), a design safeguard that directly underpins range, reliability, and performance.

Also, it’s worth noting that there are two types of CMTI: static and dynamic. Static CMTI refers to the test condition where the input is held at a fixed logic high or logic low, and the output state is monitored during a common-mode transient strike. The requirement is that the gate driver output remains in its specified state across variations in process, voltage, and temperature.

Dynamic CMTI, by contrast, evaluates immunity while the device is actively switching. This measures whether the transient causes timing jitter or pulse distortion—making it the more demanding metric and the true limiter in fast-transition EV platforms using WBG devices.

And then there’s the subtle menace of ground loops: a cheap, poorly shielded cable can create electrical conflict between the car’s ground and your phone’s ground, producing that familiar buzzing in the speakers. What seems like a trivial accessory choice can make the difference between crystal-clear audio and noisy rides.

Why do some ports “only charge”

Ever noticed that not every USB port in your car lets you run CarPlay or Android Auto? That’s by design. Many automakers follow a hub strategy: one “Master Data Port” up front, usually near the driver, and several “dummy ports” in the rear that are charge-only. The reason is cost and complexity.

A data-capable port requires an automotive-grade controller, shielded wiring, and careful integration into the infotainment system—all of which add expense and engineering overhead. By contrast, a charge-only port is far simpler: just a buck converter stepping down voltage to feed your device. It’s a deliberate hardware trade-off, balancing convenience for passengers with the realities of automotive design budgets.

V2L: The ultimate USB upgrade

If USB-C feels powerful, Vehicle-to-Load (V2L) takes the idea to an entirely new scale. Cars like the Hyundai IONIQ 5 or Kia EV6 don’t stop at charging your phone; they turn the whole vehicle into a rolling generator. Instead of 60 W from a USB-C port, V2L delivers up to 3.6 kW through a standard AC outlet at 120 V (North America) or 230 V (Europe/Asia). That’s enough to run a full desk setup: monitor, laptop, and lights, all powered via a USB-C multi-charger.

And in trucks like the Ford F-150 Lightning, the concept scales even further with Pro Power Onboard, offering up to 9.6 kW across multiple AC outlets. At that level, the EV isn’t just a power bank; it’s a backup generator capable of supporting tools, appliances, or even parts of a home during an outage. In essence, V2L is the logical extension of the same engineering principles—scaling from watts to kilowatts—while keeping the promise of mobility and connectivity intact.

Sidenote: V2L technology depends on a coordinated handshake between the vehicle and adapter, primarily through the Proximity Pilot (PP) and Control Pilot (CP) pins defined by IEC 61851. The PP resistor identifies the adapter type and signals readiness, while the CP line maintains PWM-based communication for safe connection and disconnection.

In bi-directional on-board chargers, detection of the correct PP resistance or proprietary handshake prompts the system to enter discharge mode, closing internal contactors to deliver AC power outward. If the CP signal drops or the adapter is unplugged, the vehicle instantly opens the contactors to prevent arcing—ensuring safe, reliable V2L operation across varying manufacturer implementations.

Figure 4 A universal V2L adapter with a mode selector supports multiple EV platforms by initiating the vehicle’s power-discharge sequence. Source: Author

The future: Wireless vs. wired

Convenience is pushing hard toward wireless, but the trade-offs are real. Wireless charging pads promise a cable-free cabin, yet they come with hidden costs: extra heat from inductive transfer and a slight latency in power delivery compared to the precision of a wired USB-C port. That means slower charging and less efficiency, especially when you’re juggling multiple devices.

On the data side, the shift is already happening. Wireless CarPlay and Android Auto bypass the USB port entirely, riding on the car’s internal Wi-Fi signal. In this setup, the USB port is relegated to pure power duty, while your phone streams navigation, music, and messages over a wireless link. It’s a glimpse of the future—where the port becomes less about data and more about energy, while the car’s network takes over the role of digital bridge.

The car as a service

We used to choose cars based on horsepower; now we choose them based on their digital horsepower. Infotainment speed, connectivity options, and seamless integration with our mobile lives have become as decisive as torque or acceleration. And at the center of that experience sits the most-used interface in the cabin: the USB port.

It’s no longer just a plug—it’s the gateway to energy, data, and the services that define modern mobility. In this sense, the car has evolved into a platform, a service hub on wheels, where the humble port is the everyday touchpoint between driver, device, and digital ecosystem.

From volts to vision, engineering isn’t just power, it’s empowerment.

T. K. Hareendran is a self-taught electronics enthusiast with a strong passion for innovative circuit design and hands-on technology. He develops both experimental and practical electronic projects, documenting and sharing his work to support fellow tinkerers and learners. Beyond the workbench, he dedicates time to technical writing and hardware evaluations to contribute meaningfully to the maker community.

Related Content

• USB Keypad Reference Design
• USB Proves Ready for T&M Tasks
• Top 10 innovative USBs and peripherals
• Take off with Simplified USB Type-C Development
• The USB takeover: Why modern T&M is moving to your pocket
• A quick and practical view of USB Power Delivery (USB-PD) design

The post More than a plug: The hidden USB engineering in your EV appeared first on EDN.