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Phlux Technology — which was spun off from the University of Sheffield in 2020 and designs and manufactures 1550nm avalanche photodiode (APD) infrared (IR) sensors — has announced beta-sample availability of the Apex 200µm receiver module, PX02200-TO, for ultra-low-light detection as part of a family of Apex receivers that combine Phlux’s Noiseless InGaAs Aura APD detectors with low-noise, optimized pre-amplifier circuits all integrated in an industry-standard TO-8, 12-pin header package...

As quantum technologies move towards commercial deployment, the need to accelerate UK research into scalable, real-world deployment is increasingly critical. In response, the UK’s Compound Semiconductor Applications (CSA) Catapult has appointed as head of quantum, helping to accelerate its focus on key areas including quantum systems, AI hardware, advanced packaging, photonics, RF control, William Waller cryogenic integration and test. These capabilities are central to enabling the next generation of quantum technologies, particularly in quantum communications, quantum sensing and future quantum computing infrastructure, where integration, reliability and scalability will be essential...

As quantum technologies move towards commercial deployment, the need to accelerate UK research into scalable, real-world deployment is increasingly critical. In response, the UK’s Compound Semiconductor Applications (CSA) Catapult has appointed as head of quantum, helping to accelerate its focus on key areas including quantum systems, AI hardware, advanced packaging, photonics, RF control, William Waller cryogenic integration and test. These capabilities are central to enabling the next generation of quantum technologies, particularly in quantum communications, quantum sensing and future quantum computing infrastructure, where integration, reliability and scalability will be essential...

Rohde & Schwarz is driving the commercialization of 5G-based New Radio non-terrestrial networks, with successful certification of the highest number in GCF conformance test cases for NR-NTN to date. The validation covers all three domains, RF, RRM, and PCT.

Following the successful validation of the first 5G-based NR-NTN at the PTCRB (PCS Type Certification Review Board), Rohde & Schwarz continues its efforts to enable validation at the GCF (Global Certification Forum). The validated test cases within GCF WI-555 (Work Item) are defined in accordance with the 3GPP test specifications for RF (Radio Frequency), RRM (Radio Resource Management), and PCT (Protocol Conformance Testing) and were executed with Rohde & Schwarz conformance test solutions.

All measurements were conducted on the R&S TS8980 Conformance Test Platform, the R&S TS-RRM, and the CMX500 in frequency range 1 (FR1), verifying the latest NR-NTN chipset from Samsung as the device under test (DUT).

3GPP conformance testing is essential for ensuring that devices and networks comply with global standards. 5G NR-NTN testing presents challenges that extend beyond those encountered in traditional terrestrial networks, primarily due to the vastly different operating environment and the dynamic nature of satellite-based communication.

At the core of the Rohde & Schwarz conformance test solutions is the CMX500 5G one-box signaling tester, which also supports early research and development through integrated fading and channel emulation, along with an intuitive tool for visualizing satellite constellations – all in a single-box test setup. In addition, the user-friendly R&S CONTEST test system software platform facilitates the seamless execution of 3GPP test cases.

The post Rohde  and Schwarz Leads GCF 3GPP NR-NTN Validation with Record Test Cases appeared first on ELE Times.

After announcing capacity investments last July and October and this February, Tokyo-based JX Advanced Metals Corp is to invest up to ¥120bn more over the next four years to further expand its production capacity of indium phosphide (InP) substrates, used in optical communications transceivers that support the large-volume data transmission required by the advancement of AI...

After announcing capacity investments last July and October and this February, Tokyo-based JX Advanced Metals Corp is to invest up to ¥120bn more over the next four years to further expand its production capacity of indium phosphide (InP) substrates, used in optical communications transceivers that support the large-volume data transmission required by the advancement of AI...

ROHM develops the “AG16xFNxx Series,” a lineup of 80V power MOSFETs designed for 48V power supply systems, which are becoming increasingly common in automotive applications.

In the automotive sector, power demand is increasing, particularly in high-end vehicle models. 48V power supply systems are gaining attention as a highly efficient alternative to conventional 12V power supply systems. With widespread adoption expected around 2030, there is a growing need for 80V power MOSFETs capable of delivering even lower power losses than standard 100V devices.

ROHM’s new products enable downsizing in comparison to standard automotive MOSFET packages such as the TO-252 (6.6 × 10.0mm) by adopting the HPLF5060 (4.9 × 6.0mm) and DFN3333 (3.3 × 3.3mm) packages.

The HPLF5060 features Gull-Wing Leads, while the DFN3333 features Wettable Flank Technology, which contributes to improved reliability on PCBs (Printed Circuit Boards). Furthermore, by adopting Copper Clip Junction Technology to enhance heat dissipation, these devices are capable of handling high currents. All models comply with the automotive reliability standard AEC-Q101, ensuring high reliability.

The product lineup of these packages will be further expanded in the near future. In addition, development of TOLG (TO-Leaded with Gullwing, 9.9 × 11.7mm) packaged products has begun, with continued expansion of the lineup of high-power, high-reliability 80V MOSFETs.

Application Examples

Automotive 48V systems: Main inverter control circuits, electric motors, electric water pumps, etc.

 

The post ROHM Launches AG16xFNxx Series MOSFETs for Automotive 48V Power Supply Systems appeared first on ELE Times.

🔵 День вступника 2026 kpi ср, 06/17/2026 - 11:42

When chip design and verification teams start a new project, they recognize the need for models that capture the design at a high level of abstraction. However, they tend to focus on acquiring or creating models of the IP blocks used to implement the device’s core functionality, while overlooking network-on-chip (NoC) interconnect IP until it’s too late.

Modeling and simulation evolution

As chip designs grew from a handful of gates in the 1970s to hundreds of IP blocks connected by complex interconnect fabrics in the 2020s, modeling and simulation evolved to keep pace. Early approaches modeled everything at the gate level, providing complete visibility, but they quickly became impractical as complexity increased.

The industry’s first major step up in abstraction was the register transfer level (RTL). These models describe how data moves between registers on each clock cycle, maintaining bit-level and cycle-level accuracy. To this day, RTL simulation remains the gold standard for functional correctness and final sign-off. The trad-eoff is speed. Because the RTL models every signal transition, meaningful simulations can take hours or even days.

Figure 1 The integration of functional blocks and interconnects increased over time. Source: Arteris

To address this, engineers introduced cycle-accurate models. These preserve timing at the clock-cycle level but avoid modeling every individual signal. They capture events as they happen without describing every bit flip, thereby making them ideal for performance analysis. Designers can evaluate latency, bandwidth, and contention with high confidence while running simulations fast enough to explore architectural alternatives.

At an even higher level of abstraction is transaction-level modeling (TLM). Rather than modeling signals and clock cycles, TLM focuses on high-level transactions, such as moving data across the system. By abstracting away low-level implementation details, TLM can enable simulations that run orders of magnitude faster than RTL. This speed makes it practical to test hundreds of scenarios and quickly explore different design options.

TLM models also underpin virtual prototypes, enabling software to run on a simulated hardware platform long before silicon is available. This enables early hardware–software co-verification and faster overall development.

System complexity increases

Modern system-on-chips (SoCs) are sophisticated ecosystems in which processors, accelerators, memory subsystems, and NoC interconnect fabrics must work in concert with complex software stacks.

This interaction adds another layer of complexity because software must be verified in the context of the hardware throughout the design process. RTL simulation continues to play a critical role, particularly for final validation and corner-case debugging. However, it’s simply too slow to support meaningful software development at scale. Higher-level models, especially TLM-based virtual prototypes, enable software teams to begin work early while hardware teams continue refining the design.

If all of this sounds challenging, it becomes even more so in the era of chiplets and multi-die systems. Modern designs increasingly partition functionality across multiple dies, sometimes mixing process nodes, vendors, and packaging technologies. Data must move not only within a die, but across die boundaries. Some of this traffic is non-coherent, while other portions must maintain cache coherency, depending on the system architecture.

Figure 2 Here is how die-to-die options look like in NoC designs. Source: Arteris

The result is a heterogeneous communication fabric that is far more complex than the simple buses of the past. In such environments, performance is no longer determined solely by the compute elements themselves. Instead, it depends heavily on how efficiently data can move between them. Increasing data movement complexity—driven by heterogeneous compute, coherence requirements, and chiplet architectures—makes overall system performance difficult to predict without appropriate modelling.

Beyond the IP blocks

That same modeling discipline must extend to the NoC interconnect. In modern designs, NoCs are no longer passive conduits. They are first-order determinants of system performance. A contemporary SoC may contain multiple NoCs, some coherent, some non-coherent, and some forming bridges between chiplets. These interconnect fabrics are highly configurable, with parameters governing topology, bandwidth, arbitration policies, buffering, and quality-of-service (QoS) mechanisms.

This means NoCs must be modeled at the same levels of abstraction as the rest of the system. Transaction-level models support rapid exploration and system-level integration. Cycle-accurate models enable detailed performance analysis, and RTL models remain essential for final verification and implementation. Crucially, these models must be consistent with one another, enabling smooth progression from architectural intent to implementation reality.

Equally important is the ability to analyze the results generated by these models. These analysis capabilities enable designers to examine key performance indicators—including bandwidth utilization, latency, congestion, contention, buffering efficiency, and QoS behavior—across the NoC fabric. Rather than forcing engineers to sift through enormous amounts of low-level simulation data, the modeling environment presents targeted performance insights that help teams quickly identify bottlenecks, validate architectural assumptions, and compare alternative configurations.

This kind of system-level analysis is valuable in complex chiplet-based designs. Architects can use automatically generated SystemC TLM models to study NoC behavior earlier and help create and iterate NoC topologies faster.

From Exploration to implementation

Increasingly, commercial NoC providers are offering higher-level models alongside their RTL implementations. In many cases, however, these models are added as an afterthought, a bolt-on capability that may not fully reflect the behavior of the final implementation. What’s emerging as a best practice is a more integrated approach in which modeling is not an add-on but a foundational element of the design flow.

Arteris, for instance, offers FlexGen interconnect IP for non-coherent interconnects and Ncore for cache-coherent fabrics. These solutions are supported by a continuum of models, from transaction-level to cycle-accurate to RTL, designed to be consistent and correct by construction.

The result is a design methodology that enables teams to explore, validate, and refine their architectures early, with confidence that their insights will carry forward into implementation. In a world where performance margins are tight, schedules are unforgiving, and complexity continues to grow, the ability to move fast and get it right the first time may be the most valuable model of all.

Rocco Jonack is principal corporate application engineer at Arteris, where he works on advanced SoC architecture modeling, virtual prototyping, and performance analysis for complex semiconductor systems.

 

Related Content

• SoC design: What’s next for NoCs?
• How NoC architecture solves MCU design challenges
• Smarter SoC Design for Agile Teams and Tight Deadlines
• Why verification matters in network-on-chip (NoC) design
• NoC configuration tool takes makes complex SoC design easier

The post Model your IPs and your NoCs appeared first on EDN.

Sound meter with tower light and projector message device for classroom a teacher is buying submitted by /u/noooooo_12 [link] [comments]

🔗 Проєкт Професійного стандарту «Оператор з обслуговування та експлуатації когенераційних установок» kpi ср, 06/17/2026 - 00:00

I am really autistic about the precision of temperature in my projects, and I found a cheap toaster oven for 14$ the perfect size for my work space, decided to replace the bimetallic thermostat with custom electronics and control circuitry, it was an amazingly fun project! hope you all enjoy this dumb project! and remember, if you mess with 120V BE CAREFUL! programming listed on github, video of process posted to youtube https://github.com/EleriLove/pwm-pid-control-of-relay- https://youtu.be/Qr83flDN-Bk submitted by /u/JarrekValDuke [link] [comments]

I’m always interested in how researchers, scientists, engineers, and manufacturing specialists leverage apparently unrelated advances to their own advantage for devising innovative techniques and advances. This phenomenon is not new, of course; it’s been one of the driving forces behind technological advances for hundreds of years in situations ranging from fairly modest to some that are impressively esoteric.

This seems to be the case especially for sophisticated sensors. The latest one I have seen addresses the challenge of detecting terahertz energy. It’s not news to this audience that the terahertz region of the electromagnetic spectrum, generally defined as 100 GHz to 10 THz, has many barriers when developing complete viable systems. It’s informally called the “THz gap” where the frequencies are too high and the wavelengths too short for most electronic components; yet too low and too long, respectively, for using optical ones.

A deep-physics concept

Addressing this issue, a joint team at the University of Cambridge and Swansea University (both in the U.K.) took advantage of some “new” physics. Their sensor merges a metasurface with a recently discovered quantum physics effect that is a spinoff of the well-known photoelectric effect.

In the photoelectric effect, there is the emission of electrons (current) from a material (usually a metal) when it’s struck by electromagnetic radiation such as light with high-enough energy. In contrast, their terahertz detector makes use of the in-plane photoelectric effect (IPPE), where incoming terahertz photons transfer energy to electrons that are confined within a two-dimensional electron gas. Those energized electrons cross a carefully designed potential step, generating an electrical current that can be measured.

If you are not familiar with the photoelectric effect, it has a major place in the history of modern quantum physics. The effect had been observed since the latter half of the 1880s with solid experimental data, but non-quantum physics could not explain the data and in fact was at odds with the data. Albert Einstein proposed a radically new explanation in his seminal 1905 paper “On a Heuristic Viewpoint Concerning the Emission and Transformation of Light”—one of four truly significant papers he had published in that “miraculous year”, which resulted in the Nobel Prize award in 1921.

That photoelectric effect, however, is different in the in-plane version, a phenomenon that was observed only recently, in 2022 (“An in-plane photoelectric effect in two-dimensional electron systems for terahertz detection”). In the IPPE quantum process, incoming terahertz photons transfer energy to electrons confined within a two-dimensional electron gas. Those energized electrons cross a carefully designed potential step, generating an electrical current that can be measured.

Unlike conventional photoelectric detectors, this mechanism does not require photons to exceed a minimum energy threshold. Because the process occurs entirely within the plane of the material, it also avoids several efficiency limitations that affect traditional detector designs.

While earlier detectors using this concept showed promising performance, they suffered from one major drawback. They captured only a small portion of the incoming radiation because they relied on single-antenna structures.

A new approach

To overcome that limitation, the team devised a metasurface with a patterned structure that concentrates electromagnetic energy into regions much smaller than the wavelength of the incoming radiation. In the new design, a repeating “brickwork” pattern gathers terahertz waves and channels them into narrow gaps where detection takes place (Figure 1).

Figure 1 Schematic diagram of the MetaPETS detector with the brickwork metamaterial (a). Zoom-in view showing a unit cell indicated by a black dashed rectangle. The unit cell sizes in the 𝑥- and 𝑦-directions, 𝑑𝑥 and 𝑑𝑦, are indicated (b). Zoom-in view highlighting the capacitive gap, illustrating the width 𝑤 of the capacitor in the lateral (𝑥)-direction, and the gap size 𝑔 of the capacitor. The 2DEG is depleted along the edge of the mesa, as indicated, causing the area of the conducting 2DEG to be offset inwards from the lithographically defined mesa edge (c). Zoom-in view highlighting the summation of photocurrents generated by the PETS detection elements at the lower right corner. The electron flow occurs within the 2DEG, and its direction is shown by the red arrows. Without loss of generality, we show an example with gate 1 positively biased and gate 2 negatively biased (d). Photocurrent detection circuit (e). Source: SPIE Digital Library

Each of these tiny gaps functions as an individual detector. By distributing many of them across the metasurface and connecting them electronically, the researchers were able to combine their outputs into a stronger overall signal.

But that was only the first step. Individual photoelectric tunable-step (PETS) detector elements were then integrated into the capacitive gaps, as they experience the strongest electromagnetic fields. This ensures optimal coupling of the metasurface to the detection elements and significantly boosts the detection sensitivity compared to simply connecting the elements in parallel.

Fabrication relied on a semiconductor structure containing a high-mobility electron gas. The manufacturing process closely resembles techniques already used to produce field-effect transistors, making future integration with electronic circuits more feasible. Since the metasurface itself concentrates the incoming radiation, the detector does not require external focusing components such as silicon lenses and their precise alignment, which simplifies assembly, reduces cost, and could make large-scale manufacturing easier.

In tests, the detector was cooled to 10 K and exposed to radiation near 1.9 THz. It generated a clear electrical signal that matched the on and off pattern of the incoming radiation. Measurements showed a responsivity of 2.7 amperes per watt. The proof-of-concept device also achieved an external quantum efficiency of 2.1% at 1.9 THz.

Figure 2 Time-averaged photocurrent in response to the 1.881 THz quantum cascade laser (QCL) radiation, measured in the source-drain circuit while mechanically blocking and unblocking the THz waveguide (WG). The two gates are biased at +0.76 V and −0.095 V, respectively (a). Real-time photocurrent measurement using an oscilloscope, showing the response to a pulse emitted by the QCL during its on time with 100 sweeps averaged. The two gates are biased at +0.76 V and −0.095 V, respectively (b). 2D maps are shown as a function of the two gate voltages: photocurrent (c) and four-wire conductance of the device (d). Source: SPIE Digital Library

According to the researchers, this represents roughly a 20-fold improvement over previously demonstrated PETS detectors. Much of that gain comes from the metasurface’s ability to capture more incoming radiation and direct it into the active detection regions.

The work is described in both theory and practical facets in their readable paper “Quantum metasurface-based photoelectric tunable-step terahertz detector” published in Advanced Photonics. Of course, they note that there’s more work to be done. The researchers believe the technology could eventually operate at temperatures higher than those required by many competing detector designs. Similar PETS devices have already demonstrated performance at temperatures reachable using compact cryocoolers rather than liquid helium.

Have you used a highly sophisticated sensor that blends advanced technologies, or had to innovate and implement such a sensor yourself? What were the unexpected challenges you encountered?

Bill Schweber is a degreed senior EE who has written three textbooks, hundreds of technical articles, opinion columns, and product features. Prior to becoming an author and editor, he spent his entire hands-on career on the analog side by working on power supplies, sensors, signal conditioning, and wired and wireless communication links. His work experience includes many years at Analog Devices in applications and marketing.

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The post Metasurface plus photoelectric quantum effect yields sensitive THz detector appeared first on EDN.

With the explosive growth of artificial intelligence and the exponential increase in computing power demand, data centers require greater bandwidth but without increasing power consumption further. The short-distance interconnect solution inside data-center servers and racks is currently undergoing a historic shift of ‘optical-in, copper-out’...

I have a long standing fascination with nixie tubes and wanted to build something for a while. I got this board of aliexpress with only basic clock and i simply could not waste it to leave at that so I have reverse engineered connections and disabled on board chip. I have replaced boring stm chip with esp32 and now have a cool looking clock with functions like: Timer, stopwatch, reminders, alarms, navidrom music player, adjustable RGB, wifi ntp sync etc. All controlled via backed web-ui submitted by /u/Thick_Swordfish6666 [link] [comments]

Synthetic diamond materials firm Element Six of Oxford, UK (E6, part of the De Beers Group) and Tokyo-based Orbray Co Ltd (which makes precision jewel parts, DC coreless motors, fiber-optic components, and medical devices) have announced the next phase of their partnership, building on a joint aim to deliver wafer-scale single-crystal diamond (WSC)...

Multiple domains provide designers and test engineers with complementary views of acquired signals.

Oscilloscopes originated as instruments that measure electrical signals in the time domain. The advent of the digital oscilloscope, where input waveforms were digitized and stored in the instrument, opened the door to other analysis domains. In addition to the time domain analysis of the signal, these include the Fast Fourier Transform (FFT) for frequency domain analysis and histograms for statistical analysis. These three measurement domains provide designers and test engineers with three complementary views of the acquired signals. This article reviews the three domains and provides an example of how they interact to facilitate problem diagnosis.

The time domain

The time domain plots the signal’s voltage versus time. This was the original, and still is the primary, function of the oscilloscope (Figure 1).

Figure 1 This time domain view of a sine wave, an oscilloscope’s original and still primary function, also includes some standard time domain measurement tools.

The time domain view shows the waveform as a function of time. The vertical axis is typically measured in volts, but it can be rescaled to measure in any relevant units when used with appropriate sensors. The vertical channel is scaled in volts per division. The horizontal axis is time in seconds, with the scale set to seconds per division. Time-domain measurements can be as simple as counting vertical and horizontal boxes between significant events on the displayed trace and multiplying by the appropriate scale factor, as we did in the “Before Computer (BC)” era.

Most modern oscilloscope users prefer using cursors or automatic measurement parameters. The figure shows the use of both. The cursors (vertical dashed lines) are set to measure the width of the waveform at the half amplitude of a positive half-cycle. Measurement parameters P1 through P4 measure the amplitude, frequency, period, and RMS amplitude of the waveform, respectively.

The frequency domain

A digital oscilloscope acquires and stores the input waveforms. Having the digital representation of the waveform internally allows the oscilloscope’s analysis tools to process the data. One of the most commonly used tools is the Fast Fourier Transform (FFT). The FFT converts the acquired time-domain data into the corresponding frequency-domain data, also known as a spectrum. This enables the oscilloscope to perform most of the common measurements typically found in a spectrum analyzer (Figure 2).

Figure 2 The FFT spectrum of the sine wave plots signal power versus frequency, showing the frequency content of the acquired signal.

The spectrum of a sine wave shows a spectral line at the fundamental frequency, 10 kHz in this example. Due to the large dynamic range of the frequency domain view, it defaults to a logarithmic vertical axis. This scale is calibrated to read in decibels relative to one milliwatt (dBm). If the acquired signal were a perfect sine wave, then the fundamental is all there would be. In the real world, signal sources are not perfect and also show noise and harmonics. This signal has spectral lines at the third (30 kHz), fifth (50 kHz), and seventh (70 kHz) harmonic frequencies.

The frequency domain has the same measurement tools as the time domain, namely, cursors and measurement parameters. The measurement parameters include many that are specific to frequency domain measurements. In this example, the spectral peak amplitudes and frequencies are read out for the fundamental and third harmonics. The fundamental frequency is 10 kHz (P2), and its amplitude is -7.5 dBm (P1). The third harmonic at 30 kHz (P4) has an amplitude of -84.9 dBm (P3), about 77 dB below the fundamental. The dashed lines on the display show the measurement markers for the parameters, indicating what each measures.

The statistical domain

The statistical domain consists mainly of histograms and persistence trace statistical displays. The histogram is the principal tool of statistical analysis. The persistence trace displays show the statistical mean, standard deviation, and range for each point along a trace. The histogram counts the number of amplitude values within a narrow range (called a bin) as a function of amplitude. The vertical axis is the number of samples in a bin, and the horizontal axis is amplitude (Figure 3).

Figure 3 The amplitude histogram of a sine wave is the principal tool of its statistical analysis.

The histogram of a sine wave has a saddle shape, higher on each end and lower in the middle. The reason for this shape lies in the signal’s rate of change. The oscilloscope samples the incoming signal at a fixed rate. If the input signal has a non-uniform rate of change, there will be a greater number of samples where the signal’s rate of change is slower and fewer samples when the rate of change is faster.

In the case of a sine wave, the rate of change is the slowest at both the positive and negative peaks, and greatest at the zero crossings. Hence, the histogram has the greatest concentration of values at the negative (left side) and positive (right side) values. The zero crossings, located in the center of the histogram, have the lowest concentration of values.

The measurement parameters in the statistical domain include the mean, mode, median, standard deviation, and range, among others. The mean, standard deviation, and range of the histogram in the figure are displayed. The mean is the average value of the waveform, the range is the peak-to-peak value, and the standard deviation is the RMS value for a zero mean (some oscilloscope suppliers list it as AC RMS).

Measuring in three domains

Measuring distortion in an amplifier is a common application for an oscilloscope. Consider a measurement of crossover distortion in a push-pull amplifier that uses two transistors to drive a load (Figure 4).

Figure 4 This simplified overview of a push-pull amplifier is accompanied by a diagram of crossover distortion.

The push-pull amplifier uses two complementary transistors to drive a load. The upper NPN transistor supplies current to the load on the positive half of the input signal. The PNP transistor drives the load for the negative half of the input signal. The transistors conduct alternately, based on the polarity of the input signal.

This type of circuit is commonly found in various applications, including amplifiers, half-bridge and full-bridge power supply circuits, and even totem pole output circuits in ICs. The advantage of push-pull operation is that it has no quiescent power dissipation; when the input is zero volts, no power is delivered to the load. A measurement of a properly operating push-pull amplifier (simulated) shows nearly ideal performance (Figure 5).

Figure 5 The analysis of a properly functioning push-pull amplifier shows nearly ideal performance.

Applying a 10 kHz sine wave to a simulated amplifier and analyzing the output yields the expected results across all three measurement domains. The top trace is the time domain view, expanded using horizontal zoom in the trace below it. The trace is a smooth sine wave with no non-monotonic areas. The positive and negative half cycles have a symmetrical shape. There is no obvious clipping or limiting.

The frequency spectrum displays a fundamental spectral line at 10 kHz, accompanied by small odd harmonic distortion products at 30, 50, and 70 kHz, all of which are below -90 dBm. The statistical domain view is a histogram that exhibits a classical, symmetrical saddle-shaped distribution.

One thing that cannot be allowed in this type of amplifier is for both transistors to conduct simultaneously, which would short-circuit the positive and negative power buses. Most amplifiers use a considerable amount of circuitry to prevent this from happening. This compensation can cause one transistor to turn off before the other turns on, resulting in a nonmonotonic flat spot in the output waveform. This situation is described as crossover distortion, which was shown in Figure 4.

What does crossover distortion look like in the three measurement domains? See Figure 6 for an example.

Figure 6 Crossover distortion is evident in all three measurement domain views.

The figure shows a waveform simulating crossover distortion. The distortion is evident in the zoom trace at the zero-crossing points. In this example, the distortion is exaggerated to make it obvious in the time-domain waveform. The frequency spectrum still shows the 10 kHz fundamental, but the levels of the odd harmonics have increased in both number and amplitude.

The FFT spectrum is excellent at showing the presence of distortion as an increase in harmonic amplitudes. The harmonic amplitudes are in the range of -65 to -70 dBm, about 20 to 25 dB higher than the previous levels of normal operation. What the spectrum doesn’t indicate is the source of the distortion.

Look at the histogram in the bottom trace in the figure. Note the large spike at the zero crossing. This indicates a large number of sample values at the 0-volt level, an indicator of crossover distortion. Other forms of distortion would appear in different areas. If the histogram is not symmetric when folded about the zero amplitude axis, then a non-linearity, such as limiting, is suspected. If either peak shows a significantly larger number of values, then clipping is indicated.

Conclusion

The three domain views provide a three-dimensional interpretation of the analyzed waveform. If the distortion is large enough, it is visible as asymmetries and discontinuities, as exemplified by the step in the time-domain zoom trace. Typically, significant distortion does not necessarily produce visible anomalies in the time-domain view.

The increased harmonic levels in the FFT provide a good indicator of any distortion, but it doesn’t indicate the specific type of distortion. The statistical view in the histogram provides information about the type of distortion.

Arthur Pini is a technical support specialist and electrical engineer with over 50 years of experience in electronics test and measurement.

Related Content

• Basic oscilloscope operation
• Understanding FFT vertical scaling
• Analyze noise with time, frequency, and statistics
• FFTs and oscilloscopes: A practical guide
• How to perform histogram analysis on your oscilloscope

The post Using an oscilloscope’s time, frequency, and statistical measurement domains appeared first on EDN.

PicoJool Inc of Palo Alto, CA, USA (which is developing optical chips and modules for high-bandwidth, low-cost connectivity in hyperscale AI data centers) is introducing its 200G vertical-cavity surface-emitting laser (VCSEL) products, with a bandwidth exceeding 37GHz. The firm will begin sampling chip-level products in third-quarter 2026, including quad 100G, quad 200G and 32x50G NRZ micro-VCSELs for slow and wide applications. PicoJool says that it is already working with system startups and hyperscalers to define the next generation of pluggable, near-packaged optics (NPO) and co-packaged optics (CPO) solutions for AI data centers...

• Industrial-grade vibration sensor delivers the latest wide-bandwidth and dynamic range sensing.
• Intelligent sensor processing unit (ISPU 2.0) inside the sensor boosts signal processing and edge AI performance while reducing energy consumption.
• Provides the first compelling alternative to piezosensors for condition monitoring, combining performance, lightweight design, ease of integration, ultra-accuracy, and energy efficiency.

A global semiconductor leader serving customers across the spectrum of electronic applications introduces an intelligent vibration sensor designed for industrial condition monitoring that requires high accuracy, reliability, and energy efficiency.

Built using ST MEMS (Micro Electromechanical Systems) technology, the IIS3DWB10IS vibration sensor with intelligent sensor processing unit (ISPU 2.0) brings advance digital signal processing and AI inference closer to the sensing element. The result is a compact, rugged device that measures vibrations and shocks up to 200g at frequencies of 10 kHz and above. Combining digital precision and ease of use with a wide temperature range up to 125°C to withstand harsh conditions, the vibration sensor is engineered to help customers improve equipment uptime, reduce unplanned downtime, and support predictive maintenance strategies across industrial environments.

Vibration analysis is the dominant segment in condition monitoring, as many industries use rotating and oscillating machinery for cutting, shaping, moving, cooling, and other processes. The ability to prevent equipment stoppages through early detection of issues, such as predicting bearing failures in advance, helps companies across all sectors, including automotive and other manufacturing activities, to optimize production flow.

“Our industrial MEMS vibration sensor delivers the dynamic range and bandwidth needed for high-end applications and extends the advantages of ST in-sensor digital processing. Integrating the ISPU 2.0, with its new hardware accelerators for fast signal processing and AI inference, sharpens equipment-wear recognition while reducing latency and power consumption,“ said Simone Ferri, APMS executive VP MEMS sub-group. “Industries can expect a new generation of condition monitoring sensors, the first compelling alternative to piezosensors, that is lightweight, easy to fit and design, ultra-accurate, and energy efficient enough for battery-powered operations.”

“The IIS3DWB10IS delivers unique properties for our target markets and environments. Its high dynamic range, wide bandwidth, and high-temperature capability, combined with ease of adoption and a cost-effective, simplified circuit design, allowed us to replace the incumbent piezosensor technology. Moreover, the integrated ISPU 2.0 processor positions complex signal processing and rapid AI inference close to the sensing element, enabling smarter system responses,” said  Andrea Torcelli, Chief Technology Officer at Bonfiglioli S.P.A.

By enabling predictive and prioritizing maintenance, remote condition monitoring allows companies to improve equipment uptime and operating efficiency while eliminating unexpected failures and enhancing safety. Fortune Business Insights states the global market for this technology will exceed $5 billion by 2032, growing at over 9% CAGR1.

 

Further technical information:

The IIS3DWB10IS vibration sensor is the first digital sensor with wide bandwidth and embedded processing to deliver performance meeting the needs of high-end industrial condition monitoring applications, offering a compelling alternative to piezoelectric sensors.

Accurate measurement of vibrations above 10 kHz, with a large dynamic range up to 200g, combines with a noise floor as low as 35 µg/sqrt(Hz). This is comparable to the noise performance of piezoelectric sensors. Moreover, the IIS3DWB10IS delivers equivalent accuracy and sensitivity, adding digital-sensing advantages including smaller size, lower power consumption, simplified electrical and mechanical design, and greater flexibility in the computational partitioning.

ISPU 2.0 (Intelligent Sensor Processing Unit) introduces new hardware accelerators to perform real-time signal processing and AI at the edge. These hardware accelerators make frequently used functions faster and more power-efficient. The core is C-programmable and contains on-chip program and data RAM.

The supporting ecosystem provides software libraries that facilitate executing typical vibration monitoring algorithms in the ISPU, including FFT, filtering, envelope, velocity severity, and anomaly detection. With 40 MIPS and 40 MFLOPS digital signal processing, the ISPU 2.0 delivers up to four times the processing performance of the previous generation. In addition, the ISPU 2.0 sensor interface supports six times faster data transfer with the MEMS circuitry.

The IIS3DWB10IS also contains a 2048×80-bit FIFO register and an accurate temperature sensor. The sensor’s rugged MEMS-based design supports operation up to 125°C. The IIS3DWB10IS is supported in ST’s 10-year industrial longevity program. The IIS3DWB10IS is a 4.5 mm x 4.5 mm x 1.5 mm 16-lead LGA package with wettable flanks that facilitate automatic optical inspection in high-quality surface-mount assembly processes. The product is scheduled to be available by July 2026 from $25 for orders of 1000 pieces. 

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