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Now, India is about to move a further step ahead in enhancing its airborne surveillance and monitoring with the development of Airborne Early Warning and Control (AEW&C) Mk II or Netra Mk II. Under the programme, six Airbus A321 aircraft will be converted into sophisticated airborne surveillance aircraft. Reports suggest that DRDO has inked a contract with the aviation giants to get the jets converted as advanced Airborne Early Warning and Control aircraft, as per the Defence Analysis Wing of India’s Defence Ministry.

These new aircraft are supposed to carry advanced electronic warfare systems which are also capable of detecting and tracking aerial targets at high altitudes and from large distances. Equipped with highly capable radars and state-of-the-art electronic sensors, such platforms allow commanders to expand their real-time battlefield awareness and to effectively command coordinated counter-attack actions.

Electronic Age of warfare: “With the production of this aircraft, we would reduce our dependence on imported advanced electronics for such applications and achieve indigenisation”. Said by Mr R.N. Murali, Director. R&D facility, India. With the development of Netra Mark II, electronics will play just as important a role as our traditional weapons. Improved radars, data link, secure radio, processing capability & C2 system. The technology has to be a force for our country.

The programme is poised to enhance India’s indigenous air surveillance capability, enabling it to quickly respond to developing situations, and improving sky surveillance.

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India is rapidly developing solutions for this threat of drone swarms and unmanned aerial systems that are proving to be a major problem for troops on modern battlefields. Its own drone counter system now incorporates radar and electro-optical and infrared sensors together with radio frequency detection and electronic warfare systems.

Through this technology a defence force should be able to not just detect and identify a drone, but also monitor it and determine an appropriate response. For example, radar can detect drones as soon as they enter the operational area, then other better sensors can be used to corroborate a possible threat. Defensive electronic warfare devices may also be able to jam the drone’s navigation or communication system.

AI is predicted to have even a greater responsibility and help humans understand what they detect much faster, especially because AI processes sensor data. This includes detecting whether it is a bird or an insect etc. And identifying which is threatening amongst several targets, etc.

As drone technology becomes a cheaper alternative for even those with limited budgets, it’s telling how much New Delhi’s priorities to tech have turned to ‘state-of-the-art counter-drone electronics’ which, after all, seems like it could be another front on which to engage any future enemy; after all, the ‘next-gen battlefield might be determined not so much by firepower, but by those capable of finding targets the quickest, processing information the best, and fighting the smartest.

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New EV Policy 2026 Announced BY THE DELHI GOVERNMENT FOR THE NATIONAL CAPITAL Delhi’s new Electric Vehicle (EV) Policy 2026 is set for a radical change for its citizens who would be encouraged to switch to cleaner ways of transport, predominantly through the use of Battery Electric vehicles (BEVs) in the national capital. With a proposed outlay of INR 15,000 crores across a period of 4 years, the policy approved by the Delhi Cabinet and implemented by July 1, 2026, promises to further drive the agenda for zero- emission-based commuting, keeping in mind the city’s alarming and growing problem of air pollution.

To ensure a smooth subsidy process, another major initiative that comes with this updated policy is the introduction of the Delhi EV Subsidy Portal. The portal allows successful EV buyers to apply online for purchase and scrappage incentives, monitor application status and directly receive subsidized benefits through the Direct Benefit Transfer (DBT) system. The portal was introduced to make the subsidy process more transparent, accessible, and efficient for EV buyers.

This new policy marks a substantial boost in Delhi’s initiative to promote electric mobility. The state government is set to spend Rs 15,000 crore under the scope of the policy that will be effective until March 31, 2030. Much of the anticipated investment is set to support EV incentives, infrastructure charging support and other schemes geared towards creating a comprehensive EV ecosystem.

Delhi’s new INR 15,000-crore EV Policy 2026 represents one of the most ambitious state-level efforts in India to accelerate the transition towards electric mobility. By combining purchase subsidies, scrappage incentives, tax exemptions, charging infrastructure expansion, technology-based eligibility requirements, and phased registration measures, the policy seeks to create a comprehensive framework for increasing EV adoption.

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Govt Approves Establishment of 2 New Electronics Manufacturing Clusters in Tamil Nadu, India to Boost Electronic Manufacturing Ecosystem. A further boost to the indigenous electronics manufacturing ecosystem has been given today. Government of India approves the setting up of two new Electronics Manufacturing Clusters (EMCs) in Tamil Nadu. A total outlay of Rs 1012 crore will be put into developing these EMCs, which will be constructed at Manallur and Pillapaikkam, creating a push towards industrial infrastructure development and attracting electronics manufacturers.

Union Minister for Electronics and Information Technology Ashwini Vaishnaw announced the approval through a written reply in the Lok Sabha on July 22, 2026. Under the two projects, the two industrial locations to be created will be spread over 850 acres, and will house units operating in diverse segments of the value chain of electronics companies.

Tamil Nadu State Electronics Manufacturing centres are one of the major centres in India in terms of electronics investment. With such investments, the state emerged as top hub in terms of investment and production in electronics manufacturing especially mobile phone manufacturing, assembly and automotive electronics manufacturing, and their supporting industrial sector. Manallur and Pillapaikkam EMC’s, after approval by GOI, might consolidate the existing manufacturing base while enabling the set up and expansion of new companies by Indian as well as foreign companies.

The approval of the Manallur and Pillapaikkam Electronics Manufacturing Clusters represents another important development in India’s effort to strengthen domestic electronics production. With a combined project cost of approximately ₹1,012 crore and a total area of more than 850 acres, the two clusters will add new manufacturing infrastructure to Tamil Nadu’s already significant electronics ecosystem.

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On 23 July, the Vermont Gallium-Nitride (V-GaN) Tech Hub hosted an open house to showcase its new Test and Characterization Facility (TCL), which is described as a critical resource for accelerating the transition of advanced semiconductor technologies from development to commercial deployment...

Since the development of power diodes and thyristors in the 1950s, silicon has been the dominant material for power electronics across applications ranging from electric vehicles to wind turbines. However, the emergence of wide-bandgap semiconductors such as silicon carbide (SiC) and gallium nitride (GaN) has enabled industry to push to higher voltages and smaller form factors while increasing efficiency and maintaining reliability. At the same time, early-stage research into the next generation of semiconductor materials, ultrawide-bandgap (UWBG) semiconductors, threatens to disrupt this space further...

A Chinese research team has achieved consecutive breakthroughs in gallium nitride (GaN) heterojunction bipolar transistors (HBTs), with results published in IEEE Electron Device Letters (IEEE EDL) in both 2025 and 2026. The 2026 paper was selected as an Editor’s Pick, marking a transition for GaN HBTs from frequency characterization to practical power application evaluation...

StraitsMicro, a Singapore-based deep-tech semiconductor product development and solutions company, is unveiling Visora, its sovereign Camera System-on-Chip (SoC) family, at an exclusive pre-silicon demonstration. Visora serves as the core processing engine for CCTV cameras and is designed as a secure, indigenous silicon alternative, addressing the gap created by the Government of India’s restriction on Chinese SoCs in surveillance hardware. Positioned as India’s sovereign surveillance SoC family, Visora is built for government, defence, smart-city, and critical-infrastructure use across India and global markets.

The company is taking its proof-of-concept to market through a series of three showcase touchpoints, supported by partners Proxelera (Bengaluru-based design partner), Aqtronics (distributor), with the India-Singapore semiconductor partnership as a supporting narrative.

Commenting on the demonstration, Mr. Pankaj Sharma, Founder & CEO, StraitsMicro, said, “Today marks the successful pre silicon validation of our indigenous CCTV Camera Edge AI SoC architecture. This reflects our commitment to developing trusted, secure and intelligent semiconductor solutions for surveillance and other applications for the Indian and global market. Our aim is to build a globally competitive semiconductor company leveraging India’s talent and strengths in design and Singapore’s capabilities and prowess in fabrication, manufacturing, quality and reliability engineering for semiconductors. With India as a major innovation and development hub duly complemented by Singapore with a robust semiconductor ecosystem, we look forward to working with government, industry, customers and partners to build relevant and trusted semiconductor solutions. This is only the beginning of our product and solutions roadmap. We welcome strategic partners and customers to join us on this exciting journey.”

The event featured a live FPGA-based Camera SoC demonstration, showcasing proposed AI features, security architecture, and performance. The Visora roadmap spans three products for CCTV and one product for Network Video Recorder (NVR). The entry-level Visora Edge supports video up to 5MP at 30fps for residential cameras, retail security, small and medium businesses and other cost-sensitive IP-camera applications. The mid-range Visora Secure supports up to 8MP at 30fps, an integrated AI accelerator and advanced low-light imaging for commercial surveillance, industrial applications, smart cities, traffic monitoring, railways and metros. The high-end Visora Pro scales to 4K at up to 120fps and can support up to eight cameras for defence, border security, safe-city projects, airports and other critical infrastructure. The Visora Network SoC for NVRs completes StraitsMicro’s trusted surveillance semiconductor platform by extending hardware-rooted security from the camera to the network, ensuring secure video processing, storage, and transmission while mitigating cyber threats and data leakage across the surveillance ecosystem.

Across the family, the proposed architecture combines an ultra-low-power multicore 64-bit CPU with hardware-accelerated AI, low-power DDR5, and H.265 video encoding, delivering very high compression. The frame-to-stream imaging pipeline incorporates multi-exposure HDR, motion-compensated 3D noise reduction, wide-angle and fisheye distortion correction, and on-chip lossless buffer compression that can reduce memory-bandwidth demand. Depending on the model, edge-AI functions range from motion and human detection to crowd analytics, facial recognition, behaviour analytics and advanced edge inference.

Mr. KT Chan, Director – Services & Partners, StraitsMicro, added, “Having spent three decades in the semiconductor industry, I believe trusted semiconductor technologies will play a critical role in the future of secure AI semiconductor solutions. StraitsMicro combines extensive experience, leadership, strong technical skills and capabilities, an innovative product development approach and international partnerships with worldwide reach to create semiconductor products and solutions in India with global relevance. Our goal is not only to develop world class semiconductor solutions but also to contribute to a trusted and resilient semiconductor ecosystem. We thank all our customers and partners for their support and look forward to creating lasting value together.”

StraitsMicro’s approach centers on fostering the electronics and semiconductor ecosystem through the establishment of a Semiconductor Development Hub for indigenous new products through co-creation; and providing value addition to domestic fabless semiconductor companies to help them build indigenous products, a holistic approach to developing the electronics and semiconductor ecosystem, spanning both the domestic and global markets.

 

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Kia India has added the Kia Syros EV, a compact electric SUV designed for India, to its EV line-up. The car carries a base price of ₹13.49 lakh (ex-showroom) and boasts a maximum ARAI-certified range of 526 km, as Kia strengthens its portfolio in India’s EV landscape. Deliveries of the Kia Syros EV will begin from July 30, 2026, across the brand’s dealerships.

The introduction of this vehicle marks a critical development in Kia’s objective to accelerate the pace of electrification and bring it into the reach of more and more Indian buyers. The Syros EV would be a compact SUV that integrates driving range, connectivity, driver-assistance technology, and practical urban dimensions as a complete package, derived from the existing Syros body style but features EV-specific modifications, a different front-end styling, an external charging port and a front trunk.

A key highlight of the vehicle is its battery and range capability. The larger 51.4-kWh battery pack provides an ARAI MIDC-certified range of up to 526 km, placing the Syros EV among the long-range options in its segment. Kia also offers two battery options, allowing customers to choose between different combinations of range, performance, and price. The company claims that the vehicle can be charged from 10% to 80% in approximately 39 minutes using a 100-kW DC fast charger under standard test conditions.

Launched at a time when there is already high competition in Indian electric subcompact SUV market. SyrosEV will compete with leading and well-established electric contenders in India such as Tata Motors & Mahindra. Combined with its small footprint as well as 500 km range claims, the car gets packed features and ownership options to stand out from the competition in the segment. As buyers are most anxious about charging options, range, battery warranty, & driving cost.

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Engineers are redefining energy by looking not at massive grids but at the overlooked flows around us. Rain gutter generators that channel storm runoff, tap-mounted turbines spinning with household water, and balcony-scale wind turbines catching urban breezes prove that power can be harvested wherever motion exists.

These micro power generators embody the spirit of engineering empowerment, transforming ordinary infrastructure into sustainable energy assets. By designing systems that thrive on the smallest currents, engineers are not just solving technical challenges; they are enabling a future where autonomy, resilience, and sustainability are built into the everyday fabric of life.

Harnessing gravity: Micro hydro power

You don’t need a colossal dam to tap into hydroelectricity—gravity and flowing water are enough. Whenever water moves downward, whether from a rooftop gutter or a household faucet, it carries kinetic energy that can be captured and converted into usable current.

Micro hydro systems thrive on small vertical drops, known as “head,” which create surprising pressure even in everyday settings. A rain gutter turbine, often built around a miniature Pelton wheel, can be placed at the base of a downspout so that rainfall from a two-story home delivers enough head to charge an outdoor battery bank, turning stormwater into renewable energy storage.

Faucet hydros, on the other hand, are pocket-sized turbines that screw directly onto sinks or showerheads, producing between 5-V and 12-V DC—the perfect range for powering smart water temperature displays, LED bathroom lighting, or other low-voltage gadgets. Together, these simple setups prove that even the smallest streams of water can be harnessed to generate clean electricity, making hydro power accessible at the scale of everyday living.

Figure 1 Micro-hydroelectric power generators convert kinetic energy from small water streams into sustainable electrical power. Source: Author

Catching the breeze: Urban wind

Just as falling water can be harnessed for energy, moving air offers another everyday source of clean electricity. Standard windmills are massive, but compact vertical axis wind turbines (VAWTs) are reshaping the landscape for residential use. Unlike the towering three-blade giants on hillsides, these turbines resemble kinetic sculptures, blending into urban settings while quietly generating power.

Their design makes them safer for birds, more tolerant of turbulent wind bouncing off fences or house walls, and ideal for small spaces where airflow is unpredictable. With the ability to charge 12-V batteries, they provide reliable energy for garden sheds, security cameras, or other low-voltage systems, proving that even the breezes swirling through neighborhoods can be transformed into practical power.

Figure 2 Mini wind turbines harvest kinetic energy from turbulent urban breezes to provide localized renewable power. Source: Author

Harvesting the invisible: RF and Wi-Fi

If water and wind can be turned into electricity, why not the invisible waves that surround us every day? It may sound like science fiction, but it’s pure physics: electromagnetic energy from routers, cell towers, and radio stations constantly fills the air. RF energy harvesters capture this ambient power using a specialized antenna called a rectenna, which converts radio frequency signals into direct current. The output is small—usually measured in microwatts (𝜇𝑊)—but it’s enough to sustain ultra-low-power devices.

Imagine a moisture sensor in your garden that never needs a battery because it feeds on the Wi-Fi signal leaking from your window, or a network of “batteryless” sensors quietly monitoring conditions without ever needing replacement. By tapping into the invisible spectrum, RF harvesting extends the idea of micro power generation into the realm of everyday signals, proving that even the unseen can be harnessed for sustainable living.

Figure 3. The AEM30940 PMIC manages energy extraction from piezoelectric, micro-turbine, or high-frequency RF sources. It simultaneously charges a storage element while providing two independently regulated output voltages to power system components. Source: e-peas

Power from difference: Thermal energy

Just as water and wind can be harnessed for electricity, temperature itself can drive power generation through the Seebeck Effect. When one side of a material is hot and the other is cold, electrons begin to move, creating a voltage difference that can be captured as usable current.

This principle is already at work in stove-top generators found in many off-grid cabins, where a thermoelectric fan sits with its base on a hot wood stove and its top cooled by surrounding air. The temperature gradient produces enough electricity to spin the fan, circulating warmth throughout the room without external wiring.

On a smaller scale, wearable thermoelectric generators (TEGs) are emerging as a way to harvest body heat, powering fitness trackers and other low-power devices directly from the warmth of your skin. By turning everyday temperature differences into electricity, thermal energy harvesting extends the reach of micro power generation into both rustic cabins and modern wearables, proving that even the contrast between hot and cold can be transformed into sustainable current.

Figure 4 Stove-top thermoelectric generators convert waste heat into usable electricity. Source: TEG

Sunbeams to volts: The “magic” of micro-solar

At its heart, solar is the only micro-generator that feels like literal magic: it has zero moving parts, no loud turbines, and it runs on nothing but daylight. The fundamental “trick” is simply catching photons to knock electrons loose, creating a silent flow of power. Today, this technology is defined by “energy independence in a box,” where ultra-portable power stations—utilizing long-lasting LiFePO4 batteries and AI-driven energy management—allow anyone to build a personal power grid in minutes.

We’ve come a long way from the flimsy calculators of the 90s. From high-efficiency bifacial panels that harvest light from both sides to the emergence of perovskite-silicon tandem cells that pack 25% more power into the same small footprint, solar micro-generators provide a fuel-free alternative to traditional engines.

Whether it’s a balcony-mounted micro-inverter system or a foldable camping mat, solar is no longer just a “green” alternative; it’s the most reliable, scalable tool for decentralized power in our modern world. It’s basically like having a tiny, silent utility company that you can carry in your backpack.

Figure 5 N-type TOPCon dual-glass bifacial solar panels maximize energy harvesting by capturing incident sunlight on the front surface while simultaneously absorbing reflected light from the rear. Source: Author

Power of a pulse: Stepping into piezo power

While solar catches light, piezoelectric generators catch movement. The fundamental principle is almost toy-like in its simplicity: certain materials, like specialized ceramics or crystals, generate an electric spark when you squeeze or deform them.

In the world of micro-generation, this means turning everyday “wasted” energy—like the thud of a footstep, the vibration of a passing train, or even the pulse of a finger on a keyboard—into usable volts. Today’s technology has miniaturized this into “energy harvesting skin” and thin-film polymers that can be embedded into everything from smart sneakers to bridge supports.

Unlike solar, which needs the sun, or wind, which needs a breeze, piezo power only needs action. It’s the ultimate “hidden” generator, silently sipping energy from the vibrations of the world around us. While a single “squeeze” might only power a tiny sensor or a wireless signal, scaling this tech into “smart floors” or wearable fabrics is turning the human body and our infrastructure into a living, breathing power plant. It’s the fundamentals of physics turned into a literal “walk in the park” for renewable energy.

Figure 6 Cantilever piezoelectric harvesters convert mechanical strain from bending and vibrations into usable electrical energy. Source: Smart Material

Designing lean systems for ultra-low power

For engineers and makers, the frontier of micro power isn’t just about capturing energy; it’s about designing lean, ultra-low-power systems that thrive on the tiniest trickles of current. By leveraging efficient voltage regulators, sleep-mode microcontrollers, and energy-aware communication protocols, you can stretch microwatts into meaningful work.

Smart design tricks—like duty-cycling sensors, harvesting capacitors for short bursts, and matching generator output to the load—transform fragile prototypes into reliable systems. Today’s ecosystem of modular rectennas, plug-and-play thermoelectric modules, and ultra-low-power ICs makes experimentation easier than ever, giving designers the tools to tailor micro power generators for domains ranging from smart homes to wearables.

Power your world with micro generators

Today’s maker landscape is rich with possibilities: micro hydro turbines, mini vertical-axis wind kits, piezo energy harvesters, and even RF harvesting modules are widely available online, often bundled as DIY systems that simplify setup for hobbyists. Many components—Pelton wheels, turbine housings, and airflow vanes—can be 3D-printed from open-source designs, making customization affordable and accessible.

Dedicated ICs such as ultra-low-power boost converters, energy harvesting PMICs, and rectifier-regulator modules are designed to stabilize and store trickle currents, while plug-and-play thermoelectric generators extend experimentation into thermal domains. With kits, printable parts, and specialized electronics at hand, building micro power generators across water, wind, signal, heat, light, and vibration/impact sources has become a practical weekend project rather than a distant engineering challenge.

The possibilities are here and the tools are ready—so why wait? Shock your imagination, spark your designs, and start building micro power generators that turn everyday forces into lasting energy solutions.

T. K. Hareendran is a self-taught electronics enthusiast with a strong passion for innovative circuit design and hands-on technology. He develops both experimental and practical electronic projects, documenting and sharing his work to support fellow tinkerers and learners. Beyond the workbench, he dedicates time to technical writing and hardware evaluations to contribute meaningfully to the maker community.

Related Content

• Micro Hydro Generator
• Energy Harvesting Block Diagram
• Micro-Harvesting Will Not Power Our Planet
• What’s Happening in the World of Micro-Energy Harvesting?
• Platform design for testing vibration to electrical power generators

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🏠 Про поселення на 2026/2027 навчальний рік kpi пн, 07/27/2026 - 10:00

The display runs on dual voltage (120VAC and 12VDC) Has a BCD input. Does 7 segment decoding with lightbulbs and some odd ceramic plate with black squares. These also run at mains voltage and switch some transistors. I’d make a schematic, but I have no idea how this tech works. Thought you’d all appreciate it. submitted by /u/aspie_electrician [link] [comments]

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The market for commercial autonomous vehicles (AVs) is poised for explosive growth over the coming decade, and 4D imaging radar has a key part to play. 4D radar, which offers a 4D view combining distance, velocity, position, and vertical resolution, will help AV companies deploy autonomous fleets in real-world environments faster while also building the potential to scale such deployments rapidly.

The autonomous truck market alone is set to rocket from $50.8 billion this year to $158.7 billion in 2035, at a compound annual growth rate of 13.5%, according to a research report by MarketsandMarkets. With technology the key driver of growth, according to the researcher, the adoption of advanced sensors such as 4D radar, alongside high-performance computing platforms and AI-based software, is vital to this expansion.

However, one of the key challenges facing the sector is that 4D radar solutions have, until now, tended to operate as closed systems, meaning that access to the raw data is limited. Newer systems, such as bitsensing’s AIR4D imaging radar, will help enable developers and AV companies to continuously refine vehicles’ perception models and validate their performance.

In turn, this will accelerate the path from testing new systems to safe and large-scale deployment in real-world fleets. This will drastically speed up the commercialization of AVs worldwide.

In contrast to sensors such as LiDAR and camera sensors, radar offers key advantages that will be vital to driving real-world use in the commercial vehicle sector. It is safe, cost-effective, and proven, and it is already widely incorporated into advanced driver-assistance systems (ADAS) to offer the velocity accuracy needed for ADAS functions such as automatic emergency braking. This is a well-known technology and already evolving into more advanced 4D systems, suited for commercial vehicles.

Radar systems work in all weather conditions (cameras, for example, struggle in fog and low-light conditions as well as over longer ranges). The latest radar systems work comfortably at ranges of more than 200 meters and have low power consumption. The technology can easily be integrated into vehicle systems, with manufacturers already building systems designed specifically for the commercial AV market.

4D radar delivers high-resolution, real-time environmental mapping and integrates with cameras to deliver a comprehensive perception system. (Source: Adobe Stock) The 4D advantage

The reason 4D radar is so important for the rapid commercialization of AV technology is that it enables the rapid classification of different kinds of road users (for instance, pedestrians, buses, and cars). This will play an important role in enabling trucks, buses, and robotaxis to move safely through city streets, whether in Level 2 or 3 autonomy (where driving is conditionally automated) and moving toward Level 4 autonomy (where driving is highly automated, with vehicles capable of driving fully autonomously in real-world settings without the assistance of a human driver).

The reason 4D radar is so powerful is that it instantly senses distance, velocity, and position, along with vertical resolution. This means that anything “seen” by the vehicle has not only movement but also shape and altitude. This allows vehicle systems to sense how quickly an object is moving and rapidly categorize it as a certain class of vehicle, such as a motorbike or truck, or a pedestrian.

The rapid adoption of 4D radar will be a key growth driver in commercial AVs. Today, some robotaxis already ship with more than 20 advanced 4D sensors, and this will become a key trend across the market for commercial vehicles. Analysis by ResearchAndMarkets found that 169 million radar sensors shipped globally in 2024, translating into 0.8 long-range radars per vehicle and rising to one per vehicle by 2030.

The adoption of regional regulatory mandates (such as the EU’s Vehicle General Safety Regulations) is also helping to accelerate the growth of commercial AVs. The latest radar sensors offer both horizontal and vertical resolution, enhancing obstacle-detection and collision-avoidance capabilities. This means they can cope with any road conditions and any weather conditions, complying with the new regulations.

Built for commercial vehicles

To really drive the commercial AV market forward, it’s also vital that sensors are purposely designed for full autonomy, rather than being repurposed from devices for the consumer market. Today, many 4D radars were developed for use in ADAS, rather than being built from the ground up for full driverless functionality.

To truly deliver the information that AVs need, these systems should be optimized to deliver 4D sensor data directly to the AI models in these vehicles. They should also be optimized for power and heat efficiency. These features will be vital for real-world operation.

Going forward, a camera-plus-radar architecture will also be crucial to offering a viable path to curbing per-vehicle sensor costs. This will help to drive faster AV deployment on roads around the world. These are some of the design factors that we have also considered with our own work, including with the AIR4D imaging radar.

The AIR4D imaging radar is purpose-built for AVs, which is critical for full autonomy. (Source: bitsensing Inc.) Increasing accuracy

The latest radar sensors build on the strengths of the technology to offer higher performance than rival sensors, such as LiDAR and cameras, with long-range detection up to 300 meters and the ability to operate in near-total darkness. This allows commercial vehicles to maintain awareness even on poorly lit roads in the middle of the night.

The ability to measure direct velocity per object is also helping to enable faster and more accurate decision-making, with the latest radar sensors able to measure the speed and direction of vehicles, cyclists, and pedestrians in real time. This means that radar alone can provide full spatial accuracy. With previous generations of 3D radars, other sensors were relied on to create a “full” image of the objects moving in the surrounding environment.

Today, AVs equipped with 4D radar can build a high-resolution, real-time spatial picture of their environment across all four dimensions. This is what safe autonomous driving demands. With 4D radars penetrating even snow and rain and able to integrate with cameras, radar is the foundation of a comprehensive perception system, which will be the building block of autonomous driving.

Toward safer bus fleets

There are many factors that make radar sensors appealing in a commercial context, especially the “weather-proof” nature of the technology. Commercial fleets, such as the use case of buses in Korea, are already adopting radar-based technology through initial pilot schemes, with further plans to expand fully to intercity bus routes.

Critically, these ADASes have modularity at their heart, with features that can be easily added to existing vehicles. These functions, such as forward-collision warning, enable buses to precisely detect vehicles and pedestrians, even in the most demanding environments or roads.

A 4D future

The dawn of the commercial AV era is upon us today, and to drive forward into this future, it’s clear that 4D imaging radar has a vital role to play. Not only will 4D radar help to overcome the limitations of previous sensors, such as LiDAR and cameras, but it also transcends the limitations of previous radar systems, with the latest sensors purpose-built for seamless integration into the fleets of tomorrow.

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Just practiced to desoldering some SMD components(at least not THD, thanks gods). However I noob in SMD, but I love it! Very fast, easy and beautiful soldering using hot air fan. submitted by /u/IvanIsak [link] [comments]

Keysight Technologies (NYSE: KEYS) today announced Keysight Multiphysics, a design and verification solution that addresses the physics interactions driving failure in modern electronic designs. The structural analysis application covering drop, shock, and vibration enables engineering teams to identify and fix problems earlier, before a prototype is built.

Electronic products are growing in complexity faster than traditional engineering workflows can scale. As electrical, thermal, mechanical, and optical elements are compressed into tighter, more integrated designs, the physics interactions between them create failure risks that cannot be evaluated in isolation. Physics effects in one domain can produce unintended outcomes in another, and those interdependencies are rarely caught until the physical product is built, when the cost of redesign is highest and projects often miss deadlines and exceed budgets.

Keysight Multiphysics integrates physics simulation into the electronic engineering workflow, completing in hours a process that traditionally takes weeks. The first release addresses structural analysis and includes compliance simulation for drop, shock, and vibration. Previously, this step required building numerous physical prototypes for testing in an external lab, committing design and manufacturing tooling before identifying potential failures. Pre-built application templates embed setup expertise directly into the workflow, improving simulation fidelity.This allows teams to avoid late-stage failures without requiring a computer-aided

Key application benefits:

• Faster time to insight: Simulation-driven development helps teams reduce physical prototype iterations and identify reliability issues earlier in the design cycle.
• Lower redesign cost: Drop, shock, and vibration simulation enables engineers to locate where failures originate and make targeted corrections earlier in development.
• Increased design confidence: An application-specific database, expanded to include modern electronic materials, helps engineers model component behavior under realistic operating conditions.
• Broader access to simulation: A guided workflow interface embeds application expertise for each use case directly into the process, enabling engineers to confidently evaluate product reliability without specialist CAE skills.
• More time for engineering: Automated setup workflows eliminate manual configuration tasks traditionally required for structural simulation.
• Accelerated regulatory sign-off: Built-in compliance workflows support MIL-STD, IEC, and JEDEC standards for shock, drop, and vibration.

Niels Faché, Senior Vice President, Keysight Design Engineering Software, said: “Complexity now defines electronic design. Engineers used to treat electrical, thermal, and mechanical effects as separate problems. That approach can no longer keep pace. We built Keysight Multiphysics by working through the very problems our own engineers faced, giving teams a digital thread to detect failures earlier and more predictably.”

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Have you heard of the golden ratio? Well, what about the gold-colored guitar fret ratio?

I’ve been listening lately to classical guitar musicians on YouTube. Such skill and artistry is utterly astonishing. After a while, though, I got curious about how the guitars were made and how they achieved their frequency outputs. I noticed something. I took a screen shot of a guitar’s strings and fretboard and, by counting pixels, I measured the dimensions seen in Figure 1:

Figure 1 Guitar fret positioning is definitely not random, acoustically speaking.

I then looked at the ratios of a string’s fret-to-base length (my choice of term) to that of the next shorter one (Figure 2):

Figure 2 Length ratios: the ratio of each fret position taken in pixels divided by that of the next fret closer to the base is the ratio of the frequencies of each note of the string. That ratio is nominally 2^(1/12) =1.05946… which is approximated in each and every case. The average of the calculations as shown here comes to 1.058422 which is only 0.1% in nominal error.

I discovered that in spite of my crudeness in using the pixels, the ratios come out very close to the twelfth root of two. That ratio is the ratio of adjacent note frequencies of a tempered musical scale. If the full length of a string is taken as “Do” in its particular key, the fret positions yield the twelve-tone-scale arrangement of notes seen in Figure 3. In hindsight, I guess I should have intuitively known this but I didn’t. I do now.

Figure 3 Tempered scale: taking the full length of each string as the note “Do” as in Do-Re-Mi-Fa-Sol-La-Ti-Do scaling, we see how each fret position corresponds to one of the twelve notes (including sharps and flats) of the Western culture’s twelve-tone scale.

It should be noted that singer Jimmie Rodgers once admitted that he couldn’t really play the guitar as he performed, so he tuned the six strings of his guitar to be in open string harmony. Then when he was performing, he would keep one finger, his thumb, across all six strings at the same time across the fretboard. Since all six strings followed the above length versus note pattern, the six strings were always in harmony. He was using a single, movable chord.

Watch how his left hand does that in the following YouTube videos and enjoy the music.

John Dunn is an electronics consultant and a graduate of The Polytechnic Institute of Brooklyn (BSEE) and of New York University (MSEE).

Related Content

• Earplugs ready? Let’s make some noise!
• A pitch-linear VCO, part 1: Getting it going
• A pitch-linear VCO, part 2: taking it further

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In a breakthrough that will power the nation’s aspirations in aerospace propulsion, the first Indian expendable turbojet engine in the 350-kg thrust class was successfully demonstrated and marks an important step towards India’s capabilities in developing advanced propulsion technology. Developed by the Gas Turbine Research Establishment (GTRE) of the Defence Research and Development Organisation (DRDO), the engine will pave the way for increased self-reliance on high-end propulsion technology for upcoming aerial platforms and other defence applications.

Hyderabad-based Azad Engineering that was chosen by GTRE as the industry partner for its manufacturing and assembly, delivered the engine to GTRE on July 22, 2026. This also marks the coming together of the Indian defence research infrastructure and the private sector for building the aircraft. While DRDO lends its in-house design expertise and research in this field, Azad Engineering provides the cutting edge in precision manufacturing, modern engineering, and tooling facilities to make this possible.

The newly developed 350-kgf-thrust-class expendable turbojet engine is expected to power future air-breathing platforms, including selected missile systems and unmanned aerial vehicles (UAVs) that require compact, lightweight, and high-performance propulsion systems. As a turbojet is an air-breathing engine, it uses atmospheric air as part of the combustion process to generate thrust. The development represents an important advancement in India’s indigenous aerospace and propulsion capabilities, as the design and manufacture of jet engines require advanced materials, precision engineering, highly accurate manufacturing processes, and stringent quality-control measures. The technology could strengthen India’s domestic propulsion ecosystem and support the development of future high-speed aerial platforms.

The successful development highlights the growing contribution of India’s private defence industry to major propulsion programmes. Through its role in the indigenous manufacturing and assembly of the engine, Azad Engineering demonstrates how precision-engineering companies are increasingly participating in the development of complex aerospace and defence systems. The 350-kgf-thrust-class expendable turbojet engine was manufactured and assembled in India by Azad Engineering based on the design and technology developed by the Gas Turbine Research Establishment (GTRE), a laboratory of the Defence Research and Development Organisation (DRDO). This collaboration reflects the increasing role of private-sector companies in supporting India’s efforts to develop advanced indigenous propulsion technologies.

The post India Develops Indigenous Expendable Turbojet Engine for Future Missile System appeared first on ELE Times.

Gallium nitride (GaN) power IC and silicon carbide (SiC) technology firm Navitas Semiconductor Corp of Torrance, CA, USA and South Korea-based Magnachip Semiconductor Corp (which designs and manufactures of analog and mixed-signal power semiconductor platform solutions) have announced a strategic partnership to accelerate adoption of SiC technologies in high-voltage (HV) and ultra-high-voltage (UHV) power markets...

Part 2 of this series covered the user-space tooling stack—cxl, ndctl, daxctl, numactl, lspci, and setpci—and walked the boot path from power-on through DRAM training, DVSEC and HDM reporting, decode programming, CDAT delivery, ACPI table handoff, and OS driver binding. It framed each stage as a validation gate so you can tell whether a failure is rooted in link training, capacity reporting, firmware tables, or policy—not only in application behavior.

Part 3 turns that framework into hands-on practice. You will learn how CXL memory may surface as system RAM or Device DAX, when to use daxctl and boot parameters such as efi=nosoftreserve, how to confirm expander memory as a distinct NUMA node, how to decode key lspci fields for link health and CXL.mem enablement, and how to drive targeted traffic with numactl and standard stress tools. So, you can separate transport defects from NUMA misconfiguration before closing bring-up or sign-off on CXL Type 3 device validation.

Integration modes: System RAM and Device DAX

CXL Type 3 host-managed memory may integrate in more than one way. The platform and kernel can expose it as conventional system RAM, or as persistent-memory-class capacity that surfaces as Device DAX character devices (for example /dev/dax0.0). The daxctl utility and libdaxctl can reconfigure those DAX instances; for example, switching a region to system-RAM mode so the same physical capacity behaves like normal DRAM instead of a raw DAX mapping, subject to firmware and driver support.

To reconfigure a device that appears as /dev/daxX.Y to system RAM:

sudo daxctl reconfigure-device –mode=system-ram daxX.Y

Firmware can mark some memory ranges in the system map as EFI “soft reserved.” Think of that map as the machine’s inventory of RAM, soft-reserved means, “this range exists, but do not treat it as ordinary free RAM yet.”

That pattern is common when capacity comes from persistent memory (PMEM) or CXL Type 3 expanders, because the platform often wants the OS to decide later whether that capacity should behave like normal DRAM or be exposed as a Device DAX mapping (a special character device such as/dev/dax0.0). By default, Linux honors those soft reservations, which leaves the memory set aside instead of freely handing it to applications as regular RAM.

The boot parameter efi=nosoftreserve changes that policy. It tells the kernel: do not keep soft-reserved areas reserved so the OS can bring that capacity online in the mode operators want (typically system RAM) when the firmware’s soft-reserve marking does not match the deployment goal.

Use efi=nosoftreserve only when your platform vendor or bring-up guidance says it’s appropriate. Applied without that context, it can change how capacity appears (RAM vs DAX), affect NUMA topology, and complicate debugging when firmware and OS expectations disagree.

Verifying NUMA topology

Use numactl to confirm the expander enumerates as its own NUMA node:

numactl -H

Figure 1 Sample numactl -H output on a two-socket system with 2 CXL devices, where each CPU is a NUMA node with native DRAM. Node 0 and node 1 show socket-local DRAM and the CXL devices appear as node 2 and node 3 with 128 GB of memory (each) and no local CPUs. This memory-only NUMA node pattern is common for Type 3 expanders and is the baseline for placement-aware testing. Source: Author

Initial sanity checks with lspci

lspci shows whether the CXL endpoint is present and reports vendor/device ID, class codes, PCIe link width and speed, and related DVSEC register status. It’s a fast first check before chasing firmware decode, driver bind, or memory-onlining issues.

lspci | grep -i cxl

lspci -s <BDF> -vvvv

Decoding key lspci fields

Device link width and speed

LnkCap and LnkSta should match expectations (for example speed 32GT/s, width x16). Unexpected degradation signals an unstable link and issues at the electrical layer. This must be resolved before proceeding further.

Figure 2 lspci output showing the negotiated PCIe link speed and width for a CXL Type 3 endpoint. Source: Author

CXL capabilities and status

CXL DVSEC blocks use Vendor ID 0x1E98 and a DVSEC ID identifying the structure type. A healthy device advertises both CXL.io and CXL.mem under CXLCap/CXLCtl. If CXL.mem is disabled (CXLCtl Mem-), possible causes include DRAM enumeration failure or the host failing to assign address space. HDMCount 0 is a red flag. When memory enumeration fails, verify DIMM compatibility and mounting, and use vendor SDKs to probe internal controller registers via out-of-band access where available.

Figure 3 CXL DVSEC capability and control fields showing CXL.io and CXL.mem enablement, HDM decoder configuration, and active memory ranges. Source: Author

Address range and Active bit

Device firmware can be set up to include the entire HDM in one range or split it into two. The range fields reflect the size and which range is active. Range fields should translate to the full HDM size with Valid+ and Active+ set. Otherwise, it indicates that DDR negotiation or mapping failed. For initial bring-up, set the decoder and mailbox timeout values to their maximum supported settings to avoid premature failures during DDR negotiation.

Driver and kernel modules

Kernel driver in use should be cxl_pci. To verify kernel version, kernel 6.3 and above are recommended. During link stability testing, unlink drivers as required by your test procedure.

The cxl CLI tool for CXL memory expander bring-up

The cxl command-line utility is the user-space front-end to libcxl, shipped with the ndctl project on most Linux distributions. It walks the kernel CXL sysfs hierarchy, which includes buses, ports, endpoints, memdevs, decoders, and regions and prints structured as JSON output.

It complements lspci, which shows transport and DVSEC state at the PCI layer, and daxctl or numactl, which show how onlined memory capacity is exposed to applications. Reach for cxl after dmesg if the firmware, CXL driver, and user-visible memory policy do not agree.

What cxl exposes

At a high level, cxl list reports the objects the Linux CXL core registers under /sys/bus/cxl/devices/; root buses, switch and root ports, endpoints tied to PCI functions, memory devices (mem0, mem1, …), host-managed device memory decoders, and regions that may span one or more expanders. For single-LD Type 3 cards, the first sanity check is usually whether a memdev appears with a non-zero ram_size, a host BDF, and decoders or regions in a committed decode_state after platform firmware has programmed HDM and asserted mem_enable.

Essential commands during bring-up and sanity testing

Initial discovery

Run these early in bring-up to confirm the kernel bound cxl_pci and registered at least one memdev:

cxl list -M

cxl list -M -u

Look for memdev entries with ram_size, serial, host (PCI BDF), and numa_node when memory is onlined. An empty list or zero-sized memdev often means the device is present on the bus but not yet consumable—trace back to HDM validity, decode programming, or driver bind before chasing application issues.

Topology and decoder verification

After link-up and driver bind, verify the decode path from root port through endpoint decoders:

cxl list -vvu

cxl list -D -d endpoint -u

cxl list -P -p switch,endpoint -m memX -u

Use -vvu for buses, ports, decoders, regions, and target mapping in one view. Filter by memX or by PCI BDF (cxl list -M -m 0000:bb:dd.f) when multiple expanders or a switch is present. Decoder listings should show plausible Host Physical Address (HPA) windows and a committed state before you treat CXL-attached DRAM as usable system memory.

Region and exposure mode checks

When the platform surfaces expander memory through a CXL region and DAX subsystem, confirm how capacity is configured before running daxctl or numactl tests:

cxl list -R -RXu

cxl list -r regionN -RXu

The daxregion section reports chardev names (for example dax0.0), mode (devdax versus system-ram), and memblock onlining progress. This tells you whether the next step is daxctl reconfigure-device, memory hotplug onlining, or NUMA verification with numactl -H.

Enable, disable, and health

Type 3 expanders usually auto-enable by default. These commands matter after manual disable, hot-reset recovery, or scripted regression gates:

cxl enable-memdev mem0

cxl disable-memdev mem0

cxl list -m mem0 -H -u

enable-memdev revalidates HDM decoders and CXL.mem enablement along the port hierarchy. The -H health listing exposes maintenance, media, and error counters when the device supports mailbox health reporting—useful during long stress runs alongside dmesg and RAS logs.

Suggested bring-up command sequence

A practical first-pass sanity script on a booting system:

lspci | grep -i cxl

lspci -s <BDF> -vvvv

cxl list -M -u

cxl list -vvu

cxl list -R -RXu

cxl list -m mem0 -H -u

numactl -H

Together, these commands separate device not seen (lspci) with details of DVSEC that can be parsed for information of interest, device seen but not registered (no memdev in cxl list), decode not committed (decoders/regions), and memory online but misconfigured (numactl shows wrong node or missing capacity). That layering matches the validation mindset used throughout the “Bring-up and testing of systems with CXL Type 3 memory expanders” series.

Keeping kernel pages off CXL memory

CXL expander memory should be treated as a migratable capacity tier, not as interchangeable DRAM. Slab caches, page tables, and other non-migratable kernel structures must stay on local socket memory because they cannot be demoted or migrated and would suffer higher latency and reliability risk on CXL.

Online CXL capacity in ZONE_MOVABLE

The primary remedy is to defer CXL expander capacity only into ZONE_MOVABLE on a discrete, CPU-less NUMA node. After confirming the device with cxl list and daxctl list, reconfigure it as system RAM with the default movable policy as we saw previously.

sudo daxctl reconfigure-device –mode=system-ram daxX.Y

daxctl onlines new blocks as movable by default; avoid –no-movable. Only move blocks assigned to CXL memory to ZONE_MOVABLE. This must be done carefully; determine the NUMA node assigned to a CXL device, use the sysfs interface, /sys/devices/system/node/node2/memory*, to determine which blocks are assigned to the CXL memory and only apply the ZONE_MOVABLE attribute to those blocks by looping over the respective CXL nodes. It’s important to note that CXL memory range onlined in ZONE_MOVABLE is not eligible for 1-GB Gigantic Page allocation.

Page temperature and tiered memory placement on CXL systems

Hot, warm, and cold pages

In CXL-enabled tiered memory systems, pages are commonly classified by access frequency over a sliding time window rather than by a fixed label. Hot pages are touched often enough to affect performance while cold pages are allocated but remain idle for minutes or longer.

Production studies report that a large share of allocated memory, often well over half, can be cold in short windows. Warm pages sit between those extremes: accessed occasionally or likely to be re-accessed soon, so they tolerate slower tiers better than hot data, but still benefit from promotion if they heat up.

TPP further notes that page type matters. Anonymous heap and stack pages tend to run hotter than file-backed cache and tmpfs, and temperature can flip quickly as pages are allocated and freed, so static placement fails.

Why page placement is critical

CXL expander memory is reachable with byte-addressable semantics but at higher latency and often lower effective bandwidth than socket-local DRAM. If the OS treats all NUMA nodes as equivalent, hot working sets can land on CXL, new allocations compete with cold data for fast DRAM, and capacity-bound workloads that should tolerate tiering still lose double-digit performance.

TPP reports up to roughly 18% performance improvement over default NUMA balancing on CXL-tiered platforms, and production analyses show sharp latency-sensitivity once the hot footprint exceeds what local DRAM can hold.

For CXL Type 3 bring-up, correctness may pass with memory online, but performance sign-off requires verifying not only that CXL capacity exists, but that hot, warm, and cold pages are landing on the intended tiers under the policies that the user fleet actually runs.

Default Linux policies

Default policies start simple: allocate preferentially from local DRAM and spill to the CXL NUMA node only when fast-tier capacity is exhausted. The kernel’s NUMA balancing (numa_balancing) enables and configures automatic, page-fault–based balancing. Setting it to NUMA_BALANCING_MEMORY_TIERING (value 2) tells the kernel to treat the NUMA nodes as tiers and promote frequently accessed (“hot”) pages into the fast tier.

echo 2 > /proc/sys/kernel/numa_balancing

Memory-tier demotion (numa_demotion_enabled) under reclaim pressure moves cold pages to the slow tier instead of swapping them to disk.

echo 1 > /sys/kernel/mm/numa/demotion_enabled

Zone reclaim mode is a Linux kernel parameter that controls how aggressively the system reclaims memory from a local NUMA node when that specific node runs out of memory, rather than allocating memory from other remote nodes. It accepts one of the specified policies or a combination. Typical production knob will enable all reclaim policies.

echo 7 > /proc/sys/vm/zone_reclaim_mode

The above setting should not be used in all conditions. It’s highly recommended that the user try combinations of the above settings with benchmarks that closely resemble the workloads and use the combination that works best.

Tools for traffic generation and performance validation

While a detailed discussion of each benchmark and the traffic type deserve a separate discussion, some common benchmarks and tools are mentioned below that should help the reader get started.

Memory structural test

Memtester

Latency

Intel Memory Latency Checker (MLC) for x86 platforms

Bandwidth

Google Stressful Application Test (SAT/GSAT/stressapptest)

Google Multichase – pointer chasing benchmark

TPCH with DuckDB

Heimdall

When expander memory appears as its own NUMA node, numactl+membind forces traffic onto CXL-attached DRAM.

numactl –cpubind=0-15 –membind=2 <command to run memory traffic>

The example below runs on node 0 CPUs but allocates memory on node 2. CXL memory (see Part 1, Figure 2); swapping –membind between 0 and 2 gives a direct local-DRAM versus CXL comparison. On single-socket systems, the CXL device may enumerate as NUMA node 1.

Matching CXL link width to memory bandwidth

When sizing a CXL memory expander, usable bandwidth is not simply the PCIe/CXL rate on the connector. Traffic crosses two stages: the host-facing PCIe/CXL link and the DDR channels behind the Type 3 controller. End-to-end bandwidth is therefore the lesser of the two.

Effective Bandwidth = min(PCIe/CXL link bandwidth, DDR bandwidth behind CXL)

Recycled DDR4 is often slower, or with fewer active channels than native DDR5. Subsequently, the DRAM side can limit throughput before a full-width link saturates. In that case, a x16 link may not add much, and an x8 (or narrower) link can already match what DDR4 sustains. This frees up lanes, cutting expander cost and power, and leaving host I/O for GPUs, NICs, and other devices. Size the link to the slower of the two bandwidths, not to the maximum PCIe generation width.

A cross-layer validation mindset

CXL Type 3 memory expanders offer a practical way to grow capacity and effective memory bandwidth for data- and memory-intensive workloads where traditional DDR scaling is constrained by I/O, cost, and signal integrity. But successful deployment is not only a silicon or link problem.

Host-visible expander memory remains physically and administratively distinct from socket-local DRAM, so discovery, NUMA topology, performance, and RAS must be validated as a cross-layer problem spanning CPU, firmware, kernel parameters, device firmware, and user-space policy.

This three-part series outlined system context and platform prerequisites; the boot timeline from power through DVSEC, decode/mem_enable, CDAT/DOE, ACPI tables, and driver attach; and user-space tooling plus transport-level checks for CXL.mem enablement and HDM validation.

Future work includes switched and multi-device topologies, CXL 3.x pooling models, formal compliance automation, and standardized regression coupling protocol evidence with OS topology and workload QoS.

Acknowledgment

The author thanks Linux CXL kernel developers (the detailed notes and exchanges in lwn.net are extremely valuable), the open-source CXL community, the CXL Consortium, and platform engineers at CXL memory expander vendors and hyperscalers. Any errors remain the author’s own.

Ameet Sanghavi works in post-silicon validation for PCIe and CXL at Nvidia with a focus on interface bring-up and validation on shipping products. He has worked on PCIe since 2005 (from PCIe 1.1 onward) and on CXL since 2020 (from CXL 1.1 onward).

Editor’s Note

The views and content of the article are the author’s own and not affiliated to any of his current or previous employers.

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