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Radon: Level detection, risk determination, and as-needed mitigation
Odorless. Colorless. Tasteless. But certainly not harmless. Radon, in both air and ground water, is a health risk whose prevalence should be regularly assessed and, if necessary, dealt with.
Beginning last fall and continuing through early summer, my community built an emergency access road that links up with a state highway below us and provides an alternate escape path in case of fire or other calamity, a particularly appealing option for those (like me) whose homes are at the far end of the community.
Road construction involved, among other things, the use of dynamite to blast pathways through rocky hillsides. And shortly after road completion, I learned that a residence a few minutes’ walk away from us had tested positive for high radon levels and was in the process of installing a mitigation setup.
Were the two events—earth disturbance due to road construction and radon release—related? I don’t know, and I’m not forward enough to ask the neighbors, but it’s possible. Regardless, even though our home had successfully passed a radon test done as part of the pre-purchase inspection more than a decade ago, I was motivated to learn more about radon and then re-test the premises for myself to see if the situation had subsequently evolved in an adverse direction.
Uranium and radium decayAs usual, I began my education with a visit to Wikipedi’s radon entry.
Radon is a chemical element; it has symbol Rn and atomic number 86. It is a radioactive noble gas and is colorless and odorless. Of the three naturally occurring radon isotopes, only 222Rn has a sufficiently long half-life (3.825 days) for it to be released from the soil and rock where it is generated. Radon isotopes are the immediate decay products of radium isotopes.
Here’s more.
A common source of environmental radon is uranium-containing minerals in the ground. Radon can also occur in ground water, such as spring waters and hot springs. Radon trapped in permafrost may be released by climate-change-induced thawing of permafrosts, and radon may also be released into groundwater and the atmosphere following seismic events leading to earthquakes, which has led to its investigation in the field of earthquake prediction.
Seismic events leading to earthquakes…and possibly also dynamite blasts? Here’s where the prose turned worrisome.
Epidemiological studies have shown a clear association between breathing high concentrations of radon and incidence of lung cancer. Radon is a contaminant that affects indoor air quality worldwide. Because radon is denser than air it accumulates in basements and crawlspaces under dwellings. According to the United States Environmental Protection Agency (EPA), radon is the second most frequent cause of lung cancer, after cigarette smoking, causing 21,000 lung cancer deaths per year in the United States. About 2,900 of these deaths occur among people who have never smoked. While radon is the second most frequent cause of lung cancer, it is the number one cause among non-smokers, according to EPA policy-oriented estimates.
And finally, there’s this from the related Wikipedia entry for radon mitigation.
There is no proven link between radon in water and gastrointestinal cancers; however, extremely high radon concentrations in water can be aerosolized by faucets and shower heads and contribute to high indoor radon levels in the air.
Yikes!
Radeon prevalence varies across the United States and, more broadly, the world at large. It turns out that Denver, Colorado and surrounding regions have among the highest U.S. concentrations, as the following two related graphics show. The first documents the predicted fraction of U.S. homes having concentrations of radon exceeding the EPA’s recommended action level of 4 pCi/L. Note the orange region smack dab in the middle of Colorado, right where my residence is located.
And then there’s this one, which formats the data slightly differently, but ends up with the same essential outcome.
The most concise and clarifying data I came across related to my specific situation comes from an informative page (and a highly recommended read, even if you’re not a neighbor of mine) on the Jefferson County website.
Approximately 50% of homes in Jefferson County test above the EPA action level for radon every year.
It’s followed by this.
Radon is found throughout the U.S. and is particularly prevalent in Colorado. The U.S. Environmental Protection Agency (EPA) has ranked Colorado as a Zone 1 area, meaning the average house will exceed the EPA’s action level for indoor radon.
Once again: yikes! I guess that’s why I see mitigation setups (more on them later) like this one all over the community.
The Jefferson County webpage on radon also includes these non-scientist explanation statements that I thought were enlightening.
Radon is an invisible, odorless, tasteless, cancer-causing gas that comes from the natural radioactive breakdown of uranium and radium in soil, rock and water. Radon enters buildings through cracks, holes and pipes in the foundation. All buildings contain some radon, but homes are the most concerning since that is where families spend most of their time.
There’s also this.
Radon is produced as a decay product from uranium and radium. This naturally occurring radioactive gas is found in most soil, rock, and groundwater. Since radon is a gas, the inert element can easily travel through cracks and pores without being chemically bound or attached to other elements. Voids and porous materials are found under every building, allowing radon easy entry.
Perhaps obviously, once again quoting from the Jefferson County website, “the test kit should be placed in the lowest occupied level (typically a basement) and in the normal breathing zone (about 2-6 ft. from the floor) and 3 ft. from windows, doors, vents, or anything that allows airflow.”
Preferably, in fact, windows, doors (especially screened) and other outside-air ventilation sources should be shut as much as possible through the entire multi-day testing cycle to minimize gas dilution and maximize negative pressure (aka, “stack effect”) flow into the home, thereby simulating the worst-case radon accumulation that would normally occur in winter and other closed-off times (that said, air conditioning systems are another common catalyst for high radon gas leakage into buildings).
Free radon test kits are available to me from both Jefferson County and the Colorado Department of Public Health and Environment and can also be bought from local hardware and home improvement stores and online retailers. Keep in mind, however, that the kit still needs to be sent in for post-test analysis, with results subsequently sent back to the submitter, all steps incurring delays.
Instead, especially since I’m a techie who can’t resist new toys, I decided to buy my own radon detector hardware. The Airthings Corentium Home 2 (stock photos and promo video follow) normally costs around $180, but I found one promotion-priced on the Resale (formerly Warehouse) area of Amazon’s website for $121.46.
Versus its first-generation predecessor, it supplements the integrated display with Bluetooth LE and SmartLink (Airthings’ proprietary wireless protocol) connectivity to a separate device.
And battery life extends from 1.5-2 years (3 AAA alkaline batteries) with the original Correntium to 2-3 years (two AA alkaline batteries).
Here’s my own unit, starting with outer packaging shots.
Now open, with the contents accompanied by a 0.75′′ (19.1 mm) diameter U.S. penny for size comparison purposes.
Inside, of course, is the Corentium Home 2, along with some literature (also found online here) and a silica gel packet.
Here’s the open backside; batteries are included, with only a thin slip of plastic needing to be removed to complete the connection. Activate them as the power source and start testing.
Mating and initial setup of the device with my smartphone—which subsequently receives periodic notifications from it—was uneventful.
And, after a preparatory 24-hour delay over which the device collected and averaged (but did not yet share with me) its initial data set, preliminary results were encouraging.
I kept the measurements going for nearly three weeks before capturing another screenshot set, and the good news thankfully kept coming.
The application (Android in my case, but iOS also available) displays trend graphs, too, useful to see how radon levels, along with also-measured humidity and temperature, varied over time.
All well and good, though I plan to continue conducting going-forward measurements, since radon gas levels vary over time due to a variety of factors. But what if my results had been more concerning? Step one is to seal off as much as possible any soil-sourced radon gas leakage coming into the house through slab and foundation cracks; more substantial slab voids resulting from floor drains and sump pumps are also potential culprits, albeit harder-to-eliminate ones.
Next, strive to minimize negative pressure (stack effect) situations, where the inside-house air pressure is lower than that of the outside, generating a partial vacuum condition that pulls air in from below the residence in attempting to equalize the differential. Frequent, vigorous use of HVAC systems is a potential root cause of pressure imbalances, along with attic fans, bathroom and kitchen-cooking-appliance exhausts, and the like. Keeping windows and screen doors open whenever weather and broader seasonal temperatures afford this option, as earlier mentioned, is helpful albeit only as temporary workarounds.
The most significant mitigation measure, and one that per my earlier shared photo I see frequently around my community, involves the installation of an active soil depressurization system. A PVC pipe originating below the home’s foundation, commonly in combination with a continuously running inline fan, draws radon gas out and up to the roof where it’s safely exhausted, completely bypassing the residence interior (and its inhabitants) in the process.
A tutorial video I found online showcases an in-home mitigation system installation.
I found it interesting for two main reasons, among others:
- The system’s location: I’d previously only been familiar with exterior-visible setups such as the one in the earlier-shown photo. I now wonder how many more homes in my community have implemented radon mitigation, internally (and therefore invisible to me from the outside) in these latter cases.
- And the initial, albeit unsuccessful, attempt to rely solely on a passive system, later supplemented by an active fan to create sufficient incremental suction.
I’ll wrap up here and turn it over to you for narration of your radon-related experiences and broader thoughts in the comments. Thanks as always in advance for them!
—Brian Dipert is the associate editor, as well as a contributing editor, at EDN.
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Sivers announces $3.4m program with SemiNex for InP light sources forAI data centers
TI a first mover in CAN XL transceivers
The Controller Area Network (CAN) extended data-field length (XL) specification—which has been standardized for years—now has the first commercially available CAN XL transceiver. Texas Instruments has unveiled the TCAN6062 CAN XL transceiver, which supports payloads of up to 2,048 bytes per frame and data rates up to 20 Mbps.
The CAN XL transceiver ensures that priority messages are delivered first and on time, facilitating performance critical to humanoid robots, industrial robots, and human-machine interface (HMI) systems. This allows system designers to leverage CAN XL to exchange data rapidly and reliably in applications ranging from industrial robotics to automotive safety.
Figure 1 The CAN XL technology is promising to open the door to a new era of applications. Source: Texas Instruments
The new CAN XL transceiver is also backward compatible with CAN flexible data rate (FD) and CAN signal improvement capability (SIC) operations. This ensures a seamless migration and enables design teams to evolve existing designs incrementally without requiring a full redesign.
Next, while CAN XL is better and cheaper than CAN FD, it can also tunnel Ethernet. So, the CAN XL transceiver allows engineers to consolidate communication layers and use Ethernet in mixed-network architectures with Transmission Control Protocol/Internet Protocol (TCP/IP) tunneling. That facilitates efficient transfers of diagnostics, sensor data, control traffic, and over-the-air (OTA) updates on a single network.
Figure 2 The TCAN6062 CAN XL transceiver helps reduce ringing by up to 80% in complex networks, simplifying validation in high-node architectures. Source: Texas Instruments
CAN has been the backbone of industrial communications for decades. However, industrial systems are now generating and demanding more data than ever before. That’s because applications require fast, deterministic communication to synchronize motion control, sensor feedback, and diagnostic data. That, in turn, leads to new networking requirements, and as a result, engineers often accept system-level trade-offs to compensate for bandwidth constraints.
Dwight Byrd, GM of Interface Products at TI, claims that the TCAN6062 CAN XL transceiver bridges that gap. “It offers engineers a path to higher-bandwidth networks while maintaining the proven reliability CAN is known for.”
“As industrial systems become more intelligent and interconnected, what we ask of our networks continues to evolve,” Byrd added. “Engineers need more data, higher speeds, and greater flexibility, all without compromising performance or reliability.
TI’s networking technology managers are confident that CAN XL will open the door to a new era of applications, enabling systems to deliver higher performance at a reasonable cost. And here, TI has the first-mover advantage.
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- Signal Chain Basics: Industrial Market Transitions to 3.3V CAN Transceivers
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TI Advances Next-Generation Industrial Systems With the First Commercially Available CAN XL Transceiver
New TCAN6062 CAN XL transceiver delivers the highest bandwidth and largest payload of any CAN-based network while preserving the advantages of proven CAN protocols.
What’s new?
Texas Instruments (TI) today introduced the industry’s first commercially available CAN XL transceiver, designed to help industrial engineers keep pace with the growing data demands of modern networks. TI’s TCAN6062 Controller Area Network (CAN) extended data-field length (XL) transceiver supports payloads up to 2,048 bytes per frame and data rates as high as 20Mbps, while ensuring that priority messages are delivered first and on time with the performance on which humanoid robots, industrial robots and human-machine interface (HMI) systems depend.
The TCAN6062’s backward compatibility with CAN flexible data rate (FD) and CAN signal improvement capability (SIC) operations enables seamless migration to CAN XL, allowing teams to evolve existing designs incrementally without requiring a full redesign. Additionally, the transceiver allows engineers to consolidate communication layers and use Ethernet in mixed network architectures with Transmission Control Protocol/Internet Protocol (TCP/IP) tunneling, enabling efficient transfers of diagnostics, sensor data, control traffic and over-the-air updates on a single network.
Why does it matter?
Industrial systems are generating and demanding more data than ever before, with applications requiring fast, deterministic communication to synchronize motion control, sensor feedback and diagnostic data. These applications have introduced new networking requirements, often leading engineers to accept system-level trade-offs to compensate for bandwidth constraints. TI’s TCAN6062 CAN XL transceiver bridges that gap, offering engineers a path to higher-bandwidth networks while maintaining the proven reliability CAN is known for.
The specification for CAN XL has been standardized for years, but TI is the first to deliver and bring the hardware that makes it possible to the mass market. By introducing the TCAN6062, TI is transforming the innovative protocol into a broadly available, ready-to-use solution that engineers can implement in their next-generation designs.
“As industrial systems become more intelligent and interconnected, what we ask of our networks continues to evolve,” said Dwight Byrd, general manager, Interface Products at TI. “Engineers need more data, higher speeds and greater flexibility, all without compromising performance or reliability. TI’s TCAN6062 CAN XL transceiver puts that capability in their hands today, helping them build faster, more capable industrial systems.”
The TCAN6062 CAN XL transceiver’s SIC helps reduce ringing by as much as 80% in complex networks, simplifying validation in high-node architectures. Combined with wide input/output voltage compatibility and protection up to ±58V, the transceiver offers broad design flexibility across a range of industrial applications.
More details
As members of the CAN in Automation (CiA) technical group that developed International Organization for Standardization (ISO) 11898-2:2024, TI’s engineers helped shape the physical layer specification for CAN XL, ensuring the protocol was built to support the real-world demands of industrial applications.
“CAN has been the backbone of industrial communications for decades,” said Holger Zeltwanger, managing director at CiA. “Texas Instruments’ long-time membership and collaboration with CiA builds on that legacy, helping shape CAN XL by contributing to a standard that will guide the entire industry. Now with the introduction of the first commercially available CAN SIC XL transceiver, CAN XL is accessible to engineers worldwide, reflecting our shared commitment to solving the engineering challenges of today and tomorrow.”
“CAN XL opens the door to a new era of applications, enabling systems to deliver higher performance at a reasonable cost. CAN XL is the better and cheaper CAN FD, but can also tunnel Ethernet,” said Arthur Mutter, Ph.D., chairman of the CAN XL Special Interest Group at CiA and senior executive, Networking Technologies at Bosch. “With TI now offering a CAN SIC XL transceiver, system designers can leverage CAN XL to exchange data rapidly (up to 20 Mbit/s) and reliably in all applications, from industrial and robotics to automotive safety.”
The TCAN6062 represents the next generation of TI’s industry-leading CAN transceiver portfolio. Spanning CAN FD, CAN SIC and now CAN XL, TI offers a comprehensive range of solutions, giving engineers the flexibility to deliver more data faster, farther and more reliably.
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UC Berkeley to Join Applied Materials’ EPIC Center to Speed Chip Innovation
Applied Materials, Inc. today announced that the University of California, Berkeley will join the company’s EPIC Center in Silicon Valley as a research collaborator. Working side by side with Applied’s scientists and engineers, UC Berkeley faculty and students will pursue high-impact research programs to accelerate the material and process innovations that are foundational to AI computing.
“The EPIC Center is designed to bring together the best minds from industry and academia in a high-velocity, manufacturing relevant environment to dramatically accelerate the development and commercialization of next-generation semiconductor technologies,” said Dr. Prabu Raja, President of the Semiconductor Products Group at Applied Materials. “Few institutions have shaped modern chipmaking as profoundly as UC Berkeley. Expanding our research collaboration at the EPIC Center strengthens the lab-to-fab innovation pipeline and gives us a powerful platform for developing the semiconductor talent the industry will depend on for decades to come.”
Research universities generate many of the ideas that become tomorrow’s semiconductor materials and process technologies, yet those ideas advance fastest when researchers can test them on the same equipment used by global manufacturers. Applied’s EPIC Center gives university researchers access to industry-scale tools, enabling rapid iteration, earlier validation and a smoother handoff from discovery to deployment.
UC Berkeley brings a history of translating foundational research into commercial semiconductor technology. UC Berkeley engineers built the first research laboratory at a university dedicated to prototyping integrated circuits in 1962. In the decades that followed, the institution produced breakthroughs the entire industry now runs on – among them the SPICE circuit simulator and the FinFET, the three-dimensional transistor that is now the basis of leading-edge logic manufacturing worldwide. That heritage of moving inventions out of the lab and into high-volume production is precisely what the EPIC Center is built to accelerate.
“Pioneering innovations by UC Berkeley researchers have enabled advancements in semiconductor chip technology, resulting in the exponential growth of computing that has ushered in the AI era,” said Mark Asta, dean of UC Berkeley’s College of Engineering. “Applied Materials’ new EPIC Center in the heart of Silicon Valley aims to speed the translation of university inventions into commercial products by providing early access to cutting-edge, industrial-scale semiconductor process equipment and technologies. I look forward to advancing research and supporting new engineering talent through this R&D collaboration with Applied Materials.”
Applied and UC Berkeley already share strong ties through semiconductor research collaborations and shared laboratory space, including work connected to the Berkeley Emerging Technologies Research (BETR) Center and the Center for Information Technology Research in the Interest of Society (CITRIS). A large network of UC Berkeley alumni works at Applied as engineers, scientists and managers, and Applied recruits from the campus each year. Both organizations are rooted in the same Silicon Valley ecosystem, allowing ideas, people and equipment to move easily between campus and industry.
Applied’s new EPIC (Equipment and Process Innovation and Commercialization) Center in Silicon Valley represents the largest ever U.S. investment in advanced semiconductor equipment R&D. The center is designed from the ground up to dramatically reduce the time it takes to commercialize breakthrough technologies from early-stage research to full-scale manufacturing. The facility is on track to become operational in 2026.
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BAE Systems advances to Phase 2 of DARPA’s THREADS program
PayU Launches India’s First RBI-Compliant Accessible Payments Checkout for Blind and Visually Impaired Users
PayU, India’s leading diversified fintech platform, today announced the launch of Accessible Payments Checkout, India’s first RBI-compliant payment checkout designed for people who are blind or visually impaired. The launch marks a significant step towards making digital payments more accessible and inclusive. As the country celebrates Independence Day, the launch reinforces the importance of ensuring that everyone can participate in the digital economy with greater independence.
With this launch, PayU becomes the first payment gateway in India to comply with the Reserve Bank of India’s October 2024 accessibility mandate (BIS IS 17802). The enhanced checkout introduces a range of features designed to improve discoverability, navigation, and interaction for users with visual and cognitive accessibility needs, making the online payment journey more seamless and intuitive.
The solution reflects PayU’s continued commitment to building inclusive financial technology and enabling every user to access digital payments with confidence and ease.
The new PayU Accessibility Checkout includes four key features:
- Full-Screen-Reader Optimisation: PayU’s Accessibility Checkout is engineered to work seamlessly with screen readers, ensuring easy navigation of the entire payment journey for the visually impaired and blind without any sighted assistance. From choosing the payment method like Net banking, UPI, QR, NEFT, etc. to payment amount confirmation and transaction completion, every element on the checkout page is clearly and transparently announced via voice commands to the user, ensuring they know where exactly they are in their payment journey.
- Adaptive User Profiles: This feature allows users to customize their checkout environments–adjusting cursor size, button dimensions, and navigation aids to fit their requirements. Their preferences can be saved, switched between or reset at any point. The checkout adapts as the user wants, delivering complete control in the hands of the user.
- Visual Inclusivity Modes: To aid users with conditions such as low vision, colour blindness, or light sensitivity, a wide variety of visual modes are offered by PayU’s Accessibility Checkout. From high contrast to greyscale mode to colour inversion to saturation adjustment options, the checkout offers support to the visually impaired users who rely on colour and contrast adaptations to use digital platforms.
- Text Resizing: The Accessibility Checkout supports text scaling of up to 200% of the standard size, without overlapping or hiding any content. This feature ensures all elements on the checkout is transparently seen and read by the users with visual impairments.
“True financial inclusion is only possible when every individual can access and use digital payments independently. At PayU, accessibility is not an afterthought – it’s a core design principle. With the launch of our Accessibility Checkout, we’re helping merchants deliver payment experiences that are inclusive by design while enabling millions of users with diverse accessibility needs to participate more confidently in India’s digital economy. This is an important step towards supporting the RBI’s accessibility vision and building digital infrastructure that works for everyone,” said Manas Mishra, Chief Product Officer, PayU and Wibmo.
Prashant Ranjan Verma, General Secretary, National Association for the Blind, Delhi, said, “I appreciate PayU’s efforts to make digital payments more accessible for everyone, including people who are blind or have low vision. I was able to complete a UPI payment independently using PayU’s accessibility-first checkout with VoiceOver. I hope PayU continues to strengthen accessibility so that more people with visual impairments can transact confidently and independently.”
PayU’s Accessibility Checkout does not require merchants to change their existing integrations. Accessibility is embedded as a design feature allowing merchants using PayU to automatically offer a compliant and accessibility-first payments checkout experience to their customers with disabilities.
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Made by Google 2026: This limited silicon-supply situation really sucks
AI-driven demand underpins logic foundry and memory fab capacity constraints, leading to cost increases. Add tariffs to the mix, and Google and its competitors (not to mention end users) pay the price.
Last year’s Made By Google fall product launch event happened midday on August 20, moderated by Jimmy Fallon. Although I found value in the devices, software and services Google unveiled there, the un-traditional Tonight Show-styled format wasn’t particularly to my liking, a negative opinion shared by a notable number of others whose coverage I subsequently perused.
This year’s event, earlier today (August 12) as I write this, was once again celebrity-moderated, this time by Trevor Noah. But this time it took place in the evening, with the announcements notably preceding it; a flurry of blog posts had already hit Google’s website at 8 am MT, where I am. Feel free to draw your own conclusions as to the judged effectiveness (or, perhaps more accurate, lack thereof) of last year’s event 
And begging the question of why Google bothered doing this year’s event at all, save I suppose for the chance to see “live” demos, “softball” interviews and other such questionable-value content.
That said, the products themselves once again were notable, both in an absolute sense and relative to their prior-generation predecessors.
Befitting my engineering-dominated readership, I’ll as usual start out my coverage with the application processor, the Tensor G6, the intelligence nexus of the Pixel 11 smartphone series.
Power/performance balance (and profit) optimization
When I published last year’s event coverage, little was known at the time about the latest-generation Tensor G5 SoC save for its 3 nm TSMC fabrication source (a notable departure from Google’s longstanding foundry partnership with Samsung) and its eight-core CPU cluster mix: “one “prime” core, five mid-level ones, and two efficiency ones.” Beyond that, all Google was saying at the time was that, versus its Tensor G4 predecessor, it delivered the following updates.
- An up to 60% more powerful TPU
- A 34% faster on average CPU, and
- New security hardware
One year later, thanks to intensive developer engagement with the platform, we know much more about the Tensor G5 than we did before.
- CPU (8 total cores): 1x Arm Cortex-X4 at 3.78 GHz, 5x Arm Cortex-A725 at 3.05 GHz, 2x Arm Cortex-A520 at 2.25 GHz
- GPU: Imagination Technologies PowerVR (DXT-48-1536)
And now on “Day Zero” of the Tensor G6 era, what’s Google saying about it? Predictably, not much beyond another year’s worth of nebulous hand waving in comparison to the Tensor G5:
Tensor G6 features an upgraded CPU for 25% faster web browsing and 15% quicker app launches. Packing 50% more TPU compute and paired with the latest Gemini Nano model, Google Tensor G6 processes on-device AI tasks up to 3.5 times faster while using up to 3.5 times less energy.
But thanks to a leak sourced from embargoed media hands-on time with the Pixel 11 family, the following additional (and more specific) Tensor G6 specs, referencing Arm’s C-series cores, are also presumably accurate.
The Tensor G6 sports a seven-core configuration, with one prime “C1 Ultra” core clocked at 4.1GHz, four performance “C1 Pro” cores clocked at 3.4GHz, and two efficiency “C1 Pro” cores clocked at 2.65GHz. The GPU appears to be a PowerVR C-series variant with six compute units clocked at 1.3GHz.
One other silicon-related nuance also bears mention. Although, as previously mentioned, Google switched from Samsung to TSMC as its foundry source for the Tensor G5 last year, it stuck with Samsung’s Exynos cellular subsystem. This year, reportedly (although I haven’t yet seen definitive confirmation), this too has changed; Google’s supposedly now leveraging MediaTek M90 5G cellular IP.
Smartphone evolutionary modestyAside from the new colorways, you’d understandably likely be hard-pressed to discern a visual difference between Google’s latest handsets—the baseline Pixel 11, high-end Pixel 11 Pro and Pro XL, and book-style Pixel 11 Fold—and their 10th generation predecessors. Backs are once again all-glass. Displays are a bit brighter, and more scratch-resistant in the “Pro” variants. Camera bars are a bit more svelte (along with overall Fold thinness), and for “Pro” versions, embed a multicolor notification LED assembly surrounding the flash and branded “HiLight”. Particularly clever readers may have already noted the enhanced scratch-resistance association, since the notifications can only be seen when the phone is screen-down on a flat surface.
That all said, to the overall “supply constraints” theme of this writeup, I’ll point out that the Pixel 11 storage options now start at 256 GBytes; the entry-level 128 GByte variant of the Pixel 10 that I recently acquired isn’t offered this time around. In Google’s defense, Apple did the same thing a year ago with the iPhone 17 versus its iPhone 16 precursor, although in that earlier case the 2x capacity multiplier came for the same intro price as the 128 GByte prior-gen device.
This time the 256 GByte Pixel 11 price thankfully at least matches that of the year-ago 256 GByte Pixel 10, versus with an accompanying price increase as other smartphone suppliers are doing nowadays. Further to Google’s defense, note that a year ago any bill-of-materials cost increases were predominantly due to tariff impacts. Now, in contrast, supply constraints are additionally being felt to fuller effect. It’ll be curious to see how Apple handles both memory and TSMC foundry cost increases at its likely next-month announcement event; for one thing, the company will reportedly delay the launch of its baseline iPhone 18 until sometime next year.
In closing, at least for this section, one more memory-related twist bears mention. A year ago, I wrote, “Google also didn’t “hide” tariff costs by cutting RAM capacities (which would counterbalance its burgeoning AI ambitions, anyway)”. Well, this year they did. The lowest (256 GByte) storage capacity variants of the Pixel 11 Pro and Pro XL also have less RAM—12 GBytes vs 16 GBytes—than both their higher-capacity this-year siblings and same-capacity Pixel 10 predecessors, in the latter case with no accompanying generational price break. Admittedly, Google’s working hard on optimizing memory requirements for its on-device models, but still…
Watches and trackersLast year’s Pixel Watch 4 was a notable update to its predecessor(s), as I wrote about at the time (although I’m still fiscally quite content with a recent update from my long-in-the-tooth first-generation wearable to “only” the Pixel Watch 3, more discussion of which I’ll save for another post another day). This year’s Pixel Watch 5 advancements are also more modest, notably including slight (~12%) CPU performance and battery capacity upticks along with an on-device AI-intended RAM upgrade from 2 GBytes to 3 GBytes, the latter leading to—you guessed it—an associated $50 price tag increment.
I’m not entirely sure why Google included a set of earbuds in its launch suite promo photo shown earlier this piece, as aside from a new Pixel Buds 2 (two years old) colorway option and pending firmware-delivered feature updates to both them and the Pixel Buds 2a (introduced a year ago), nothing’s new. Conversely, the most brand-new device released this week was the Pixel Tag, unsurprisingly supportive of Google’s Find My Device network and conceptually similar to (and a competitor of) Apple’s also-UWB-enhanced second-generation AirTag.
Hopefully, this wireless-connectivity enhancement suggests that we’ll be seeing broader support for UWB in both Google’s and other Android licensees’ handsets in the future. My biggest surprise here is that, unlike Motorola and other tracker manufacturers, Google didn’t also adopt an AirTag-clone form factor that would enable it to slot into the already sizeable and still steadily expanding AirTag ecosystem of luggage tags, stealth security setups and the like.
That’s what I’ve got for you today, folks. As always, please sound off with your thoughts in the comments!
—Brian Dipert is the associate editor, as well as a contributing editor, at EDN.
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- Google’s Pixel 10: Upgrading smartphones again
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6.5-kV SiC MOSFET reaches 8-kV blocking
NoMIS Power has developed a 6.5-kV large-die SiC MOSFET that has demonstrated over 8 kV of blocking voltage, 90-mΩ on-resistance, and 55-A drain current. Based on the planar SiC technology used in its 3.3-kV devices, the 6.5-kV MOSFET extends the technology into the high-voltage class and provides a foundation for the company’s planned 10-kV MOSFETs and 20-kV SiC IGBTs.
NoMIS is sampling the 6.5-kV SiC MOSFET to U.S.-based customers, with standard-production devices scheduled for Q4 2026. The company plans to expand the 6.5-kV portfolio with additional on-resistance variants, small-die MOSFETs, hybrid junction-barrier Schottky FETs (JBSFETs), and standalone diodes for applications including HVDC power transmission, solid-state transformers, pulsed-power systems, rail traction, and megawatt-scale EV charging
The 6.5-kV devices build on the company’s 3.3-kV SiC MOSFET family, which is already in production, while 10-kV and higher-voltage MOSFETs, diodes, JBSFETs, and SiC IGBTs are in development.
For more information, visit the NoMIS Power Semiconductors and Modules webpage.
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Memory platform tackles AI bottlenecks
NEO.AI is a memory platform from NEO Semiconductor that overcomes SRAM and DRAM scaling limitations in AI memory systems. As part of the platform launch, NEO Semiconductor is introducing its X-SRAM technology for on-chip memory in GPUs and AI processors and reporting its latest progress on 3D X-DRAM, a high-capacity memory technology for HBM.
By replacing conventional six-transistor SRAM with a two-transistor architecture, X-SRAM enables up to 5 times higher memory density to support 1–2 GB of on-chip memory, according to NEO. The technology maintains SRAM-class performance and is compatible with advanced nanosheet CMOS processes. It also provides a path toward future monolithic 3D X-SRAM implementations.
Built on 3D NAND manufacturing processes, 3D X-DRAM delivers up to 10 times higher memory capacity than conventional DRAM, according to NEO. Successful proof-of-concept validation demonstrates its potential as a scalable and manufacturable solution for next-generation HBM.
For more information, visit the NEO X-SRAM webpage.
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eFuse speeds overcurrent detection
The KTS1630 5-A eFuse from Kinetic Technologies protects sensitive electronics against overcurrent, short circuits, and thermal faults. It is designed for consumer and industrial systems operating from 5-V and 12-V power rails, helping improve system safety and reliability. By detecting overcurrent conditions typically within 100 ns, the device can isolate faults before they can damage downstream circuitry.
An integrated MOSFET with a typical on-resistance of 31 mΩ from VIN to VOUT helps reduce conduction losses while supporting operation across a 4.5-V to 18-V input range, with a 20-V absolute maximum rating at VIN. The KTS1630’s adjustable 1-A to 5-A current limit allows designers to set the protection threshold for specific loads rather than relying on a fixed current-limit threshold. The eFuse also includes a dedicated control output for an external reverse-blocking MOSFET that prevents reverse current when the input supply is removed or the output voltage exceeds VIN.
A programmable output slew rate controls inrush current during startup, helping prevent input-supply droop, connector stress, and unintended system resets when large capacitive loads are connected.
Supplied in 10-pin, 3×3-mm VDFN packages, the eFuse is available in both auto-retry and latched-off versions.
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Four-channel USB-UART IC boosts server management
A high-speed USB-to-UART bridge, MaxLinear’s Carmel MxL81434 supports console access and infrastructure management in AI data centers and hyperscale cloud environments. The highly integrated device includes USB 2.0 High-Speed (480 Mbps) connectivity, four independent UART channels operating at up to 15 Mbps each, an I2C master, and 32 GPIOs for server and rack-scale management designs.
Carmel extends MaxLinear’s USB-to-UART portfolio, increasing the maximum UART data rate to 15 Mbps and doubling the transmit and receive FIFO size. The 1024-byte FIFOs help sustain high throughput and reduce host processor overhead, while the integrated I2C master and 32 GPIOs consolidate management, monitoring, and debugging functions. Low-latency console connectivity supports faster system bring-up, recovery, diagnostics, and provisioning.
The USB-to-UART bridge provides ±15-kV HBM ESD protection for demanding server and data center environments.
Samples of the Carmel MxL81434 are expected to be available Q4 2026.
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RTD terahertz evaluation kit quadruples output
ROHM is offering the RTD-EVK-G2 evaluation kit, based on its second-generation terahertz-wave oscillation device. Built using resonant tunneling diodes (RTDs), the device delivers up to 40 µW of output power, four times that of the first-generation product. The kit enables companies and research institutes to evaluate terahertz-wave oscillation and detection for applications such as nondestructive testing, medical imaging, high-resolution radar sensing, material identification, and high-speed wireless communications.
Unlike conventional terahertz systems, which are costly and require large equipment, the RTD-EVK-G2 includes a sample device, cable, and evaluation board for evaluation in space-constrained settings. The terahertz device maintains the same 0.5×0.5-mm chip size and 4.0×4.3-mm PLCC package as the first-generation component. Compared with other terahertz generation methods, the RTD approach generates less heat and consumes less power.
Sales of the RTD-EVK-G2 kit are scheduled to begin in August 2026 at $3,300 per set. Contact a sales representative or visit the Rohm contact page for more information. Purchase of the evaluation kit requires signing a non-disclosure agreement with Rohm.
The post RTD terahertz evaluation kit quadruples output appeared first on EDN.
Ultisense - A devboard to sense as many things as possible
 | After a lot of learning I finally designed and manufactured my own custom (working) PCB! it's an esp32s3 devboard, with as many sensors as you can think of: NFC, IMU, VOC, humidity/temperature, color/ambient light, magnetometer, microphone, speakers, sd card, I2C expansion. I'm a high school student, so this definitely took a lot of help from people who knew what they were doing, and two failed circuit boards before this lol. Most recently I've used it for a rhythm game I made, where using the IMU let me make a beatsaber-style anime game of bad apple! open source at https://github.com/darshg321/Ultisense [link] [comments] |
Cheap and cheerful LMC555 RC PWM pulse generator
This circuit enables you to generate remote control PWM test signals with a (very) generic (and cheap) chip.
A recent Design Idea illustrated the application of an interesting chip (the LTC6992) to remote control (RC) PWM test signal generation. Being familiar with neither the application nor the chip, and despite being a (very) old dog, I decided to try to learn a new trick or two. So I took a trip Through the Looking Glass into the LTC6992 datasheet. Here’s what I found there.
Wow the engineering world with your unique design: Design Ideas Submission Guide
Firstly, the LTC6992 is a very capable and consequently rather complex device. Inevitably its datasheet is similarly complex and, frankly, more than a little confusing. Which, of course, might be due to that old dog factor! But moving along…
Secondly, it’s not inexpensive: ~$6 in singles, plus it needs an external precision regulator that adds another buck.
But worsetly (??? Ed.), it happens that the RC PWM application involves rather low, only 5% to 10%, PWM duty cycle numbers. When you combine that with the LTC6992 datasheet’s specification (on page 4) of +/-3% typical duty cycle error, it becomes clear the LTC6992 is unlikely to be very happy (or accurate) in this application.
So I decided to work toward a Design Idea that would be more familiar (and friendly?), not needful of (too many) extra external components, (mainly) more accurate, and hopefully a bit cheaper. Figure 1 shows what my labors achieved.
Figure 1 This Design Idea leverages a LMC555 as a variable duty cycle (1ms to 2ms = 5% to 10%), constant frequency (20ms = 50Hz) PWM oscillator. Timing is ratiometric and therefore independent of V+ so no external voltage regulator is needed.
How it works is (roughly) sketched in Figure 2’s timing diagrams.
Figure 2 The PWM oscillation cycle alternates between the Threshold pin for the duration of the 1ms to 2ms ON halfcycle is adjusted by R1, and the Trigger pin for the 18ms to 19ms OFF halfcycle. C2 > C1 to compensate for D1 forward drop.
PWM duty cycle = (R2 + R1+)/(R1 + R2 + R3) = 5% to 10%.
Oscillation frequency = 1/(loge(3)C1(R1 + R2 + R3)) = 50Hz independently of R1 setting
D1 recharges C2 during the PWM on interval. Z1 limits the output amplitude to TTL-safe levels. And given that LMC555s can be had for about a dollar in singles, I’d say the hoped-for price point box was also checked.
Stephen Woodward‘s relationship with EDN’s DI column goes back quite a long way. Over 200 submissions have been accepted since his first contribution back in 1974. They have included best Design Idea of the year in 1974 and 2001.
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Veeco’s Q2 results exceed guidance
NVIDIA Mobilises $500 Billion for Next-Generation AI Infrastructure
The rapid expansion of artificial intelligence is creating an unprecedented demand for computing power, data centres, advanced networking, electricity and high-performance chips. However, the enormous capital required to build AI infrastructure has become a major challenge for AI companies and cloud providers. Addressing this funding gap, NVIDIA has announced partnerships with major global investment firms to establish independent financing platforms designed to mobilise more than $500 billion in third-party capital for AI infrastructure over time.
The initiative brings together NVIDIA with Apollo Global Management, BlackRock, Blackstone, Brookfield, Goldman Sachs and KKR. Rather than NVIDIA providing the entire $500 billion itself, the initiative is designed to attract capital from institutional investors through dedicated financing platforms. The capital can then support the development and deployment of AI computing infrastructure, including GPUs, servers, data centres, networking systems and related power infrastructure.
The chipmaker on 10 August announced partnerships with Apollo, BlackRock, Blackstone, Brookfield, Goldman Sachs and KKR to create independent financing platforms for AI compute infrastructure. The platforms are expected to mobilise more than $500 billion in third-party capital over time for the development of AI infrastructure.
Nevertheless, the NVIDIA’s collaboration marks a landmark step in the financing of AI infrastructure. By mobilizing as much as $500 billion from third-party sources, the firm and financial partners intend to accelerate the build-out of infrastructure for the next iteration of AI innovation. The effort could fundamentally reposition the notion of AI compute from a technologically motivated expenditure into a substantial asset class with unprecedented interconnectivity between semiconductor design, data centres, power and institutional capital.
The post NVIDIA Mobilises $500 Billion for Next-Generation AI Infrastructure appeared first on ELE Times.
OpenLight and Tower expand PH18DA photonics ecosystem to accelerate photonic IC development
Record high wafer shipments. Can fabs keep pace?
AI has transformed the semiconductor industry’s pressure points. The conversation is no longer focused solely on designing faster chips. Instead, manufacturers are racing to ensure every part of the supply chain—from silicon wafer production to advanced packaging to global logistics—can support an unprecedented wave of demand.
This shift means evaluating more than process nodes and transistor density. For electronics engineers, supply chain resilience, packaging availability, and manufacturing capacity increasingly influence component selection, product schedules, and long-term design decisions.
AI changing wafer demand
The scale of that demand became clear in the second quarter of 2026, when global silicon wafer shipments reached a record 3,573 million square inches, up 7.4% year over year. AI servers, high-bandwidth memory (HBM), advanced logic, automotive electronics, and industrial semiconductors are all contributing to this wafer demand.
The current cycle differs significantly from previous semiconductor rebounds. After demand being shifted from smartphones or PCs, AI infrastructure is driving simultaneous growth across advanced logic, memory, and power devices.
According to SEMI, AI infrastructure continues to drive demand for leading-edge logic and memory devices, while the rapid expansion of hyperscale data centers is also increasing demand for power management ICs. As industrial markets recover and inventory levels normalize, semiconductor demand is becoming more balanced across multiple end-use sectors.
The impact extends well beyond cloud infrastructure. Consumer devices, such as smartphones and tablets, continue relying on advanced logic and memory, while automotive electronics for ADAS controllers, battery management systems, and zonal computing platforms are consuming larger volumes of semiconductors. Networking switches, 5G base stations, industrial PLCs and robotics controllers are also increasing silicon content, sustaining demand across multiple process nodes rather than only the most advanced technologies.
The broader demand profile has made supply planning more complex for design engineers. While AI accelerators rely on advanced process nodes, many supporting components—including power management ICs (PMICs), microcontrollers (MCUs), connectivity chips, and analog devices—continue to be manufactured on mature nodes. Modern electronic systems depend on both, making balanced capacity expansion critical across the semiconductor ecosystem.
300 mm fabs remain a priority
Silicon remains the primary raw material for manufacturing chips. After being refined into wafers, its electrical properties can be precisely engineered through controlled doping, making it the foundation of the transistors used in AI processors, memory devices, automotive electronics, and countless other semiconductor applications.
The semiconductor industry’s expansion continues to center on 300-mm wafer production because larger wafers enable manufacturers to produce more chips per fabrication cycle, improving throughput and reducing the cost per die. Those efficiencies make 300-mm fabs the preferred choice for advanced logic, memory, and other high-volume semiconductor devices.
That strategy is evident from the recent investments. GlobalWafers is preparing the next phase of expansion at its advanced 300-mm wafer facility in Sherman, Texas, in response to growing customer demand for domestically produced silicon wafers. The plant is the first advanced 300-mm silicon wafer facility built in the United States in over two decades, underscoring broader efforts to strengthen domestic semiconductor supply chains.
Simultaneously, foundries such as TSMC continue expanding advanced fabrication capacity to support AI processors, high-performance computing, and automotive semiconductor demand, highlighting the industry’s broader push to scale leading-edge manufacturing.
For electronics engineers, continued investment in 300-mm manufacturing should improve long-term wafer availability. However, securing leading-edge devices will also increasingly depend on how quickly packaging, testing, and logistics infrastructure expand alongside wafer production.
Logistics becoming the next constraint
Higher wafer output does not automatically translate into higher semiconductor availability. Modern semiconductor manufacturing depends on tightly synchronized movement of raw wafers, specialty gases, ultrapure chemicals, photomasks, lithography equipment, and finished devices across multiple continents. A disruption affecting any stage can slow production despite available fab capacity.
Transportation also introduces reliability challenges. Vibration during shipping can generate electrostatic charge through tribocharging, increasing the risk of electrostatic discharge (ESD) for sensitive semiconductor components if they are not properly protected. As wafer volumes continue rising, ESD-safe packaging and handling become increasingly important to ensure that devices arrive ready for assembly and deployment.
Advanced packaging has become another pressure point. AI processors increasingly rely on chiplets, 2.5D integration, HBM stacks, and sophisticated substrate technologies. Even if wafer fabrication keeps pace, shortages in packaging capacity or substrate availability can delay final product shipments.
Engineers designing products with leading-edge processors should evaluate supply chains beyond wafer availability. Long lead times for advanced substrates or packaging services can delay board assembly completion, even when silicon is available. As a result, packaging partners, OSAT capacity, substrate suppliers, and logistics resilience have become critical considerations alongside device specifications and performance.
Building resilience in future designs
Recent supply chain disruptions have encouraged semiconductor manufacturers to diversify production geographically while increasing regional investments in wafer fabrication, materials, and packaging. Government-backed semiconductor initiatives across North America, Europe, and Asia are helping expand domestic manufacturing ecosystems. These efforts reduce dependence on single-region supply chains while improving resilience against geopolitical and transportation risks.
The implications extend into product architecture. Selecting components with multiple qualified manufacturing sources and maintaining flexibility across process nodes can reduce exposure to future capacity constraints.
The record wafer shipment figures suggest upstream silicon availability is improving. However, transforming those wafers into finished electronic systems increasingly depends on synchronized investments across fabrication, advanced packaging, materials handling, and global logistics.
Keeping pace with growing AI demand will require more than expanding silicon wafer manufacturing. Engineers must also account for packaging capacity, logistics resilience, and supplier readiness throughout the design process.
Emily Newton is editor-in-chief of revolutionized.com.
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- The 300-mm Era Begins
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- One-stop advanced packaging solutions for chiplets
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L&T Technology Services Launches AgenticIQ, an End-to-End Agentic AI Platform for Engineering, Manufacturing and Customer Experience
L&T Technology Services, a global leader in Engineering Intelligence Solutions & ER&D Consulting Services, today announced the launch of AgenticIQ, an end-to-end Agentic AI platform purpose-built for engineering and manufacturing organizations. Designed to help enterprises move beyond isolated AI pilots, AgenticIQ enables autonomous, multi-agent workflows across engineering, product development, manufacturing, industrial operations and customer experience, accelerating the adoption of Engineering Intelligence at scale.
As enterprises increase investments in AI, many initiatives continue to struggle to move beyond proof-of-concepts into production. Disconnected engineering systems, manual processes and highly regulated environments often prevent organizations from scaling autonomous AI while maintaining governance, security and operational reliability.
Built on LTTS’ portfolio of Engineering Intelligence solutions, AgenticIQ transforms proven engineering capabilities into specialized, reusable AI agents through a planning-first architecture that is embedded directly into engineering and production workflows and designed to operate within enterprise governance boundaries. The platform helps safeguard critical data, intellectual property and regulatory compliance while laying the foundation for LTTS’ next-generation Engineering Intelligence solutions and an Agentic-led engineering delivery model, enabling faster development and deployment of AI-powered solutions.
Designed for customer-centric engineering and R&D-intensive environments, AgenticIQ supports industries including automotive, industrial manufacturing, medical devices and healthcare, semiconductor, plant engineering and high-tech. Its cloud-agnostic architecture enables organizations to build once and deploy anywhere across cloud and on-premises environments, helping enterprises scale trusted AI while retaining control of proprietary engineering knowledge, workflows and intellectual property.
Amit Chadha, Chief Executive Officer & Managing Director, L&T Technology Services, said, “The next phase of Engineering Intelligence will be defined by how effectively autonomous AI agents collaborate to solve complex industry challenges across engineering, production and customer experience. Over the years, LTTS has built AI-powered engineering solutions that address domain-specific business problems across industries. With AgenticIQ, we are transforming these proven capabilities into reusable AI agents on a unified Agentic AI platform that enables enterprises to rapidly build, orchestrate and deploy next-generation agentic solutions at scale.”
The post L&T Technology Services Launches AgenticIQ, an End-to-End Agentic AI Platform for Engineering, Manufacturing and Customer Experience appeared first on ELE Times.
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