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Murata Brings 3D EM and Thermal Simulation Models to Ansys
Murata Manufacturing Co., Ltd. announces a new collaboration with Synopsys, Inc., enabling users of Synopsys’ simulation tools to navigate directly to Murata’s website to access and download the latest high-performance simulation models from Murata. The collaboration covers Synopsys’ 3D electromagnetic field analysis tool, Ansys HFSS, and thermal analysis tool Ansys Icepak, and marks a significant step toward streamlining the simulation workflow for electronic circuit designers. Murata is also the first company to offer passive component simulation models via Ansys Icepak.
As demand for high-speed, high-capacity communications continues to grow, electronic circuit design has become increasingly complex. Engineers must now account for a range of physical phenomena, from electromagnetic interference (EMI) to component heat generation, within a single design. Addressing these challenges early in the design process is critical; overlooking them can trigger costly redesigns, extend development timelines, and drive up prototyping expenses. This has placed greater pressure on electronic component suppliers to provide ready-to-use, high-quality simulation models that are compatible with the tools engineers already rely on.
Developing accurate models for electromagnetic and thermal analysis is inherently challenging, as both electromagnetic behavior and temperature distribution shift considerably depending on design conditions. Murata’s vertically integrated approach, spanning raw material development and manufacturing through to final product processing, enables the company to draw on an extensive proprietary dataset, resulting in simulation models that closely reflect real-world component performance.
The models are compatible with Ansys 2026 R1. Ansys HFSS supports electromagnetic field analysis and covers Murata’s RF inductors and multilayer ceramic capacitors (MLCCs), while Ansys Icepak supports thermal analysis and covers Murata’s power inductors.
The post Murata Brings 3D EM and Thermal Simulation Models to Ansys appeared first on ELE Times.
Microchip’s Nantes Facility Achieves QML Class Y Certification
Microchip Technology announces that its Nantes facility in France expands its Qualified Manufacturers List (QML) MIL‑PRF‑38535 certification scope to include QML Class Y, reinforcing the company’s commitment to delivering high‑reliability semiconductor solutions for aerospace and defense applications. The Nantes site expanded its certification scope from QML Classes V and Q to now include Class Y.
Microchip’s Nantes site has maintained QML certification to Classes Q and V since 1999, supporting the most demanding space and defense mission requirements. The addition of Class Y certification advances the facility’s capabilities to include additional packaging technologies, including non‑hermetic solutions, enabling higher levels of integration and supporting more advanced semiconductor architectures required by next‑generation military and space programs.
“We’re honored to be a leading supplier of semiconductors to the aerospace and defense industry and continue to deliver the quality and reliability our customers depend on for critical missions,” said Patrick Johnson, senior corporate vice president of Microchip’s Aerospace and Defense Group. “Microchip’s products are in most military applications, and in space, we are virtually in everything that leaves Earth.”
With Class Y certification, the Nantes facility strengthens Microchip’s European manufacturing footprint for high‑reliability devices. The site also holds ESCC QML and AS9100:2018 certifications, positioning it among Microchip’s most highly qualified manufacturing locations for aerospace and defense solutions.
The company’s Nantes facility is equipped to support the qualification and testing of its PIC64 High-Performance Spaceflight Computing (PIC64-HPSC), a series of 64-bit microprocessors (MPUs) that are radiation-hardened and radiation-tolerant for space exploration applications. This capability enhances Microchip’s ability to meet evolving customer requirements for electrical testing, qualification, and long‑term mission assurance in harsh operating environments.
Microchip has worldwide qualification sites in the United States and Europe, each certified to specific military standards and classes aligned with their product focus. In the U.S., the company’s site in San Jose, Calif., is qualified to MIL-PRF-38535 Classes Q, V, and Y, for advanced digital and space applications, while its site in Garden Grove, Calif., supports Class Q for analog and mixed-signal devices. The company’s Lawrence, Mass. facility provides capabilities under MIL-PRF-19500 and MIL-PRF-38534 Classes H and K for discrete and hybrid microelectronics. In Europe, in addition to the Nantes site, Microchip’s facility in Ennis, Ireland, is certified to MIL-PRF-19500 for its discrete manufacturing. These sites ensure consistent high-reliability qualification across regions without reliance on dedicated lab certifications.
Microchip has a broad portfolio of high-reliability solutions designed for the aerospace and defense market, including Radiation-Tolerant (RT) and Radiation-Hardened (RH) MCUs, MPUs, FPGAs, and Ethernet PHYs, power devices, RF products, timing solutions, as well as discrete components from bare die to system modules.
The post Microchip’s Nantes Facility Achieves QML Class Y Certification appeared first on ELE Times.
Vishay Intertechnology Releases New 1 A, 2 A, and 3 A Gen 7 1200 V FRED Pt Hyperfast Rectifiers in SMPC HV Package
Reducing Switching Losses and Increasing Efficiency, Devices Combine Low Qrr Down to 105 nC and VF Down to 1.45 V With Low Junction Capacitance, Fast Recovery Time, and Minimum Creepage Distance of 5.4 mm.
Vishay Intertechnology, Inc. expands its Gen 7 platform of 1200 V FRED Pt Hyperfast rectifiers with six new devices in the eSMP series SMPC HV package. Optimized for industrial, automotive, and energy applications, the 1 A, 2 A, and 3 A rectifiers not only offer the best trade-off between reverse recovery charge (Qrr) and forward voltage drop for devices in their class, but also provide the lowest junction capacitance and recovery time.
The Vishay Semiconductors rectifiers release include the VS-E7SX0112-M3V, VS-E7SX0212-M3V, and VS-E7SX0312-M3V, and AEC-Q101 qualified VS-E7SX0112HM3V, VS-E7SX0212HM3V, and VS-E7SX0312HM3V. To reduce switching losses and increase efficiency, the devices combine a fast recovery time of 50 ns with Qrr down to 105 nC typical, forward voltage drop down to 1.45 V, and junction capacitance down to 7.25 pF. The robust rectifiers offer non-repetitive peak surge current up to 70 A in a compact package measuring 4.3 mm x 6.5 mm with a low 1.1 mm profile, which is footprint-compatible with the TO-277A. Combined with a minimum 5.4 mm creepage distance and molding compound with a comparative tracking index (CTI) ≥ 600 (Material Group I), the devices reduce component counts and lower BOM costs based on IEC 60664-1 requirements for high voltage applications.
The VS-E7SX0112-M3V, VS-E7SX0212-M3V, VS-E7SX0312-M3V, VS-E7SX0112HM3V, VS-E7SX0212HM3V, and VS-E7SX0312HM3V will serve as clamp, snubber, and freewheeling diodes in flyback auxiliary power supplies and high-frequency rectifiers for bootstrap driver functionality, while providing desaturation protection for the latest fast-switching IGBTs and high-voltage Si / SiC MOSFETs. Typical applications for the devices include industrial drives and tools, on-board chargers and motors for electric vehicles (EV), energy generation and storage systems, and Ćuk converters and industrial LED SEPIC circuitry.
The rectifiers feature a planar structure and platinum-doped lifetime control that guarantee system reliability and robustness without compromising on performance, while their optimized stored charge and low recovery current minimize switching losses and reduce power dissipation. RoHS-compliant and halogen-free, the devices feature a Moisture Sensitivity Level of 1 in accordance with J-STD-020 and offer high temperature operation to +175 °C.
Device Specification Table:
| Part # | IF(AV) (A) | VR (V) | VF at IF (V) | trr (ns) | Qrr (nC) | CT (pF) | IFSM (A) | Package | AEC-Q101 |
| VS-E7SX0112-M3V | 1 | 1200 | 1.45 | 50 | 105 | 7.25 | 19 | SMPC HV | No |
| VS-E7SX0112HM3V | 1 | 1.45 | 105 | 7.25 | 19 | Yes | |||
| VS-E7SX0212-M3V | 2 | 1.6 | 165 | 9.0 | 21 | No | |||
| VS-E7SX0212HM3V | 2 | 1.6 | 165 | 9.0 | 21 | Yes | |||
| VS-E7SX0312-M3V | 3 | 1.45 | 240 | 20 | 70 | No | |||
| VS-E7SX0312HM3V | 3 | 1.45 | 240 | 20 | 70 | Yes |
Samples and production quantities of the new Gen 7 rectifiers are available now, with a lead time of eight weeks.
The post Vishay Intertechnology Releases New 1 A, 2 A, and 3 A Gen 7 1200 V FRED Pt Hyperfast Rectifiers in SMPC HV Package appeared first on ELE Times.
4-20mA to 0-20mA converter sips mere microamps
Circuits for converting 4 to 20mA analog current loop signals to 0 to 20mA may be hot topics, but hot implementations of those circuits are not.
Circuit designs for conversion of 4 to 20mA analog current loop signals, which are ubiquitous in process monitoring and control, to 0 to 20mA are a hot topic recently. “Hot topic” is a perfect description because typical examples of such converters can dissipate half a Watt. Some cook even hotter than that! This results in some very un-green complications like TO220 packaged power pass transistors sporting substantial heatsinks. Would Greta T. approve? I think not!
Wow the engineering world with your unique design: Design Ideas Submission Guide
The design in Figure 1 offers a cool (and maybe even useful) efficiency improvement. It thriftily recycles most of the 4 to 20mA input current to generate the 0 to 20mA output while needing only microamps from its own local power supply. It consumes merely 250uA x 24v = 6mW (typical) and dumps only similar single-digit milliwatts from Q2 (which is the closest thing it has to a pass transistor). That’s not even enough heat to make a TO92 tepid.
Here’s how it works:
Figure 1 This circuit’s operation is governed by the following equation: Iout = Iin – 4mA(1 – (Iin – 4mA)/16mA)) = 1.25(Iin – 4mA). The maximum current drawn from the local V+ supply is only 1/80th of max Iout, translating to an 80:1 efficiency gain. Asterisked resistors are 0.5% precision or better.
The 4 to 20mA input current (99.95% of it, to be precise) passes through current sense resistor R1 and from there to the load, generating 200mv to 1v as Iin goes from 4 to 20mA. The voltage to current converter R1+A1+Q1 makes that into Ic1 = Iin R1/R2 = 2uA to 10uA as the input to current to voltage converter R5+A2+Q2+R4, generating 0.5 to 2.5v across R5. A2 compares this to A3’s 2.50v internal reference, forcing Q2 to conduct so that the sum Vr4 + Vr5 = 2.5v.
Thus Ic2 = (2.5 – Vr5)/R4 and it decreases linearly from 4mA to zero as Iin increases from 4 to 20mA. The net effect is to force Q2 to subtract a linearly decreasing 4 to 0mA from Iin, so that its 4 to 16mA span is corrected to 0 to 20mA in Iout. In other (mathspeak) words: Iout = Iin – 4mA(1 – (Iin – 4mA)/16mA)) = 1.25(Iin – 4mA)
The payoff is that 98.8% of Iout comes from recycled Iin instead being sucked anew from V+.
V+ isn’t critical and needs only be sufficient to provide the compliance required by the (grounded) load. R3 needs to provide 50uA bias for the A3pin3 shunt reference, so R3 = (V+ – 2.5)/50uA = 390k for V+ = 24v. Noncritical Z1 provides a few volts of headroom for the transistors. The total voltage drop from input to output is 5.6v.
Finally, there’s a caveat. In the event of complete loss of the nominal 4 to 20mA input current, A2 will drive Q2 into saturation. This won’t damage anything, but will force A2 to draw 5mA from V+ to supply the required Q2 base current.
Stephen Woodward‘s relationship with EDN’s DI column goes back quite a long way. Over 200 submissions have been accepted since his first contribution back in 1974. They have included best Design Idea of the year in 1974 and 2001.
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The post 4-20mA to 0-20mA converter sips mere microamps appeared first on EDN.
Coherent to receive $50m US CHIPS Act funding to expand Sherman 6-inch InP fab
Coherent to receive $50m US CHIPS Act funding to expand Sherman 6-inch InP fab
Phlux announces beta-sample availability of Apex 200µm Noiseless InGaAs APD receiver modules for ultra-low-light detection
Phlux announces beta-sample availability of Apex 200µm Noiseless InGaAs APD receiver modules for ultra-low-light detection
CSA Catapult appoints head of quantum
CSA Catapult appoints head of quantum
Rohde and Schwarz Leads GCF 3GPP NR-NTN Validation with Record Test Cases
Rohde & Schwarz is driving the commercialization of 5G-based New Radio non-terrestrial networks, with successful certification of the highest number in GCF conformance test cases for NR-NTN to date. The validation covers all three domains, RF, RRM, and PCT.
Following the successful validation of the first 5G-based NR-NTN at the PTCRB (PCS Type Certification Review Board), Rohde & Schwarz continues its efforts to enable validation at the GCF (Global Certification Forum). The validated test cases within GCF WI-555 (Work Item) are defined in accordance with the 3GPP test specifications for RF (Radio Frequency), RRM (Radio Resource Management), and PCT (Protocol Conformance Testing) and were executed with Rohde & Schwarz conformance test solutions.
All measurements were conducted on the R&S TS8980 Conformance Test Platform, the R&S TS-RRM, and the CMX500 in frequency range 1 (FR1), verifying the latest NR-NTN chipset from Samsung as the device under test (DUT).
3GPP conformance testing is essential for ensuring that devices and networks comply with global standards. 5G NR-NTN testing presents challenges that extend beyond those encountered in traditional terrestrial networks, primarily due to the vastly different operating environment and the dynamic nature of satellite-based communication.
At the core of the Rohde & Schwarz conformance test solutions is the CMX500 5G one-box signaling tester, which also supports early research and development through integrated fading and channel emulation, along with an intuitive tool for visualizing satellite constellations – all in a single-box test setup. In addition, the user-friendly R&S CONTEST test system software platform facilitates the seamless execution of 3GPP test cases.
The post Rohde and Schwarz Leads GCF 3GPP NR-NTN Validation with Record Test Cases appeared first on ELE Times.
JX expanding InP substrate production capacity again to meet data-center optical communications demand
JX expanding InP substrate production capacity again to meet data-center optical communications demand
ROHM Launches AG16xFNxx Series MOSFETs for Automotive 48V Power Supply Systems
ROHM develops the “AG16xFNxx Series,” a lineup of 80V power MOSFETs designed for 48V power supply systems, which are becoming increasingly common in automotive applications.
In the automotive sector, power demand is increasing, particularly in high-end vehicle models. 48V power supply systems are gaining attention as a highly efficient alternative to conventional 12V power supply systems. With widespread adoption expected around 2030, there is a growing need for 80V power MOSFETs capable of delivering even lower power losses than standard 100V devices.
ROHM’s new products enable downsizing in comparison to standard automotive MOSFET packages such as the TO-252 (6.6 × 10.0mm) by adopting the HPLF5060 (4.9 × 6.0mm) and DFN3333 (3.3 × 3.3mm) packages.
The HPLF5060 features Gull-Wing Leads, while the DFN3333 features Wettable Flank Technology, which contributes to improved reliability on PCBs (Printed Circuit Boards). Furthermore, by adopting Copper Clip Junction Technology to enhance heat dissipation, these devices are capable of handling high currents. All models comply with the automotive reliability standard AEC-Q101, ensuring high reliability.
The product lineup of these packages will be further expanded in the near future. In addition, development of TOLG (TO-Leaded with Gullwing, 9.9 × 11.7mm) packaged products has begun, with continued expansion of the lineup of high-power, high-reliability 80V MOSFETs.
Application Examples
Automotive 48V systems: Main inverter control circuits, electric motors, electric water pumps, etc.
The post ROHM Launches AG16xFNxx Series MOSFETs for Automotive 48V Power Supply Systems appeared first on ELE Times.
🔵 День вступника 2026
27 червня відбудеться День вступника КПІ ім. Ігоря Сікорського. Це найкраща можливість наживо познайомитися з великою КПІшною родиною та перспективними сферами для розвитку.
Model your IPs and your NoCs
When chip design and verification teams start a new project, they recognize the need for models that capture the design at a high level of abstraction. However, they tend to focus on acquiring or creating models of the IP blocks used to implement the device’s core functionality, while overlooking network-on-chip (NoC) interconnect IP until it’s too late.
Modeling and simulation evolution
As chip designs grew from a handful of gates in the 1970s to hundreds of IP blocks connected by complex interconnect fabrics in the 2020s, modeling and simulation evolved to keep pace. Early approaches modeled everything at the gate level, providing complete visibility, but they quickly became impractical as complexity increased.
The industry’s first major step up in abstraction was the register transfer level (RTL). These models describe how data moves between registers on each clock cycle, maintaining bit-level and cycle-level accuracy. To this day, RTL simulation remains the gold standard for functional correctness and final sign-off. The trad-eoff is speed. Because the RTL models every signal transition, meaningful simulations can take hours or even days.
Figure 1 The integration of functional blocks and interconnects increased over time. Source: Arteris
To address this, engineers introduced cycle-accurate models. These preserve timing at the clock-cycle level but avoid modeling every individual signal. They capture events as they happen without describing every bit flip, thereby making them ideal for performance analysis. Designers can evaluate latency, bandwidth, and contention with high confidence while running simulations fast enough to explore architectural alternatives.
At an even higher level of abstraction is transaction-level modeling (TLM). Rather than modeling signals and clock cycles, TLM focuses on high-level transactions, such as moving data across the system. By abstracting away low-level implementation details, TLM can enable simulations that run orders of magnitude faster than RTL. This speed makes it practical to test hundreds of scenarios and quickly explore different design options.
TLM models also underpin virtual prototypes, enabling software to run on a simulated hardware platform long before silicon is available. This enables early hardware–software co-verification and faster overall development.
System complexity increases
Modern system-on-chips (SoCs) are sophisticated ecosystems in which processors, accelerators, memory subsystems, and NoC interconnect fabrics must work in concert with complex software stacks.
This interaction adds another layer of complexity because software must be verified in the context of the hardware throughout the design process. RTL simulation continues to play a critical role, particularly for final validation and corner-case debugging. However, it’s simply too slow to support meaningful software development at scale. Higher-level models, especially TLM-based virtual prototypes, enable software teams to begin work early while hardware teams continue refining the design.
If all of this sounds challenging, it becomes even more so in the era of chiplets and multi-die systems. Modern designs increasingly partition functionality across multiple dies, sometimes mixing process nodes, vendors, and packaging technologies. Data must move not only within a die, but across die boundaries. Some of this traffic is non-coherent, while other portions must maintain cache coherency, depending on the system architecture.
Figure 2 Here is how die-to-die options look like in NoC designs. Source: Arteris
The result is a heterogeneous communication fabric that is far more complex than the simple buses of the past. In such environments, performance is no longer determined solely by the compute elements themselves. Instead, it depends heavily on how efficiently data can move between them. Increasing data movement complexity—driven by heterogeneous compute, coherence requirements, and chiplet architectures—makes overall system performance difficult to predict without appropriate modelling.
Beyond the IP blocks
That same modeling discipline must extend to the NoC interconnect. In modern designs, NoCs are no longer passive conduits. They are first-order determinants of system performance. A contemporary SoC may contain multiple NoCs, some coherent, some non-coherent, and some forming bridges between chiplets. These interconnect fabrics are highly configurable, with parameters governing topology, bandwidth, arbitration policies, buffering, and quality-of-service (QoS) mechanisms.
This means NoCs must be modeled at the same levels of abstraction as the rest of the system. Transaction-level models support rapid exploration and system-level integration. Cycle-accurate models enable detailed performance analysis, and RTL models remain essential for final verification and implementation. Crucially, these models must be consistent with one another, enabling smooth progression from architectural intent to implementation reality.
Equally important is the ability to analyze the results generated by these models. These analysis capabilities enable designers to examine key performance indicators—including bandwidth utilization, latency, congestion, contention, buffering efficiency, and QoS behavior—across the NoC fabric. Rather than forcing engineers to sift through enormous amounts of low-level simulation data, the modeling environment presents targeted performance insights that help teams quickly identify bottlenecks, validate architectural assumptions, and compare alternative configurations.
This kind of system-level analysis is valuable in complex chiplet-based designs. Architects can use automatically generated SystemC TLM models to study NoC behavior earlier and help create and iterate NoC topologies faster.
From Exploration to implementation
Increasingly, commercial NoC providers are offering higher-level models alongside their RTL implementations. In many cases, however, these models are added as an afterthought, a bolt-on capability that may not fully reflect the behavior of the final implementation. What’s emerging as a best practice is a more integrated approach in which modeling is not an add-on but a foundational element of the design flow.
Arteris, for instance, offers FlexGen interconnect IP for non-coherent interconnects and Ncore for cache-coherent fabrics. These solutions are supported by a continuum of models, from transaction-level to cycle-accurate to RTL, designed to be consistent and correct by construction.
The result is a design methodology that enables teams to explore, validate, and refine their architectures early, with confidence that their insights will carry forward into implementation. In a world where performance margins are tight, schedules are unforgiving, and complexity continues to grow, the ability to move fast and get it right the first time may be the most valuable model of all.
Rocco Jonack is principal corporate application engineer at Arteris, where he works on advanced SoC architecture modeling, virtual prototyping, and performance analysis for complex semiconductor systems.
Related Content
- SoC design: What’s next for NoCs?
- How NoC architecture solves MCU design challenges
- Smarter SoC Design for Agile Teams and Tight Deadlines
- Why verification matters in network-on-chip (NoC) design
- NoC configuration tool takes makes complex SoC design easier
The post Model your IPs and your NoCs appeared first on EDN.
V2 vs V1 blueprint
 | Sound meter with tower light and projector message device for classroom a teacher is buying [link] [comments] |
🔗 Проєкт Професійного стандарту «Оператор з обслуговування та експлуатації когенераційних установок»
Національним технічним університетом України «Київський політехнічний інститут імені Ігоря Сікорського» з метою створення умов для запровадження системи професійних кваліфікацій для підтвердження кваліфікації оператор з обслуговування та експлуатації когенераційних установок було подано заявку до Національного агентства кваліфікацій (від 25.09.2025, № 1177) на розроблення Професійного стандарту «Оператор з обслуговування та експлуатації когенераційних установок» та створено відповідну Робочу групу.
I gave this toaster anxiety so it would do my bidding
 | I am really autistic about the precision of temperature in my projects, and I found a cheap toaster oven for 14$ the perfect size for my work space, decided to replace the bimetallic thermostat with custom electronics and control circuitry, it was an amazingly fun project! hope you all enjoy this dumb project! and remember, if you mess with 120V BE CAREFUL! programming listed on github, [link] [comments] |
Metasurface plus photoelectric quantum effect yields sensitive THz detector
I’m always interested in how researchers, scientists, engineers, and manufacturing specialists leverage apparently unrelated advances to their own advantage for devising innovative techniques and advances. This phenomenon is not new, of course; it’s been one of the driving forces behind technological advances for hundreds of years in situations ranging from fairly modest to some that are impressively esoteric.
This seems to be the case especially for sophisticated sensors. The latest one I have seen addresses the challenge of detecting terahertz energy. It’s not news to this audience that the terahertz region of the electromagnetic spectrum, generally defined as 100 GHz to 10 THz, has many barriers when developing complete viable systems. It’s informally called the “THz gap” where the frequencies are too high and the wavelengths too short for most electronic components; yet too low and too long, respectively, for using optical ones.
A deep-physics concept
Addressing this issue, a joint team at the University of Cambridge and Swansea University (both in the U.K.) took advantage of some “new” physics. Their sensor merges a metasurface with a recently discovered quantum physics effect that is a spinoff of the well-known photoelectric effect.
In the photoelectric effect, there is the emission of electrons (current) from a material (usually a metal) when it’s struck by electromagnetic radiation such as light with high-enough energy. In contrast, their terahertz detector makes use of the in-plane photoelectric effect (IPPE), where incoming terahertz photons transfer energy to electrons that are confined within a two-dimensional electron gas. Those energized electrons cross a carefully designed potential step, generating an electrical current that can be measured.
If you are not familiar with the photoelectric effect, it has a major place in the history of modern quantum physics. The effect had been observed since the latter half of the 1880s with solid experimental data, but non-quantum physics could not explain the data and in fact was at odds with the data. Albert Einstein proposed a radically new explanation in his seminal 1905 paper “On a Heuristic Viewpoint Concerning the Emission and Transformation of Light”—one of four truly significant papers he had published in that “miraculous year”, which resulted in the Nobel Prize award in 1921.
That photoelectric effect, however, is different in the in-plane version, a phenomenon that was observed only recently, in 2022 (“An in-plane photoelectric effect in two-dimensional electron systems for terahertz detection”). In the IPPE quantum process, incoming terahertz photons transfer energy to electrons confined within a two-dimensional electron gas. Those energized electrons cross a carefully designed potential step, generating an electrical current that can be measured.
Unlike conventional photoelectric detectors, this mechanism does not require photons to exceed a minimum energy threshold. Because the process occurs entirely within the plane of the material, it also avoids several efficiency limitations that affect traditional detector designs.
While earlier detectors using this concept showed promising performance, they suffered from one major drawback. They captured only a small portion of the incoming radiation because they relied on single-antenna structures.
A new approach
To overcome that limitation, the team devised a metasurface with a patterned structure that concentrates electromagnetic energy into regions much smaller than the wavelength of the incoming radiation. In the new design, a repeating “brickwork” pattern gathers terahertz waves and channels them into narrow gaps where detection takes place (Figure 1).
Figure 1 Schematic diagram of the MetaPETS detector with the brickwork metamaterial (a). Zoom-in view showing a unit cell indicated by a black dashed rectangle. The unit cell sizes in the 𝑥- and 𝑦-directions, 𝑑𝑥 and 𝑑𝑦, are indicated (b). Zoom-in view highlighting the capacitive gap, illustrating the width 𝑤 of the capacitor in the lateral (𝑥)-direction, and the gap size 𝑔 of the capacitor. The 2DEG is depleted along the edge of the mesa, as indicated, causing the area of the conducting 2DEG to be offset inwards from the lithographically defined mesa edge (c). Zoom-in view highlighting the summation of photocurrents generated by the PETS detection elements at the lower right corner. The electron flow occurs within the 2DEG, and its direction is shown by the red arrows. Without loss of generality, we show an example with gate 1 positively biased and gate 2 negatively biased (d). Photocurrent detection circuit (e). Source: SPIE Digital Library
Each of these tiny gaps functions as an individual detector. By distributing many of them across the metasurface and connecting them electronically, the researchers were able to combine their outputs into a stronger overall signal.
But that was only the first step. Individual photoelectric tunable-step (PETS) detector elements were then integrated into the capacitive gaps, as they experience the strongest electromagnetic fields. This ensures optimal coupling of the metasurface to the detection elements and significantly boosts the detection sensitivity compared to simply connecting the elements in parallel.
Fabrication relied on a semiconductor structure containing a high-mobility electron gas. The manufacturing process closely resembles techniques already used to produce field-effect transistors, making future integration with electronic circuits more feasible. Since the metasurface itself concentrates the incoming radiation, the detector does not require external focusing components such as silicon lenses and their precise alignment, which simplifies assembly, reduces cost, and could make large-scale manufacturing easier.
In tests, the detector was cooled to 10 K and exposed to radiation near 1.9 THz. It generated a clear electrical signal that matched the on and off pattern of the incoming radiation. Measurements showed a responsivity of 2.7 amperes per watt. The proof-of-concept device also achieved an external quantum efficiency of 2.1% at 1.9 THz.
Figure 2 Time-averaged photocurrent in response to the 1.881 THz quantum cascade laser (QCL) radiation, measured in the source-drain circuit while mechanically blocking and unblocking the THz waveguide (WG). The two gates are biased at +0.76 V and −0.095 V, respectively (a). Real-time photocurrent measurement using an oscilloscope, showing the response to a pulse emitted by the QCL during its on time with 100 sweeps averaged. The two gates are biased at +0.76 V and −0.095 V, respectively (b). 2D maps are shown as a function of the two gate voltages: photocurrent (c) and four-wire conductance of the device (d). Source: SPIE Digital Library
According to the researchers, this represents roughly a 20-fold improvement over previously demonstrated PETS detectors. Much of that gain comes from the metasurface’s ability to capture more incoming radiation and direct it into the active detection regions.
The work is described in both theory and practical facets in their readable paper “Quantum metasurface-based photoelectric tunable-step terahertz detector” published in Advanced Photonics. Of course, they note that there’s more work to be done. The researchers believe the technology could eventually operate at temperatures higher than those required by many competing detector designs. Similar PETS devices have already demonstrated performance at temperatures reachable using compact cryocoolers rather than liquid helium.
Have you used a highly sophisticated sensor that blends advanced technologies, or had to innovate and implement such a sensor yourself? What were the unexpected challenges you encountered?
Bill Schweber is a degreed senior EE who has written three textbooks, hundreds of technical articles, opinion columns, and product features. Prior to becoming an author and editor, he spent his entire hands-on career on the analog side by working on power supplies, sensors, signal conditioning, and wired and wireless communication links. His work experience includes many years at Analog Devices in applications and marketing.
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The post Metasurface plus photoelectric quantum effect yields sensitive THz detector appeared first on EDN.
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