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An 8-key piano on a breadboard with an Arduino Uno R3, eight 6×6 mm tactile buttons and a passive piezo buzzer. Each key you press plays a note of the C major scale, from C4 at 262 Hz up to C5 at 523 Hz. That is enough to play tunes like Twinkle Twinkle Little Star. No shield, no external library and no soldering are needed: just a breadboard, jumpers and a USB cable.

Assembly is the quickest part. The tactile buttons go into the breadboard straddling the centre channel, one next to the other. Each button has one side connected to an Arduino digital pin and the other side to GND. The passive buzzer has its positive leg on pin D10 and its negative leg on GND. A jumper connects the breadboard’s GND rail to the board’s ground.

The keys occupy pins D2 to D9, eight consecutive digital pins. The Arduino Uno has 14 digital pins (D0-D13) and 6 analog pins usable as digital inputs, so there is plenty of room to add keys in a later version. For the keys, the catalogue has a 6×6 mm PCB mini pushbutton, the same format used in the project.

INPUT_PULLUP and the tone() function in the firmware

The code uses no library: it relies on the tone() function built into the Arduino IDE. Each button is connected between a pin and GND, so the firmware enables the internal pull-up resistor with INPUT_PULLUP. As a result the pin reads HIGH when the key is at rest and LOW when it is pressed. The code scans the eight pins, stores the first key pressed and calls tone() with the associated frequency.

The comparison if (pressedKey != lastKey) makes tone() fire only once per press, instead of repeating the call on every pass of the loop. When no key is pressed, the code calls noTone() and the sound stops. The serial monitor opens at 9600 baud and is used to check which keys are being read during testing.

• Key 1: C4 at 262 Hz
• Key 2: D4 at 294 Hz
• Key 3: E4 at 330 Hz
• Key 4: F4 at 349 Hz
• Key 5: G4 at 392 Hz
• Key 6: A4 at 440 Hz
• Key 7: B4 at 494 Hz
• Key 8: C5 at 523 Hz

The piano is monophonic, and that is a limitation of the tone() function: it generates only one frequency at a time. So if you press two keys together, the one with the lower number wins, that is, the first one the loop encounters. Anyone who wants real chords has to change approach, for example generating the waveforms by hand with a timer.

Passive buzzer, current draw and an alternative speaker

The passive piezo buzzer works from 3.3V to 5V and draws less than 30 mA, so you can drive it straight from an Arduino pin without a transistor. Its best output is around 2-4 kHz, while the notes of this piano run from 262 Hz to 523 Hz. The sound comes out, but don’t expect concert volume: to raise the sound pressure, a speaker is a better bet.

Instead of the buzzer you can use an 8 ohm speaker with a 100 ohm resistor in series. The resistor limits the current and protects the pin. On top of that, the sound is fuller on the low notes of the scale. The rest of the circuit does not change: positive on D10, negative on GND.

Rebuilding the project takes only a few parts: an Arduino Uno R3, eight 6×6 mm tactile buttons, a passive piezo buzzer, a breadboard, jumpers and a USB cable. The cost is low and so is the difficulty. In fact it is an ideal first project for learning about digital inputs, INPUT_PULLUP and the tone() function, and you can finish it in an evening.

If you want to see the build in action, on the maker’s site you will find the video with the piano played key by key. There you can see how the buzzer behaves on the different notes before soldering or buying anything.

Source: https://www.circuitschools.com/arduino-piano-project-with-8-keys-build-a-simple-piano/

Related products

• PCB Mini Pushbutton – 6x6x7 mm

The post Build an 8-Key Piano on a Breadboard with Arduino appeared first on Open Electronics.

AI processing, inference specifically, remains mostly a cloud-centric function, but not for long. Whether it shifts to client devices in tandem or completely, who will win?

Way back in December 2022, in the introduction to a teardown of an autonomous object-tracking accessory for a smartphone’s integrated camera, I more broadly positioned the trade-off between cloud- and edge-based AI processing, with the latter exemplified by the widget.

One common way to reduce the device BOM is to offload as much of the total required processing, memory and other required resources to other connected devices. A “cloud” server is one common approach, but it has notable downsides that also beg for consideration from the device supplier and purchaser alike, such as:

• Sending raw data up to the “cloud” for processing, with the server subsequently sending results back to the device, can involve substantial roundtrip latency. There’s a reason why self-driving vehicles do all their processing locally, for example!
• Sending data up to the “cloud” can also engender privacy concerns, depending on exactly what that data is (consider a “baby cam”, for example) and how well (or not) the data is encrypted and otherwise protected from unintended access by others.
• Taking latency to the extreme, if the “cloud” connection goes down, the device can turn into a paperweight, and
• You’re trading a one-time fixed BOM cost for ongoing variable “cloud” costs, encompassing both server usage fees (think AWS, for example) and connectivity bandwidth expenses. Both of those costs also scale with both the number of customers and the per-customer amount of use (both of each device and cumulatively for all devices owned by each customer).

Those points all remain valid nearly four years later, IMHO at least, although an added cloud-based set of downsides now also begs for inclusion in the list. Back then, the AI data center (also called a hyperscaler) build-out phenomenon was still in its comparative infancy, with much of the compute capability then coming online intended for cryptocurrency mining (which ironically has subsequently been redirected to deep learning processing). Nowadays, conversely, the data center phenomenon is in fuller stride, with understandable backlash from the broad populace.

• Speculative investment deals, often “circular” in nature (a hardware supplier invests in a data center developer, for example, with the latter promising to use the former’s chips and software in exchange), result in frequent stock market volatility and broader growing “bubble market” concern.
• Governmental jurisdictions provide lucrative tax breaks and other incentives to data center developers, even though any tangible increase in employment for the local populace will be time-restricted to only the subsequent duration of construction.
• Data center energy demands are substantially incremental, necessitating in-parallel built-outs of additional power plant facilities whose costs are assumed by all.
• The incremental energy predominantly comes from hydrocarbon-based power sources such as coal and natural gas, with substantive pollution and noise impacts.
• Water demands for cooling purposes are equally sizeable, redirecting and draining aquifer reserves no matter whether the sources are fresh, recycled, or a mix of these.
• And the facilities are massive in size, gobbling up available open space as well as fields formerly used for various agricultural purposes.

Edge demands

And here’s what I wrote about the edge processing alternative back in late 2022.

Another popular BOM-slimming approach involves leveraging a wired or (more commonly) wireless tethered local device with abundant processing, storage, imaging, and other resources, such as a smartphone or tablet. This technique has the convenient advantage of employing a device already in the consumer’s possession, which he or she has already paid for, and for which any remaining “cloud” processing bandwidth involved in implementing the complete solution he or she will also bankroll. The latency is also notably less than with the pure “cloud” approach, privacy worries are lessened if not fully alleviated, and although the smartphone’s connection to the “cloud” may periodically go down, the connection between it and the device generally remains intact.

All still valid, too, IMHO. And add to the list the facts that the alluded-to enhanced privacy not only applies in a general sense but also specific to keeping personal data out of the “cloud” provider’s training data set, and that the cessation of ongoing-cost outflows involves not only hardware but also monthly expenses for AI service subscriptions (if you’re a consumer) or tokens (for developers). However, the only downside I mentioned back then was the following.

The notable requirement for the manufacturer here is that whatever device-offloading application is running on the tethered mobile device must comprehend all common mobile operating systems (predominantly Android and iOS, along with the related iPadOS for tablets, nowadays) and the various devices that run on them, and it must also evolve as both operating systems and hardware evolve. Otherwise, the application will sooner-or-later stop meaningfully working, as will the device it’s tethered to.

Admittedly, in my defense, the device I was showcasing in that teardown heavily depended on a smartphone-based app, so it made at least some sense to focus on that nuance. But although I noted that the app leveraged the smartphone’s built-in image capture and processing resources, thereby obviating the need for costly redundancy in the accessory, I overlooked the not-insignificant and growing burden of that processing, along with the associated necessity for adequate memory—both nonvolatile for storage and volatile for code execution and temporary data—and how those memory capacity and speed needs might expand in the future.

Now we know. Not only are the not-unlimited supplies of SSDs (along with HDDs, interestingly, trading off raw performance and energy consumption for raw capacity and cost-per-bit) and DRAM being redirected to data centers, the required capacities of each in PCs, smartphones and the like for today’s edge AI processing functions are increasing in lockstep. Take, for example, the Gemini AI models embedded in latest-generation Chrome browser installs, which take up at least 4 GBytes of storage space. Or the Apple Intelligence included with iOS 27, now required vs. optional with the version 26 O/S predecessor, and using up to 14 GBytes of capacity. The similarly required-by-default AI model suite included with MacOS 27? 12-30 GBytes in size, although open source can come to the rescue in this case.

While a company called PrismML, which specializes in quantizing and otherwise compressing deep learning models for use in resource-constrained systems, was able to shrink Alibaba’s Qwen3.8 27B open-source model by between 9-10x while still matching 98% of Qwen’s aggregate benchmark scores, the resultant model was still 5.9 GBytes. Perplexity’s Portable Computer for local on-computer model storage and processing? 20 GBytes. And of course, storage needs in both cloud and edge scenarios will further increase in the future.

Hybrid intermediaries

One of many ironies here is that a not-insignificant percentage of the processing resources in data centers find use, at least on a part-time basis, not for inference but for training—initial training, periodic retraining to counteract performance decay, iterative training to encompass new and expanded datasets, and transfer learning to adapt frontier models for specific tasks. OpenAI recently reported, for example, that the training run for its latest-generation “Astra” GPT-6 fully consumed more than 100,000 GPUs. These particular operations are compute-intensive and highly parallelizable, which explains why GPU-derived architectures have come to the fore in this particular application.

For inference, conversely, only the prefill portion of the total task is parallelizable, therefore GPU-amenable (albeit not necessarily GPU-optimal). The subsequent decode portion of the total inference pipeline is conversely memory-intensive, from both capacity and bandwidth standpoints, the latter rationalizing the ascendance of advanced HBM approaches.

That all said, any claim that inference is instead going to transition fully to the edge in all cases is, once again IMHO, a pipe dream. Autonomous vehicles and other specific scenarios? Sure. But there are plenty of other applications where latency and privacy (which can alternatively be handled via encryption, anyway) aren’t an issue but the need for access to sizeable trained models is, and servers rule in such cases, as I noted in late-2024 follow-up coverage.

Hybrid approaches, in which a base level of inference occurs locally with cloud resources tapped as-needed for beefier-function requirements, will be increasingly common going forward. Alternatively, other local-ish (or, if you prefer, local networked cloud) scenarios are also beginning to emerge. Take, for example, NVIDIA’s Personal AI Router (PAIR), which enables spreading the overall inference (including agents) processing task across multiple LAN-connected computers (including non-NVIDIA-based Macs). Or instead consider storing the models on a LAN-shared NAS for common access, although RAM limitations will likely preclude full inference processing there.

Revenge of the commodity (and the proprietary)

The obvious beneficiaries of these trends include memory and broader mass storage suppliers. I admittedly find it ironic that after countless commodity boom-and-bust cycles, several of which I personally lived through from the supplier side, the semiconductor memory industry may have finally found a path to a predictable and otherwise sustainable business model.

The other potential winners are inference chip and IP core suppliers. As mentioned earlier, whereas GPU-based architectures will likely continue to reign into the future from a training standpoint (if for no other reason than proprietary software tools prevalence), an ever-increasing percentage of total growth in the AI processing space will instead be in inference, where toolset lock-ins are more fungible and other parallel-processing, not to mention more memory-centric architectures may indeed end up more optimal for the necessary tasks.

What are your thoughts on the trends I’ve identified, their root causes and beneficiaries, and their short- and long-term outcomes? Let me and your fellow readers know in the comments!

—Brian Dipert is the associate editor, as well as a contributing editor, at EDN.

Related Content

• iJoy’s chase face- and object-tracking widget: A robot or tripod it isn’t
• Made by Google 2026: This limited silicon-supply situation really sucks
• The Microsoft-reminiscent iPhone Duo: How much customer holding-and-folding is necessary to keep Apple from folding on the experiment?
• Training and inference: Two faces of AI compute
• HBM memory and AI processors: Happy together

 

The post Cloud to edge AI: If and when, to what degree, and how and why appeared first on EDN.

Cadmium telluride (CdTe) thin-film photovoltaic (PV) module maker First Solar Inc of Tempe, AZ, USA has inaugurated the first phase of its new $330m facility in Gaffney, Cherokee County, South Carolina, which onshores final production processes for the firm’s Series 6 Plus modules initiated by its international fleet...

OfficeNet, an HR technology company serving more than 10 million users across 500+ enterprises, has launched Smart Factory Solutions for large manufacturing companies. The platform is designed for organisations with over 10,000 employees and helps them manage workers across multiple locations and shifts. It brings workforce management, administrative tasks and key factory operations together on a single digital platform.

The platform brings key workforce tasks, including worker allocation, contractor management, production planning, expense claims, attendance and payroll, into one system. This reduces manual work, gives managers a clearer view of workforce availability and helps them assign workers more efficiently. It also helps manufacturers manage employees across multiple factories, locations and shifts while maintaining consistent processes.

The Officenet Smart Factory platform also covers the employee lifecycle from joining to exit, with centralised records, reporting and AI-powered analytics, along with biometric attendance, mobile absence tracking, multiple pay master’s and statutory compliance. This enables HR and business teams to move from fragmented workforce administration towards a more connected, data-led approach.

Sonali Chowdhry, CEO, Officenet, said, “Manufacturing productivity is not just about machines and automation; it is equally about how effectively people are managed and deployed. When organisations have thousands of employees working across plants and shifts, even small inefficiencies in workforce management can have a significant operational impact. With Officenet Smart Factory Solutions, we are bringing workforce data and factory processes closer together to improve visibility, reduce manual effort and help organisations make faster, more informed decisions.”

Officenet currently serves Bajaj Auto, LG Electronics, Havells, Amber Enterprises, Radnik Exports, Vishal Megamart with Smart Factory Solutions, the company is expanding its proposition beyond traditional HR technology to the Manufacturing Industry 5.0 landscape.

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AnalogAI has selected the memBrain Synaptic Analog Generative Engine (SAGE) neuromorphic hardware intellectual property (IP) from Silicon Storage Technology (SST®), a subsidiary of Microchip Technology, for its real-world edge AI processors. The analog edge AI processors feature a proprietary hardware-aware algorithm designed to train and simultaneously run inference on AI models in real-world environments.

Analog compute-in-memory for ultra-low-power edge

AnalogAI uses SST’s memBrain SAGE IP to deliver high levels of analog compute-in-memory (aCIM) performance at or below one watt for ultra-low-power edge applications. Leveraging the robust SST memBrain SAGE silicon IP, based on SST SuperFlash®, AnalogAI is developing new capabilities for real-world inference applications such as robots, drones, vehicles and humanoids that adapt to their environment.

Statements from Microchip and AnalogAI

“AnalogAI is pursuing innovative, co-optimized solutions for edge AI inference that let edge devices adapt in real time to sudden changes in the environment,” said Mark Reiten, senior vice president of the Intelligent Compute business unit at Microchip. “As the central inference engine for AnalogAI’s first products, SST memBrain SAGE IP delivers the compute performance needed together with the energy efficiency AnalogAI requires to reach its application goals. We are pleased to welcome AnalogAI as a new licensee of our SST memBrain IP, joining our rapidly expanding ecosystem.”

“AnalogAI selected SST’s memBrain SAGE intellectual property after extensive industry-wide research into the available offerings, and determined that the memBrain SAGE intellectual property allowed us to shorten development times while still achieving the ultra-low power and high performance required in our market segment,” said Jaejun Lee, chief executive officer of AnalogAI. “Analog compute-in-memory is a rapidly emerging field, and at AnalogAI we are innovating new features for edge AI devices that require real-world adaptation.”

Features of SST memBrain SAGE IP

• memBrain Tensor In-Memory Logic Element (TILE)
• memBrain solution with optimized ESF3 bitcell storing up to 8 bpc at nanoampere level
• custom memBrain solution array, decoders and driver circuits
• optimized DACs and ADCs
• summing-bias and high-voltage circuits
• nanoampere-level bitcell control logic
• proprietary memBrain test circuits
• SST memBrain technology documentation and simulation models
• full IP integration service and support

Production processes and technology roadmap

SST’s memBrain SAGE IP has been developed and delivered in 40 nm and 28 nm production processes using production-ready SuperFlash memory. The current technology roadmap includes the development of memBrain SAGE IP at 22 nm. Designed to provide reliable, high-performance, low-power non-volatile storage directly on chip, SuperFlash memory is widely used in applications that require fast access times, high endurance and data retention without the need for external memory components.

Pricing and availability

Customers interested in SST’s memBrain IP solutions and SuperFlash technology can visit the dedicated SST website or contact a regional SST sales executive through the contact page for more details.

Resources

High-resolution images are available through Flickr or editorial contact (images free to publish): Application image.

The post AnalogAI picks SST’s memBrain SAGE IP for its Edge AI processors appeared first on Open Electronics.

Renesas Electronics Corporation has introduced the RL78/G21, a new microcontroller (MCU) in its RL78 family. The company, which holds the leading global market share in 16-bit MCUs, has designed the new series for smart home appliances. The RL78/G21 combines low power consumption with built-in functions for efficient system control, helping manufacturers reduce energy use and product costs. It is designed for applications such as air conditioners, refrigerators, washing machines and microwave ovens.

Renesas has also expanded its RL78/G23 series with new microcontrollers that support more capacitive-touch inputs for advanced user interfaces. The RL78/G21 is designed for energy-efficient system control, while the RL78/G23 combines system control and user-interface functions in a single chip. This gives manufacturers more design options and can help reduce the overall cost of electronic components.

Ensuring Reliability, Security and Flexibility in Smart Appliances

For more than 15 years, the RL78 family has earned the trust of customers worldwide across a broad range of applications. The new RL78/G21 and RL78/G23 strengthen that foundation forward with enhanced security capabilities that help protect against physical threats, such as counterfeiting and cloning, as well as cyber threats, including unauthorized access, information leakage, tampering and spoofing. The RL78/G21’s high electrostatic discharge (ESD) tolerance of ±4 kV HBM contributes to higher reliability throughout manufacturing and assembly, as well as during operation of the end product. The RL78/G21 also adds the UARTA communication interface, an upgrade over the RL78/G13, enabling flexible system expansion such as the addition of sensors. Because the RL78/G21 is pin and function compatible with the existing RL78/G13 and RL78/G23, customers can transition designs seamlessly to the new devices with minimal redesign effort.

Ultra-Low-Power MCU Optimized for System Control

The RL78 family has demonstrated its ultra-low-power capabilities with products achieving top scores in the ULPMark-PeripheralProfile benchmark. Leveraging the advanced low-power technologies developed for the RL78 family, the RL78/G21 achieves an operating current of just 34 μA/MHz, nearly half that of the leading RL78/G13 MCU products. This helps reduce battery capacity, downsize power supply circuits and lower overall system costs. Optimization for system control also gives the device strong price competitiveness in the class of products with 128KB or 256KB of code flash memory. The integration of a high-speed on-chip oscillator (HOCO) with ±1.0% accuracy and 4KB of data flash eliminates the need for an external oscillator and EEPROM, reducing BOM costs.

Scalable Touch HMI Support

As demand for touch input grows with the increasing sophistication of human-machine interfaces (HMIs), Renesas expanded the RL78/G23 lineup with the RL78/G23 (R7F104G), which offers enhanced capacitive-touch sensing. Compared with the existing RL78/G23 (R7F100G), which provides 14 touch channels in the 44-pin version and 16 touch channels in the 48-pin version, the new devices significantly increase the number of touch channels to 24 and 25, respectively. Renesas provides common touch peripheral functionality and the QE for Capacitive Touch tool across the RL78, RX and RA families, enabling scalable HMI development ranging from simple user interfaces to advanced graphics displays.

“The RL78/G21 and RL78/G23 are built on the proven strengths of the RL78 family, delivering significant advances in low-power performance, reliability and security,” said Raji Mukhopadhyay, Business Division Manager, EP Mainstream MCU Business Division at Renesas. “The RL78/G21’s ±4 kV HBM ESD tolerance is a key differentiator. It further strengthens reliability, while its enhanced security capabilities address the growing need for more secure smart appliances.”

Additional Features

• Self-diagnostic functionality enabled by an IEC 60730-compliant self-test library
• Security features including flash read protection, flash shield window, Unique ID and Customer ID
• High ESD tolerance of ±4 kV HBM (Human Body Model) (RL78/G21 only)
• Pin and functional compatibility with the existing RL78/G13 and RL78/G23
• Wide operating voltage range from 1.6V to 5.5V
• Development support through Smart Configurator and the Fast Prototyping Board (FPB)

“Appliance makers are asking for more intelligence, better user experiences and stronger security without increasing cost or energy consumption,” added Mukhopadhyay. “With the RL78/G21’s ultra-low-power performance and enhanced security, alongside the RL78/G23’s expanded touch capabilities, customers can select the right MCU for their system control and HMI requirements and bring more efficient, reliable and secure smart appliances to market faster.”

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Wolfspeed Inc of Durham, NC, USA — which makes silicon carbide (SiC) materials and power semiconductor devices — has announced a multi-year agreement to supply its 1200V silicon carbide devices for the next-generation 800V SiC-based inverter platform of BorgWarner Inc of Auburn Hills, MI, USA (which provides sustainable mobility solutions for the vehicle market) as a strategic partner...

DigiKey, a global distributor of electronic components and automation products, expanded its product portfolio in the third quarter of 2026. The company added more than 27,000 new products to its in-stock inventory, making them available for immediate shipment. It also added over 507,000 products to its website and partnered with 93 new manufacturers to expand its product range.

“DigiKey’s strong inventory pipeline and in-stock availability continue to drive our record-breaking growth in revenue and customer count,” said Mike Slater, vice president of global business development at DigiKey. “Continued investments in our product portfolio, industry-leading website and global distribution center give customers quick access to the latest innovative products essential for accelerating their designs.”

DigiKey aims to keep more products in stock so that engineers, designers, makers and purchasing teams can order small quantities of components for prototypes and testing. This allows them to receive products quickly without placing large factory orders or waiting for long delivery times.

Q3 new manufacturer suppliers include:

• Alif Semiconductor, which provides the next-generation Ensemble family of microcontrollers and fusion processors, combining scalable performance, AI/ML acceleration, advanced security, integrated wireless and flexible processing for a wide range of applications.
• Chase Corporation is a global specialty chemicals company offering protective materials for high-reliability applications. Its HumiSeal  brand has over 60 years of experience providing conformal coating solutions that protect electronics across a wide range of industries.

DigiKey continues to expand its product inventory, helping engineers, designers and makers access the latest electronic components and newly launched products for their projects.

Some of the NPIs added in Q3 2026 include:

• The DFRobot LattePanda Mu Ultra, a compact x86 compute module designed for on-device AI, machine vision, local large language models and other compute-intensive edge applications.
• Same Sky’s anti-vandal switches combine rugged stainless-steel or black alloy construction with IP65/IP67 sealing, offering dependable performance in demanding industrial and outdoor applications.
• Schneider Electric’s TeSys Deca SNAP IN contactors feature tool-free, one-second conductor connections that can accelerate panel assembly by up to 96% while providing secure, vibration-resistant connections.
• Arduino’s VENTUNO Q Edge AI Computer combines high-performance AI processing, real-time control and advanced connectivity on a single platform for robotics and edge AI applications.
• The Sensirion SFA40, which combines high-sensitivity formaldehyde detection and low power consumption to enable next-generation indoor air quality monitoring devices for air purifiers, HVAC systems and portable monitors.
• The Nordic Semiconductor nRF93M1 Smart Modem delivers LTE Cat 1 bis connectivity, Wi-Fi and cellular-based positioning, along with robust security features in a compact, pre-certified module for global IoT applications.
• Amphenol RF’s high-flex RG-58 FAKRA cable assemblies combine flexible, durable construction and reliable RF performance to support automotive and industrial applications exposed to continuous movement and vibration.
• Eaton’s XVH Series supercapacitors combine high-density energy storage, ultra-low ESR and fast charge/discharge performance to support reliable backup power and energy recovery applications.
• SICK’s sensingCam SEC200 industrial code reader, which delivers reliable, cost-effective identification of 1D barcodes and 2D matrix codes, enabling simplified traceability, verification and automation across manufacturing, packaging and logistics applications.
• STMicroelectronics’ VL53L9CX direct Time-of-Flight (dToF) 3D LiDAR module delivers high-resolution depth sensing with up to 2.3K zones, accurate ranging to 9 m and low-power operation for robotics, smart building, AR/VR and industrial sensing applications.

Beyond investing in continuous inventory growth, the company recently announced a $100 million investment over the next 18 months to expand its global distribution centre and scale capacity and automation. The investment reinforces DigiKey’s position as a global leader in electronic component distribution, serving one million customers annually with more than 1.9 million products in stock and ready to ship the same day from the U.S. product distribution centre.

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Microchip Technology is expanding its 10BASE-T1S portfolio with the arrival of the LAN8679 and the LAN8680 10BASE-T1S PMD transceivers, together with the LAN8660X/1X/2X endpoint family with integrated transceivers. Designed to support next-generation zonal architectures, these solutions offer flexible, space-efficient connectivity that extends Ethernet all the way to the edge of the network.

Scalable edge connectivity for automotive and industry

As automotive, industrial and robotic systems evolve toward fully Ethernet-based networks, designers face growing demand for simplified architectures, lower wiring complexity and efficient integration of edge nodes. Microchip’s latest 10BASE-T1S devices address these challenges and are designed to meet the AEC-Q100 and ISO 26262 functional safety standards, building on Microchip’s VelocityDRIVE portfolio with additional multidrop connectivity solutions featuring an optimised interface.

OA3P interface and integrated SBC features

It provides a standardised Open Alliance 3-Pin (OA3P) interface in a compact 8-pin VDFN package, supporting space-constrained edge nodes while reducing pin count and design complexity. The LAN8680 builds on these capabilities by integrating System Basis Chip (SBC) functions, including power management, wake/sleep system control and watchdog supervision. Both devices are designed to improve reliability and safety in demanding environments such as automotive and industrial applications.

The statement from Charlie Forni

“Microchip’s latest 10BASE-T1S portfolio strengthens our commitment to enabling scalable, all-Ethernet network architectures,” said Charlie Forni, corporate vice president of the networking and connectivity business unit at Microchip. “By combining the simplicity of the OA3P interface with integrated endpoint features, these devices give designers the flexibility to build efficient and reliable systems while significantly reducing complexity at the edge.”

LAN8660X/1X/2X endpoints with integrated transceiver

Complementing these devices, the LAN8660X/1X/2X endpoint family integrates a PMD transceiver into a single-chip Remote Control Protocol (RCP) solution. This approach lets designers implement compact, fully integrated edge nodes for applications such as control systems, lighting and audio without the need for external PHY components.

Multidrop topology and lower system cost

Leveraging the 10BASE-T1S multidrop topology, Microchip’s solutions allow multiple nodes—typically eight or more—to share a single bus line. This reduces wiring weight, lowers system cost and eliminates the need for gateways, making it easier to connect sensors and actuators directly at the edge of the network.

Applications and availability

Microchip’s expanded Single Pair Ethernet portfolio targets a wide range of applications, including automotive zonal architecture, industrial automation, robotics and aerospace and defence systems. The products align with industry trends toward consolidated networks and simplified connectivity frameworks, letting designers implement efficient and scalable all-Ethernet architectures. For more information on Microchip’s Single Pair Ethernet solutions, visit the dedicated website.

Pricing and availability

The LAN8679, LAN8680 and LAN8660X/1X/2X are available in limited samples. For more information, contact a Microchip sales representative.

Resources

High-resolution images are available through Flickr or editorial contact (images free for publication).

Application image.

The post Microchip expands its Single Pair Ethernet portfolio with new 10BASE-T1S devices appeared first on Open Electronics.

Emerson has introduced new NI PXI instruments to expand its range of automated testing hardware and software. The new instruments aim to make AI-assisted testing more affordable and accessible, helping engineering teams develop tests faster and simplify product testing across different industries.

The new NI PXIe-4086 digital multimeter and new versions of the NI PXIe-5160 and PXIe-5162 oscilloscopes expand the NI PXI automated testing platform. The platform offers accurate measurements and precise timing and synchronisation when testing multiple signals and systems. It is designed for applications in semiconductor manufacturing, transportation, aerospace, defence and research. Combined with NI software and NI Nigel AI, the platform helps engineers build and automate complex testing systems more quickly while making it easier to adapt them to future requirements.

“Our new, entry-level NI PXI instruments are making NI’s AI-accelerated approach to automated test accessible to more engineering teams,” said David Hall, vice president of NI product marketing with Emerson’s test and measurement business. “By combining the industry’s most powerful platform for automated test with software that accelerates test automation, we’re helping engineers accelerate product development, solve problems faster and spend more time engineering rather than designing their test systems.”

The new instruments and software capabilities enable engineering teams to:

Build and expand test systems with more cost-effective instrument options.

• NI PXIe-4086 DMM: A cost-effective entry point into high accuracy, high-throughput measurements with 6½-digit of resolution and 35 ppm accuracy.
• NI PXIe-5160 and PXIe-5162 oscilloscopes: Up to 1.5 GHz of bandwidth in 2- or 4-channel configurations with 1 GB onboard memory options for high-bandwidth signal capture and analysis.

Move from hands-on measurement troubleshooting to automation with purpose-built test software.

• NI InstrumentStudio: New support for the latest PXI instruments and switches expands no-code configuration, system bring-up and debugging across multi-instrument systems.
• NI Nigel AI: Continued advancements of the test-optimized AI, help engineers accelerate the development and debugging of automated tests.

The new offerings build on Emerson’s earlier expansion of the NI PXI portfolio, extending the range of affordable hardware and connection into NI software available to automated test teams. Together, these additions broaden access to automated test by bringing cost-effective instrumentation, integrated software workflows and AI-assisted productivity to a common platform. Engineering teams can start with the capabilities they need today and scale as product complexity, validation demands and automation requirements grow.

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Ascent Solar Technologies Inc of Thornton, CO, USA — which designs and makes lightweight, flexible copper indium gallium diselenide (CIGS) thin-film photovoltaic (PV) panels that can be integrated into consumer products, off-grid applications and aerospace applications — was co-host of an executive networking event on 20 October in Willow Springs, California, that brought together leaders and innovators from across the commercial space industry to discuss emerging technologies, mission requirements, and opportunities for future collaboration...

AXT Inc of Fremont, CA, USA — which makes gallium arsenide (GaAs), indium phosphide (InP) and germanium (Ge) substrates and raw materials at plants in China — says that its majority-owned China-based wafer manufacturing subsidiary Beijing Tongmei Xtal Technology Co Ltd has entered into definitive agreements for a private equity financing to fund further expansion of its manufacturing capacity for indium phosphide substrates, expansion of its principal business operations, capital expenditures, and general working capital. The financing agreements provide for a private equity investment in Tongmei by certain institutional investors of a minimum of RMB1,912,350,000 (about US$285m) and up to a maximum of RMB3,668,639,053.25 (about US$545m) in ordinary shares of Tongmei...

Particularly in consideration of current (and over-time increasing) semiconductor constraints, this has been a surprisingly busy (albeit pricey) October from a systems-release standpoint.

Nearly two months ago, as is typical for the season, Apple announced new smartphones, watches and earbuds. Several weeks before that, the company had somewhat-typically-for-fall unveiled two new processors and systems containing them. But wait, there’s more. Just two weeks back, and atypically, Apple had rolled out more hardware, this time for the smart home. And this week? Three straight days of even more hardware. Very atypical.

I’ll get to Apple’s most recent news shortly. But it wasn’t the only tech heavyweight to unveil new mobile computing devices—a mix of laptops and tablets—this month.

Microsoft and Nvidia go “Ultra”

Last November, within my yearly “Holiday Shopping Guide for Engineers” (this year’s edition which I’m now reminded I need to begin writing shortly), I suggested (among other things) you consider purchasing, for others and/or yourself, Nvidia’s DGX Spark mini AI workstation.

(it’s the gold-colored device to the right of the laptop, not the laptop itself. Hold that thought).

As background info for today’s discussion, I noted the following back then.

Its application processor, originally referred to as the N1X, is now renamed the GB10. Co-developed by NVIDIA (who contributed the Grace Blackwell GPU subsystem) and MediaTek (who supplied the multi-core CPU cluster and reportedly also handled full SoC integration duties), it was originally intended for—and may eventually still show up in—Arm-based Windows PCs. But repeated development hurdles have (reportedly) delayed the actualization of both SoC and system shipment aspirations, and lingering functional bugs preclude Windows compatibility (therefore explaining the DGX Spark’s Linux O/S foundation).

Those bugs have apparently finally been squashed—or at least sufficiently worked around—because Nvidia and lead mobile systems partner Microsoft publicly released the Surface Laptop Ultra on October 7. The history lesson here is interesting (IMHO, at least) and instructive.

Microsoft has been steadily working on Windows-on-Arm, spanning operating systems, applications suites and hardware to run them on, since June 2012 with the Windows Surface RT, which was powered by the multi-core Arm Cortex-A9-based Nvidia Tegra 3 SoC.

 

From then until now, everything else Arm-related, including my latest Surface Pro 11 “Plus” acquisition (along with several generations of developer-tailored desktop hardware), ran Qualcomm-developed silicon, even if the SoCs were Microsoft-stamped. But Nvidia’s back, baby. And it’ll only cost you $2,599 (baseline, as much as $5,899.99 top-end) to own one. With delivery “later this year” (which, I’m compelled to note, has only two more months left in it as I type this). Gulp.

Two versions of the Nvidia RTX Spark N1X (apparently, in a clarification of the earlier rename mention, both GB10 and N1X are valid monikers, for different system form factors) exist, both with the same NPU core inside:

• 5120-core GPU and 18-core CPU, and
• 6144-core GPU and 20-core CPU

System memory ranges from 24 GB to 128 GBytes in capacity, LPDDR5x DDR unified in all configurations. SSD options start at 512 GBytes (PCIe Gen 4), with 1 and 2 TByte PCIe Gen 5 configurations also offered. And by the way, an RTX Spark-based developer platform, $5,999.99 and up, is also available for pre-order (perhaps a replacement for the canceled Qualcomm one?).

Amazon loves generic Android (again)

Next stop: tablets. I’ve said it before, I’ll say it again today, and I’m unfortunately sure I’ll be saying it more in the future, given where semiconductor building block prices and tariffs are going: when your bill-of-materials costs increase, the best way to “hide” them is to bail on entry-level models and conversely double-down on already-profit-margin-padded high-end product variants. Enter Amazon’s no-longer-Fire, now Alexa-branded, latest-generation tablets.

Plastic cases are gone (except for the kiddie-tailored ones), replaced by thin unibody aluminum chassis, wrapped around higher-quality LCDs, multi-speaker arrays and other integrated goodies. Gone too is access to the Amazon Appstore (which won’t be a surprise to anyone who read my last-October Amazon coverage); Amazon’s back to leveraging the Google Play Store.

More generally, the new tablets run “vanilla” Android instead of the “forked” Fire OS precursor. They come in 8”, 11” and 12” “Pro” flavors, each with multiple storage capacity tiers (along with two DRAM capacity options for the 8” version, interestingly), with prices starting at $299 and ranging up to $679.99, not including cases or the high-end model’s optional pen and keyboard accessories.

Speaking of October Amazon coverage, by the way, the company chose today, at the tail-end of competitor Apple’s three-day announcement cadence, to roll out this year’s collection of Echo speakers (one even complete with a camera? SMH), smart displays and such. I won’t be covering them in this particular piece, so to tide you over until I have time to discuss them, I’ll hand you over to Engadget (or any of the other usual suspects, for that matter) for coverage purposes.

Touch me. Finally.

And speaking of unwise chronological congruity, what did Apple roll out this week? Monday brought a new generation of the iPad mini (the prior generation of which, which I own, was dubbed “cute” by my wife just the other day), no longer with a trailing-edge SoC versus its larger siblings (now with the A20 Pro), and with a slightly larger display (8.5” in diameter this time) that, even more impactfully, switches from LCD to OLED. The front camera is conveniently relocated to the landscape edge, too. And yes, all this goodness is accompanied by price increases. The entry-level 128 GByte Wi-Fi-only variant of my 2024 model was originally $499 but got bumped by Apple up to $599 in June of this year, while this year’s edition is $699 and up. Yup.

 

Yesterday? Thanks for asking. The 14” (but not 16”, interestingly…the same thing happened last year, so I’m guessing the larger one’s “Pro” and “Max” only from here on out) entry-level version of the MacBook Pro now runs the M6 SoC, versus last year’s M5, while the 24” iMac makes a two-gen (and associated two-year between-updates) jump from the M4 to the M6.

Yep, that’s basically it; form factors, etc. remain unchanged. Yawn. Even the MacBook Pro stock image shown above, from Apple’s press release, was boring. And if I was a betting man, I’d lay my odds on the earlier-leaked theory that the next SoC iterations of the higher-end “Pro” and “Max” MacBook Pro variants will await the M7 Apple Silicon generation.

Apple instead “kept its powder dry” for today’s unveiling of its first touchscreen-augmented (and broader PROLED XDR-based) computers, MacBook Pro laptops in both 14” and 16” display and both M5 Pro and Max SoC options.

Now that’s a snazzy stock image…err…video, right? Unsurprisingly, there’s a whole lot of underlying software evolution of both MacOS and key apps such as the Safari browser (beta-examination insights into the latter which were discovered two weeks back) as enablers of the enhanced hardware. And equally unsurprisingly, those hardware enhancements come with an associated price tag increase. Depending on size and configuration, you could pay anywhere from $2,899 to…hold your hat…$14,549 for the privilege of a display that responds to your touch.

You may now pick yourselves up from the floor and climb back in your seats. Although I’m sure Apple’s done no shortage of advance market research, including conversations with potential customers under NDA, I’m admittedly somewhat skeptical about the prospects for long-term high volume success here. I say this although I have absolutely no doubt in the first-generation fiscal-and-other enthusiasm of technology early adopters, and even though I acknowledge (in a nod to my earlier Microsoft Surface case study comments) that Apple’s a late adopter here as compared to Windows-powered touchscreen counterparts (along with its own iPad, for that matter).

Speaking of case studies, let’s take me as an example. Including my current x86-based Surface Pro 7+ (and spare, along with two Pro 8+ successors in the queue) and earlier mentioned Arm-based Pro 11 models, I’ve to date purchased nine (six to-date actively used) touchscreen Windows laptops, if my recollection is correct. But I’ve barely used their touchscreens at all, far from for any meaningful period of time.

Partly, speaking of fiscal blessings, it’s because I’ve in-parallel owned multiple generations of iPads. And to that point, I’m most enthused about the concept when it’s applied to hybrid systems like the Surface Pro that can operate as both a tablet and a laptop, depending on if a physical keyboard is connected at the time. But that’s not the form factor of these new MacBook Pros. And I’d wager that anyone who’ll buy one is capable of buying an iPad (or few), too.

Thoughts, readers? Let me know in the comments!

—Brian Dipert is the associate editor, as well as a contributing editor, at EDN.

Related Content

• Apple’s processor cadence: A pending stutter-step for improved long-term edge inference?
• The Microsoft-reminiscent iPhone Duo: How much customer holding-and-folding is necessary to keep Apple from folding on the experiment?
• Apple heads Home: Distributed identity validation, and how much does Matter matter?
• Amazon and Google: Can you AI-upgrade the smart home while being frugal?
• The Microsoft Surface Pro 5 succession: Selections, motivations, and initial impressions

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TetraMem has completed tapeout of the MLX300, a 12-nm analog in-memory computing (A-IMC) SoC based on multi-level RRAM technology. The chip was developed using Synopsys EDA software delivered through Synopsys Cloud FlexEDA, extending multi-level RRAM-based AI chip development to advanced FinFET nodes.

The MLX300 tapeout follows TetraMem’s MLX200/MLX200M multi-level RRAM A-IMC SoCs, which completed full-mask tapeout in 2026 on a commercial 22-nm process.

TetraMem’s architecture enables scalable AI accelerator development while improving performance per watt and reducing data movement. The MLX300 uses this architecture in a single-chip accelerator for audio, vision, and smaller language models. It supports up to 64 million INT4 parameters on-chip without external DRAM for model-weight storage. TetraMem says the SoC targets energy efficiency exceeding 50 TOPS/W.

TetraMem

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ST has launched an automotive sensor platform that combines multi-axis accelerometers and angular-rate sensors in a single package. The platform is designed to extend active and passive safety systems and driver-assistance features across vehicle categories, from premium to mass-market. Applications include crash protection, rollover detection, airbag deployment, vehicle stability control, and radar beam stabilization.

The sensors feature internal diagnostics and support SafeSPI, a serial peripheral interface for automotive safety. ST’s first four offerings following its integration of NXP’s sensors division are:

• NCS1012BAEP: z-axis (yaw) angular-rate sensor and xy low-g accelerometer
• NCS1012CAEP: x-axis (roll) angular-rate sensor and yz low-g accelerometer
• NCS1012EAEP: x-axis (roll) angular-rate sensor and xy medium-g accelerometer
• NCS10135AEP: z-axis (yaw) angular-rate sensor and xyz low-g accelerometer

Angular-rate sensors offer full-scale ranges of ±125 dps, ±250 dps, or ±350 dps, with integrated low-pass filtering (12.5–400-Hz cutoff options) and operation from −40°C to +105°C. Low-g accelerometers cover ±1.50 g to ±34 g, while medium-g versions cover ±15.5 g to ±150 g and feature an independent signal chain to minimize noise. Both acceleration sensor types feature low offset and drift over the automotive temperature range and integrated low-pass filtering.

The combo sensors are now in production in 24-pin QFN packages with wettable flanks.

STMicroelectronics

The post Motion sensor combo ICs target vehicle dynamics appeared first on EDN.

A programmable Hall switch from Melexis, the MLX92342, simplifies remote position detection in automotive systems such as seatbelt buckles. The 2-wire, PCB-less sensor IC provides a valid output and generates a diagnostic safety signal in less than 100 µs. This signal indicates a fault condition, allowing the ECU to distinguish a sensor malfunction from a valid buckle-state reading.

With integrated on-chip diagnostics, the MLX92342 is certified as an ISO 26262 ASIL B SEooC and qualified to AEC-Q100. ESD protection is rated at 8-kV HBM, 15-kV system-level contact discharge, and 25-kV system-level indirect discharge. The device supports magnetic latch, unipolar switch, and omnipolar switch configurations, with a magnetic operating range of 0.5 mT to 200 mT. 

Beyond seatbelt buckle detection, the MLX92342 can be used in window lifters, brake fluid level sensors, active air skirts, locks, valves, and actuators. It is a suitable option for applications using mechanical microswitches, reed switches, or less advanced magnetic switches, adding programmability, diagnostics, and contactless operation.

The MLX92342 is available now. A locked, pre-programmed version, the MLX92341, is also available.

MLX92342 product page 

Melexis

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Innodisk offers the GMSL2 camera starter kit, which bundles four 3-Mpixel cameras, a MIPI CSI-2-to-GMSL2 capture card, and accessories. The kit provides a ready-to-use platform for developing and validating multi-camera systems for edge AI vision applications.

GMSL2 is a high-speed serial link for real-time video transmission, supporting forward-channel data rates of up to 6 Gbps. The starter kit includes camera source code for the NVIDIA Jetson Orin Nano Super Developer Kit, the platform used to run the system. The pre-integrated hardware and software reduce the need for component sourcing, complex system-level integration, driver debugging, and tuning.

In addition to the four fixed-focus GMSL2 camera modules and capture card, the kit comes with four 1-meter GMSL2 FAKRA cables, a power adapter, and power cords.  Target edge AI applications include blind spot detection and ADAS for heavy-duty vehicles, as well as object recognition and environmental perception for humanoid robots and autonomous mobile robots.

After initial validation with the starter kit, Innodisk offers customization services ranging from hardware fine-tuning to application deployment in edge environments.

GMSL2 camera starter kit (EKIT-B14-001)

Innodisk

The post Camera kit simplifies multi-camera AI development appeared first on EDN.

The Renesas RX74M and RX74N 32-bit MCUs are the first in the RX family to use a 22-nm process and incorporate embedded MRAM. Based on a 600-MHz RXv3e core, both of these industrial devices achieve more than twice the performance of their 240-MHz predecessors, the RX72M and RX72N.

Each MCU features 1 MB of code MRAM, 256 KB of zero-wait-state TCM (tightly coupled memory) RAM, and 1.5 MB of SRAM for real-time processing. Unlike embedded flash, MRAM can be written without a prior erase operation, allowing faster code and data updates and reducing programming time.

The RX74M is designed for industrial automation equipment, including AC drives, industrial robots, and PLCs. The RX74N targets smart meters, power conditioners, and HVAC systems. Both integrate Gigabit Ethernet and CAN FD, while the RX74M adds a TSN-capable Ethernet switch and an EtherCAT slave controller for industrial networking.

The RX74M and RX74N are available now, along with corresponding evaluation boards.

RX74M product page 

RX74N product page 

Renesas Electronics 

The post Industrial MCUs pair 600-MHz cores with MRAM appeared first on EDN.

Designing compact and efficient power factor correction (PFC) stages for low-power to mid-power applications often requires operating in critical conduction mode (CrM) or discontinuous conduction mode (DCM). These modes offer improved efficiency and simplified control at light loads, but require careful design to ensure correct valley detection and mode transitions across the entire input range and load range.

CrM/DCM boost PFC topology is a highly recommended solution for applications up to 200 W. This topology remains a compelling choice for the 200 W to 400 W range, particularly when cost effectiveness and light-load performance are primary design constraints. However, it’s important to select the most suitable mode depending on the power level and system constraints.

Figure 1 The PFC boost stage operates in CrM under worst-case conditions and falls back to DCM at lighter loads. Source: Monolithic Power Systems

This article presents a step-by-step methodology for designing a boost PFC stage that operates in CrM under worst-case conditions and falls back to discontinuous conduction mode at lighter loads, as shown in Figure 1.

The inductor is selected to achieve critical conduction at the minimum input voltage (VIN) and a full load, ensuring proper zero-current switching. Key aspects such as variable frequency behavior, inductance, and peak current calculation are addressed in this article through a formula-driven approach.

Step 1: Define the operating parameters

An effective power design should include a clear set of specifications and consider the worst-case scenario. The operating parameters for a universal input PFC converter are the minimum AC RMS input voltage and maximum output power (POUT_MAX).

Table 1 shows the power converter specifications for a practical example, which will be applied to the following calculations in this article.

Table 1 These power converter specifications are applied to calculations in this article. Source: Monolithic Power Systems

Based on Table 1, the minimum switching frequency (fSW) is at the peak of the low AC line and at POUT_MAX. Figure 2 shows that the inductor current dependent on time (iL (t)) follows the AC input voltage and its average value (IL_AVG) in CrM.

Figure 2 The inductor current dependent on time follows the AC input voltage and its average value in CrM. Source: Monolithic Power Systems

The worst-case conditions can be determined using the power converter specifications from Table 1.

The maximum input power (PIN_MAX) can be calculated with Equation (1):

If POUT_MAX is 150 W and η is 0.94 under the worst-case conditions, then PIN_MAX is 159.57 W.

The minimum peak AC voltage (VIN_PK_MIN) can be calculated with Equation (2):

If VAC_MIN is 85 V, then VIN_PK_MIN is 120.21 V.

Step 2: Calculate the inductance

The single most important component in this design is the boost inductor (L). Figure 3 shows an example of a power inductor for the PFC boost stage.

Figure 3 Here is an example of a power inductor for the PFC boost stage. Source: Monolithic Power Systems

The boost inductance determines the energy storage per cycle and mode. The converter must be in CrM at the minimum AC input voltage under full loads. This ensures that the inductor has sufficient energy storage capability for all other operating conditions.

The required inductance (L) for CrM can be calculated with Equation (3):

Where VIN_PK_MIN is the peak input voltage at the minimum AC input voltage, VOUT is the DC output voltage, PIN_MAX is the input power at full load, and fSW_MIN is the target minimum switching frequency.

The inductance based on Equation (3) and the power converter specifications provided in Table 1 is 450 µH, as shown below.

At the highest current demand (low line peak at full loads), a 450-µH inductor ensures that the current returns to 0 A by the end of a 70-kHz cycle. For any other current demand levels, the cycle completes faster, causing the part to operate in discontinuous conduction mode.

Step 3: Calculate the maximum component stress

With a fixed inductance, the absolute maximum peak current tolerated by the MOSFET and diode at the peak of the low AC line voltage can be calculated. In CrM, the inductor current waveform is a triangle starting from 0 A, where the peak current (ISW_PK) is exactly twice the average input current. The average current at the peak of the sinusoid (IIN_PK_AVG) can be calculated with Equation (4):

The absolute peak switch current (ISW_PK_MAX) can be calculated with Equation (5):

The calculation for the practical example is shown below.

This means that the MOSFET (Q1) and boost diode (D1) must be rated to handle a repetitive peak current of at least 5.31 A. The RMS current rating is lower, but this peak value determines the component’s survivability.

Step 4: Analyze variable frequency operation

A defining characteristic of a CrM/DCM PFC is its variable switching frequency (fSW), which changes dynamically throughout each half-cycle of the AC line and is the lowest at the peak of the AC voltage (where the most power is processed) and highest near the zero-crossings.

The instantaneous fsw (t) can be calculated with Equation (6):

Where vin (t) is the instantaneous input voltage, and p (t) is the instantaneous input power.

vin (t) can be calculated with Equation (7):

p (t) can be calculated with Equation (8):

Figure 4 shows fSW across a half-line cycle, which has a characteristic U shape.

Figure 4 Switching frequency (fSW) across a half-line cycle has a characteristic U shape. Source: Monolithic Power Systems

The designed minimum 70 kHz switching frequency (fSW_MIN) is lowest at the peak of the sinusoid, while the frequency rises dramatically near the zero-crossing. The controller IC must have a maximum frequency clamp to prevent excessively high-frequency operation, which would lead to high switching losses. A typical clamp is about 250 kHz.

Step 5: Understanding the control loop and zero-current detection (ZCD)

Compared to a fixed-frequency CCM design, a CrM/DCM PFC uses on-time control and zero-current detection (ZCD). The voltage loop sets the on-time command to regulate the output voltage (VOUT), while the ZCD signal and the controller’s internal timing logic determine when the next switching cycle can begin. As a result, fSW depends on the on time (tON), the inductor demagnetization time, and any additional delay introduced by the controller.

On-time control

The main control loop adjusts the MOSFET’s tON. A longer tON results in a higher peak current and more power delivered to the output. The controller’s error amplifier (EA) compares VOUT to a reference voltage and sets the required tON to keep VOUT in regulation. The tON behavior across the AC line cycle depends on the control method implemented between constant-on-time (COT) control and variable-on-time (VOT) control.

• Constant-on-time (COT): In this standard approach, the controller maintains a fixed tON throughout a single mains half-cycle. The peak current (IPK) can be calculated with Equation (9).

The current naturally follows the sinusoidal shape of VIN, providing inherent power factor correction. The voltage loop updates this constant value slowly across several cycles to regulate the output load.

• Variable-on-time (VOT): To further minimize total harmonic distortion (THD), advanced controllers may modulate tON within the half-cycle. For example, intentionally extending tON near the VIN zero-crossings can compensate for dead zones and crossover distortion, resulting in a purer sinusoidal input current.

Zero-current detection (ZCD)

Rather than use a fixed-frequency clock to start a new cycle, the controller waits for a signal from the ZCD circuit, indicating that the inductor current (IL) has dropped to 0 A. An auxiliary winding is added to the boost inductor. When IL decays and reaches 0 A, the voltage on the main winding collapses, inducing a voltage swing in the auxiliary winding. This voltage swing is detected by the ZCD pin on the PFC controller, which immediately initiates the next MOSFET turn-on event.

Final design

By calculating the required boost inductance and current on the semiconductor devices, a PFC boost converter design can be completed using the MP44020, a multi-mode CrM/DCM PFC controller. Table 2 shows the key design results for a 150-W application.

Table 2 Design results are shown for a 150-W application. Source: Monolithic Power Systems

The MP44020 CrM/DCM controller provides simple and high-performance active PFC using minimal external components. To enhance system performance across all load conditions, fSW is reduced at light loads via dead time (DT) extension technology, which improves efficiency and helps achieve very low standby power consumption. MP44020 also achieves lower THD by implementing VOT control, a significant advantage over conventional COT methods.

Protections include over-voltage protection (OVP), over-current limit (OCL), brown-in (BI) and brown-out (BO), VCC voltage (VCC), under-voltage lockout (UVLO), and over-temperature protection (OTP).

Due to MP44020’s high integration, the PFC stage requires only a few external components to function effectively. Figure 5 shows the PFC boost converter schematic using the MP44020 CrM/DCM controller.

Figure 5 The PFC boost converter using the MP44020 requires only a few external components to function effectively. Source: Monolithic Power Systems

Adhere to CrM design principles

Implementing an active PFC boost converter is a critical first stage for modern AC/DC power supplies. This ensures compliance with harmonic current standards and maximizes power quality. In particular, CrM topology offers a cost-effective solution for applications up to 400 W.

By adhering to the design principles for CrM, such as selecting the appropriate boost inductor and managing the variable fSW, engineers can design efficient and reliable PFC circuits. Moreover, a modern controller significantly simplifies this task. Its variable-on-time (VOT) control scheme ensures low THD in addition to integrated protections and efficiency-boosting features for light-load conditions that achieve a robust and high-performance design.

Rafael Collado is a design engineering supervisor at Monolithic Power Systems (MPS).

Related Content

• Power Factor Correction (PFC) Modules
• Back to Basics: Power Factor Correction
• How to design a high-boost-ratio boost converter
• Advantages of interleaved boost converters for PFC
• Feasibility and Accuracy Analysis of Input Power Estimation for Boost PFC Converters with Additional Sensors

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