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Microchip Technology has expanded its PolarFire FPGA–based smart embedded video ecosystem to enable low-power, high-bandwidth video connectivity. The offering consists of integrated development stacks that combine hardware evaluation kits, development tools, IP cores, and reference designs to deliver complete video pipelines for medical, industrial, and robotic vision applications. The latest additions include Serial Digital Interface (SDI) receive and transmit IP cores and a quad CoaXPress (CXP) bridge kit.

The ecosystem supports SMPTE-compliant SDI video transport at 1.5G, 3G, 6G, and 12G, along with HDMI-to-SDI and SDI-to-HDMI bridging for 4K and 8K video formats. PolarFire FPGAs enable direct SLVS-EC (up to 5 Gbps per lane) and CoaXPress 2.0 (up to 12.5 Gbps per lane) bridging without third-party IP. The nonvolatile, low-power architecture supports compact, fanless system designs with integrated hardware-based security features.

Native support for Sony SLVS-EC sensors provides an upgrade path for designs impacted by component discontinuations. Development is supported through Microchip’s Libero Design Suite and SmartHLS tools to simplify design workflows and reduce development time.

The following links provide additional information on PolarFire smart embedded vision, the CoaXPress bridge kit, and FPGA solution stacks.

Microchip Technology 

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Infineon’s EZ-USB FX2G3 USB 2.0 peripheral controllers provide DMA data transfers from LVCMOS inputs to USB outputs at speeds of up to 480 Mbps. Designed for USB Hi-Speed host systems, the devices also support Full-Speed (12 Mbps) and Low-Speed (1.5 Mbps) operation.

Built on the company’s MXS40-LP platform, EZ-USB FX2G3 controllers integrate up to six serial communication blocks (SCBs), a crypto accelerator supporting AES, DES, SHA, and RSA algorithms for enhanced security, and a high-bandwidth data subsystem with up to 1024 KB of SRAM for USB data buffering. Additional on-chip memory includes up to 512 KB of flash, 128 KB of SRAM, and 128 KB of ROM.

The family includes four variants, ranging from basic to advanced, all featuring a 100-MHz Arm Cortex-M0+ CPU, while the top-end device adds a 150-MHz Cortex-M4F. The peripheral I/O subsystem accommodates QSPI configurable in single, dual, quad, dual-quad, and octal modes. SCBs can be configured as I2C, UART, or SPI interfaces. The devices provide up to 32 configurable USB endpoints, making them suitable for a wide range of consumer, industrial, and healthcare applications.

EZ-USB FX2G3 controllers are now available in 104-pin, 8×8-mm LGA packages.

EZ-USB FX2G3 product page

Infineon Technologies  

The post Controllers accelerate USB 2.0 throughput appeared first on EDN.

Diodes’ API772x RobustISO series of dual-channel digital isolators protects sensitive components in high-voltage systems. The devices provide reliable, robust isolation for digital control and communication signals in industrial automation, power systems, and data center power supplies.

Comprising six variants, the API772x series meets reinforced and basic isolation requirements across various standards, including VDE, UL, and CQC. The parts have a 5-kVRMS isolation rating for 1 minute per UL 1577 and an 8-kVPK rating per DIN EN IEC 60747-17 (VDE 0884-17). Maximum surge isolation voltage is 12.8 kVPK. According to Diodes’ isolation reliability calculations, the devices achieve a predicted operational lifetime exceeding 40 years, based on a capacitive isolation barrier more than 25 µm thick.

RobustISO digital isolators support a range of transmission protocols at data rates up to 100 Mbps. They feature a minimum common-mode transient immunity of 150 kV/µs, ensuring reliable signal transmission in noisy environments. Operating from a 2.5-V to 5.5-V supply, the devices typically draw 2.1 mA per channel at 100 Mbps. The series offers flexible digital channel-direction configurations and default output levels to accommodate diverse design requirements.

Prices for the API772x devices start at $0.46 each in lots of 1000 units.

RobustISO API772x product page

Diodes

The post Digital isolators enhance signal integrity appeared first on EDN.

A 100-V, 200-A MOSFET from Rohm, the RS7P200BM achieves a wide safe operating area (SOA) in a compact DFN5060-8S (5×6-mm) package. The device safely handles inrush current and overload conditions, ensuring stable operation in hot-swap circuits for AI servers using 48-V power supplies.

The RS7P200BM features RDS(on) of 4.0 mΩ (VGS = 10 V, Ta = 25 °C) while maintaining a wide SOA—7.5 A for a 10‑ms pulse width and 25 A for 1 ms at VDS = 48 V. This combination of low on-resistance and wide SOA, typically a trade-off, helps suppress heat generation. As a result, server power supply efficiency improves, while cooling requirements and overall electricity costs are reduced.

Housed in a DFN5060-8S package, the RS7P200BM enables higher-density mounting than the previous DFN8080-8S design. It is now available in production quantities through online distributors including DigiKey and Mouser.

RS7P200BM product page 

Rohm Semiconductor 

The post MOSFET ensures reliable AI server power appeared first on EDN.

The Tronics AXO315T1 MEMS accelerometer from TDK is designed for oil and gas downhole navigation in extreme environments. It features a ±14‑g input range and a 24‑bit digital SPI interface for measurement-while-drilling (MWD) applications exposed to temperatures up to 175°C.

Powered by a unique closed-loop architecture, this single-axis device achieves a tenfold improvement in vibration rejection compared with conventional open-loop MEMS accelerometers. It offers vibration rejection of 20 µg/g², noise density of 10 µg/√Hz, and a bias residual error of 1.7 mg over a temperature range of –30 °C to +175 °C.

The AXO315T1 provides a cost-effective, digital, and low-SWaP alternative to quartz accelerometers for inclination measurement in directional drilling tools. It is rated for more than 1000 hours of operation at 175°C and is housed in a hermetically sealed, ceramic surface-mount package.

AXO315T1 sensors and evaluation boards are available for sampling and customer trials.

AXO315T1 product page

TDK Tronics 

The post Sensor drives accurate downhole drilling appeared first on EDN.

How does a wiggling groove on a rotating record transform into two-channel sonic excellence? It all starts with the turntable cartridge, mated to one of several possible needle types.

Mid-last year, I confessed that I’d headed back down the analog “vinyl” record rabbit hole after several decades of sole dedication to various digital audio media sources (physical, download and streamed). All three turntables now in my possession employ moving magnet cartridge technology; here’s what I wrote back in July in comparing it against the moving coil alternative:

Two main cartridge options exist: moving magnet and higher-end moving coil. They work similarly, at least in concept: in conjunction with the paired stylus, they transform physical info encoded onto a record via groove variations into electrical signals for eventual reproduction over headphones or a set of speakers. Differences between the two types reflect construction sequence variance of the cartridge’s two primary subsystems—the magnets and coils—and are reflected (additionally influenced by other factors such as cantilever constituent material and design) not only in perceived output quality but also in other cartridge characteristics such as output signal strength and ruggedness.

Miny-but-mighty magnets

And here’s more on moving magnet cartridges from Audio-Technica’s website:

Audio-Technica brand moving magnet-type cartridges carry a pair of small, permanent magnets on their stylus assembly’s cantilever. The cantilever is the tiny suspended “arm” that extends at an angle away from the cartridge body. The cantilever holds the diamond tip that traces the record groove on one end and transfers the vibrations from the tip to the other end where the magnets are located. These tiny magnets are positioned between two sets of fixed coils of wire located inside the cartridge body via pole pieces that extend outward from the coils. This arrangement forms the electromagnetic generator.

The magnets are the heaviest part of the moving assembly, but by mounting the magnets near the fulcrum, or pivot point, of the assembly the amount of mass the stylus is required to move is minimized, allowing it to respond quickly and accurately to the motion created by the record groove. In addition to enhancing response, the low effective tip mass reduces the force applied to the delicate record groove, reducing the possibility of groove wall wear and damage. The moving magnet-type cartridge produces moderate to high output levels, works easily into standard phono inputs on a stereo amplifier or receiver and has a user-replaceable stylus assembly. These cartridges have a robust design, making them an excellent choice for demanding applications such as live DJ, radio broadcasts and archiving.

The associated photo is unfortunately low-res and otherwise blurry:

Here’s a larger, clearer one, which I’d found within a tutorial published by retailer Crutchfield:

Inexpensively assuaging curiosity

Ever since I started dabbling with vinyl again, I’d been curious to take a moving magnet cartridge apart and see what was inside. I got my chance when I found a brand new one, complete with a conical stylus, on sale for $18.04 on eBay. It’s the AT3600L, the standalone version of the cartridge that comes pre-integrated with my Audio-Technica AT-LP60XBT turntable’s tonearm:

Here are some “stock” images of the AT3600L mated to the standard ATN3600LC conical stylus (with the protective plastic sleeve still over the needle):

This next set of shots accompanied the eBay post which had caught my eye (and wallet):

And, last but not least, here are some snaps of our dissection patient, first bagged as initially received:

then unbagged but still encased, and as usual (as well as with photos that follow) accompanied by a 0.75″ (19.1 mm) diameter U.S. penny for size comparison purposes:

along with mounting hardware at the bottom:

and finally, free from plastic captivity:

Conical closups and elliptical unpredictability

Next, let’s pop off the stylus and take a gander at its conical needle tip:

along with the cantilever and pivot assembly:

If you’ve already read my July coverage, you know that I’d also picked up an easily swappable:

elliptical stylus, the Pfanstiehl 4211-DE, which promised enhanced sonic quality:

but ended up being notably less tolerant than its conical sibling of any groove defects. Some of this functional variance, I noted back in July, is inherent to the needles’ structural deviations:

Because conical styli only ride partway down in the record groove, they supposedly don’t capture all the available fidelity potential with pristine records. But that same characteristic turns out to be a good thing with non-pristine records, for which all manner of gunk has accumulated over time in the bottom of the groove. By riding above the dross, the conical needle head doesn’t suffer from its deleterious effects.

But, as it turns out, the Pfanstiehl 4211-DE itself was also partly to “blame”. It reportedly works best with turntables based on the standalone AT3600L cartridge, whose tracking force and antiskating settings are both user-adjustable and lighter than those needed (non-adjustable, as well) with the fully integrated AT-LP60XBT turntable.

I resold the barely used Pfanstiehl 4211-DE on eBay and went with Audio-Technica’s (modestly) more pricey ATN3600LE elliptical stylus instead, which explicitly documented its compatibility with the AT-LP60 turntable series and indeed worked notably better with my setup:

Back to the ATN3600LC conical stylus. Two interior views showcase the magnets called out in the earlier concept image:

And here’s where they mate with the cartridge itself (with associated coils presumably inside, to be seen shortly):

Cartridge dissection

Next, let’s remove the screw that holds the top black plastic mounting assembly in place:

One more look at the connections at the back, with markings now visible:

And now, let’s peel away the metal casing, focusing attention on the top-side seam:

With that, the insides come right out:

That was a fun and informative, not to mention inexpensive, project that satisfied my curiosity. I hope it did the same for you. Sounds off with your thoughts in the comments, please!

—Brian Dipert is the Principal at Sierra Media and a former technical editor at EDN Magazine, where he still regularly contributes as a freelancer.

Related Content

• Hardware alterations: Unintended, apparent advantageous adaptations
• Mega-cool USB-based turntable
• Assessing vinyl’s resurrection: Differentiation, optimization, and demand maximization

The post Peeking inside a moving magnet phono cartridge and stylii appeared first on EDN.

The post Microchip Introduces 600V Gate Driver Family for High-Voltage Power Management Applications appeared first on ELE Times.

⛩️ Запрошуємо на відкритий турнір Кубка Посла Японії з шьоґі 2026! kpi чт, 01/22/2026 - 11:36

У КПІ відбувся фінал V Всеукраїнського інженерного хакатону SmaRTF kpi чт, 01/22/2026 - 10:24

As India approaches Union Budget 2026–27, multiple industrial sectors—from power and automation to digital infrastructure and electric mobility—find themselves at a critical inflexion point. With the country balancing rapid industrialisation alongside sustainability and energy-transition goals, industry leaders are calling for continued capital expenditure, targeted incentives, and policy stability to strengthen infrastructure depth and global competitiveness.

At the core of these recommendations is the need to reinforce India’s power and grid ecosystem. According to Meenu Singhal, Regional Managing Director, Socomec Group, Greater India, sustained capex allocation, grid modernisation, and deeper indigenisation of critical power equipment will be essential to support rising industrial and digital demand. Industry stakeholders are urging the government to prioritise scalable manufacturing clusters, digitally enabled grid infrastructure, and structural reforms that improve reliability and execution efficiency.

Strategic schemes such as capex support mechanisms, fiscal incentives for local manufacturing, and policies favouring large-scale infrastructure implementation are seen as vital to closing capability gaps across transmission and distribution networks. Equally important, experts stress, is policy consistency and an enabling tax framework that continues to attract both domestic and global capital into the power sector, reinforcing India’s long-term vision of energy security and sustainable growth.

Automation as a Manufacturing Multiplier

Beyond core infrastructure, industrial automation has emerged as a key lever for enhancing India’s manufacturing competitiveness as the economy advances towards the $5-trillion milestone. Sanjeev Srivastava, Business Head – Industrial Automation SBP at Delta Electronics India, highlights that smart factories, AI-driven automation, and closer human–machine collaboration will define the next phase of industrial transformation.

Industry players believe that stronger Budget support in the form of smart manufacturing incentives, R&D-linked tax benefits, and skill-development programmes can significantly accelerate the adoption of next-generation automation technologies. Such measures would help manufacturers improve productivity, reduce operating costs, and strengthen India’s position on the global manufacturing and automation curve.

Also read industry’s recommendations on the Union Budget 2026 at: PCB Duty Cuts to Manufacturing Zones: Top Industry Recommendations for Budget 2026

Digital Infrastructure and Data Centres

As India moves deeper into the 5G, cloud, and AI era, mission-critical digital infrastructure is increasingly being viewed as the backbone of every industry. Pankaj Singh, Head – Data Centre & Telecom Business Solutions at Delta Electronics India, notes that the upcoming Budget presents an opportunity to prioritise energy-efficient and resilient data-centre ecosystems.

Industry recommendations include stronger incentives for modular and containerised data-centre deployments to enable faster rollout of scalable core and edge facilities. There is also a growing emphasis on supporting advanced cooling technologies—such as liquid-to-liquid and liquid-to-air coolant distribution systems—to manage the high thermal loads associated with AI-driven workloads. When complemented with sustainability-linked benefits and Make-in-India incentives for locally manufactured power, cooling, and automation equipment, these measures could encourage OEMs to invest with greater confidence in building a future-ready, low-carbon digital backbone.

Strengthening the EV Manufacturing Base

Meanwhile, India’s electric mobility ecosystem is entering a decisive phase, where long-term resilience and supply-chain stability are becoming as critical as adoption numbers. Bhaktha Keshavachar, Co-Founder & CEO of Chara Technologies, points out that while policy efforts have successfully focused on vehicle adoption and battery localisation, recent global disruptions have exposed vulnerabilities stemming from India’s dependence on imported rare-earth magnet motors.

As Budget 2026 approaches, industry voices are calling for formal recognition and fiscal support for magnet-free motor technologies within existing incentive frameworks. These solutions offer predictable costs, reduced supply-chain risk, and the development of indigenous intellectual property—particularly for high-volume segments such as two-wheelers, three-wheelers, and commercial fleets.

Targeted incentives for rare-earth-free motor manufacturing, stakeholders argue, would not only de-risk India’s EV ambitions but also position the country as a global hub for affordable, resilient, and export-ready EV powertrain solutions.

The Road Ahead

Taken together, these pre-Budget recommendations underline a shared industry priority: building resilient, scalable, and future-ready industrial ecosystems through focused policy support. Whether in power infrastructure, automation, digital systems, or electric mobility, Budget 2026 is widely seen as a pivotal opportunity to reinforce India’s transition towards sustainable growth, technological leadership, and global manufacturing competitiveness.

The post From Power Grids to EV Motors: Industry Flags Key Budget 2026 Priorities for India’s Next Growth Phase appeared first on ELE Times.

On the bench is a Behringer EP2500 pro audio amplifier. It's having a blown output stage and a shorted rectifier diagnosed and repaired. In play is a TTI signal generator and a Tek 468 scope, as well as a DIY dim bulb tester. I've been slowly acquiring all this gear over the past few years. Recently got hold of a proper electronics work bench with shelf a I've for the instruments. This has made life so much easier with all of the extra space it's freed up. It's great to be using all this stuff for real work, not just playing around! submitted by /u/pspkiller91 [link] [comments]

At SPIE Photonics West 2026 in San Francisco, CA, USA (20–22 January), Polar Light Technologies AB — which stems from research by founder professor Per-Olof Holtz and his team at Linköping University (with support from Sweden’s innovation agency Vinnova) — has announced that it has produced its first series of nano-scale LEDs. The firm says that this illustrates the flexibility of its patented pyramidal architecture, developed without requiring the traditional etching process...

Polar Light Technologies AB — which stems from research by founder professor Per-Olof Holtz and his team at Linköping University (with support from Sweden’s innovation agency Vinnova) — has closed a €5m+ funding round led by J2L Holding AB, with participation from STOAF, Almi Invest and Butterfly Ventures . The additional funds will advance the rollout of Polar Light’s initial products, all based on its unique micro-LED architecture. This uses pyramidal structures grown without etching, enabling full RGB on a single epiwafer...

Here are some of the PCBs I've made myself for an 8 bit computer project I'm working on. The boards, except the A register board, are double sided. Unfortunately no plated throughholes but there are functional vias with a piece of wire. Will definitely be posting more update about the entire project as I'm slowly finishing it. submitted by /u/p3623 [link] [comments]

submitted by /u/_binda77a [link] [comments]

Materials, networking and laser technology firm Coherent Corp of Saxonburg, PA, USA and quantum technology company Quside have reached a milestone in hardware-based security with the demonstration of a mass-manufacturable quantum entropy source. This shows that fast, verifiable quantum entropy — an essential foundation for secure digital systems — can be embedded at scale, supporting next-generation security architectures across a wide range of applications...

Various designs for current mirror circuits have been an active topic recently here in Design Ideas (DIs). Usually, the mirror designer’s aim is to make the mirror’s input and output currents accurately equal, but Figure 1 shows one that takes a tangent. Being immune to traditional current mirror bugaboos (Early effect, etc.), it can achieve the equality criterion quite well, but it also has particular versatility in applications where the input and output currents deliberately differ.

Figure 1 The R1/R2 resistance ratio sets the I2/I1 current ratio.

Wow the engineering world with your unique design: Design Ideas Submission Guide

Here’s the backstory: Awhile back, I published a DI that used the venerable family of TLx431 shunt voltage regulators as programmable current regulators: “Precision programmable current sink.”

Figure 1 demonstrates their versatility again, this time combining two of the beasties to make a programmable gain current mirror. 

The choice between the 2.5-V reference voltage TL431 and the 1.24-V TLV431 can be based on their different current and voltage ratings. For current: 1 mA to 100 mA for the TL versus 100 µA to 15 mA for the TLV. For voltage: 2.5 V to 36 V for the TL versus 1.24 V to 6 V for the TLV.

Note that both I1 and I2 must fall within those respective current numbers for useful regulation (and reflection!) to occur. Minimum mirror input voltage = Vref + I2R2.

Of course, you must also accommodate the modest heat dissipation limits of these small devices. However, the maximum current (and power) capabilities can be extended virtually without limit by the simple ploy shown in Figure 2.

Figure 2 Booster transistor Q1 can handle current and power beyond 431 max Ic and dissipation limits.

And one more thing. 

You might reasonably accuse Z1 of basically loafing since its only job is to provide bias voltage for R1 and Z2. But we can give it more interesting work to do with the trick shown in Figure 3. Not only can this scheme accommodate arbitrary I1/I2 ratios, but we can also add a fixed offset current! Here’s how.

Figure 3 Add six resistors and one transistor to two TL431s to make this 0/20 mA to 4/20 mA current loop converter. Z2 sums the 500-mV offset provided by Z1 with the 0 to 2 V made by current sensor R1, then scales that with R2 to output the 4 to 20 mA with a boost from Q1 that can accommodate loop voltages up to 36 V. Note R1, R2, R4, and R6 need to be precision types.

What results here is a (somewhat simpler) solution to an application borrowed from a previous DI by frequent contributor R Jayapal in: “A 0-20mA source current to 4-20mA loop current converter.”

In electronic design, it seems there’s always more than one way to defrock a feline.

Stephen Woodward’s relationship with EDN’s DI column goes back quite a long way. Over 100 submissions have been accepted since his first contribution back in 1974.

Related Content

• Precision programmable current sink
• A 0-20mA source current to 4-20mA loop current converter
• Silly simple precision 0/20mA to 4/20mA converter

The post Combine two TL431 regulators to make versatile current mirror appeared first on EDN.

Artificial Intelligence (AI), like any other technology, comes with its own set of boons and banes. According to the Stanford AI Index 2024, India ranks first globally in AI skill penetration with a score of 2.8, ahead of the US (2.2) and Germany (1.9). AI talent concentration in India has grown by 263% since 2016, positioning the country as a major AI hub. India also leads in AI Skill Penetration for Women, with a score of 1.7, surpassing the US (1.2) and Israel (0.9).

India in its AI Era

According to a PIB report, India is one of the top five fastest-growing AI talent hubs, alongside Singapore, Finland, Ireland, and Canada. The demand for AI professionals in India is projected to reach 1 million by 2026. Taking this advancement into mind, all eyes will be on the Budget for 2026, judging what the government intends to propose to boost the AI landscape in India.

“India’s rapid advancement in the AI era places the spotlight on the upcoming Union Budget as a decisive moment for building a future-ready workforce. With over 40% of India’s IT and gig workforce already utilising AI tools, and India projected to account for the world’s AI talent by 2027, there is clear momentum; yet, significant gaps remain.

Although the employability of the workforce has improved, some part of the young workforce possesses deep AI skills, and many companies complain about the difficulties in hiring the right people. The provision of more funds for AI workforce training programs, along with the National Education Policy’s emphasis on the incorporation of applied AI, data science, and digital technologies into the curriculum, is important. We anticipate policies that foster close cooperation between the industry and the universities, provide incentives for certifying the basic knowledge gained through practical training, and allow more students to have access to hands-on labs and internships. Not only will these measures lift the entry-level skills of the labour force, but they will also make it certain that the young population of India is capable of turning to the global market as the main supplier of leaders in the coming years,” says Tarun Anand, Founder & Chancellor, Universal AI University.

Shortcomings of AI: Cybersecurity Threats

While AI has great potential and proposed advanced opportunities in various sectors, it comes with its own set of shortcomings. The issues of cybersecurity have escalated significantly in the AI era. Subsequently, it will be important to note what the new budget has in store to build on cybersecurity, as AI will continue to dominate the Indian landscape.

“As India approaches the 2026 Union Budget, the cybersecurity sector does so with clarity: compliance is no longer optional, and policy must now accelerate infrastructure transitions that enterprises cannot manage alone. In 2025, India faced nearly 265 million cyberattacks, with AI-driven ransomware democratizing threats at an unprecedented scale.

First, cybersecurity data centre infrastructure must be formally recognised as a critical national asset. Expanding the PLI framework to include cybersecurity data centres would strengthen India’s cyber sovereignty and reduce reliance on offshore infrastructure.

Second, the Budget should enable public–private partnerships to bolster SME cyber resilience. Manufacturing and mid-market enterprises are increasingly targeted by ransomware-as-a-service, yet lack access to enterprise-grade security. Government-backed subsidies routed through certified MSP networks would protect the Make in India ecosystem while democratizing DPDP compliance at scale.

Third, India must invest decisively in cybersecurity talent infrastructure. With a shortage of over 80,000 professionals, Budget 2026 should fund structured partnerships between government, academic institutions, and industry certifiers. This would create a domestic talent pipeline comparable to Singapore’s model. While we currently train over 2,000 professionals annually, government backing could scale this to more than 10,000 within three years.

The DPDP execution phase, starting in November 2026, will ultimately determine whether cyber resilience scales equitably across the country or remains concentrated in metro markets. Through targeted investments in infrastructure, partnerships, and education, the 2026 Budget has the opportunity to shape that outcome decisively,” says Rajesh Chhabra, General Manager, India and South East Asia, Acronis

By: Shreya Bansal, Sub-Editor

The post India’s Next Big Concern in the AI Era: Cybersecurity for Budget 2026 appeared first on ELE Times.

As high-performance computing (HPC) workloads become increasingly complex, generative artificial intelligence (AI) is being progressively integrated into modern systems, thereby driving the demand for advanced memory solutions. To meet these evolving requirements, the industry is developing next-generation memory architectures that maximize bandwidth, minimize latency, and enhance power efficiency.

Technology advances in DRAM, LPDDR, and specialized memory solutions are redefining computing performance, with AI-optimized memory playing a pivotal role in driving efficiency and scalability. This article examines the latest breakthroughs in memory technology and the growing impact of AI applications on memory designs.

Advanced memory architectures

Memory technology is advancing to meet the stringent performance requirements of AI, AIoT, and 5G systems. The industry is witnessing a paradigm shift with the widespread adoption of DDR5 and HBM3E, offering higher bandwidth and improved energy efficiency.

DDR5, with a per-pin data rate of up to 6.4 Gbps, delivers 51.2 GB/s per module, nearly doubling DDR4’s performance while reducing the voltage from 1.2 V to 1.1 V for improved power efficiency. HBM3E extends bandwidth scaling, exceeding 1.2 TB/s per stack, making it a compelling solution for data-intensive AI training models. However, it’s impractical for mobile and edge deployments due to excessive power requirements.

Figure 1 The above diagram chronicles memory scaling from MCU-based embedded systems to AI accelerators serving high-end applications. Source: Winbond

With LPDDR6 projected to exceed 150 GB/s by 2026, low-power DRAM is evolving toward higher throughput and energy efficiency, addressing the challenges of AI smartphones and embedded AI accelerators. Winbond is actively developing small-capacity DDR5 and LPDDR4 solutions optimized for power-sensitive applications around its CUBE memory platform, which achieves over 1 TB/s bandwidth with a significant reduction in thermal dissipation.

With anticipated capacity scaling up to 8 GB per set or even higher, such as 4Hi WoW, based on one reticle size, which can achieve >70 GB density and bandwidth of 40TB/s, CUBE is positioned as a viable alternative to traditional DRAM architectures for AI-driven edge computing.

In addition, the CUBE sub-series, known as CUBE-Lite, offers bandwidth ranging from 8 to 16 GB/s (equivalent to LPDDR4x x16/x32), while operating at only 30% of the power consumption of LPDDR4x. Without requiring an LPDDR4 PHY, system-on-chips (SoCs) only need to integrate the CUBE-Lite controller to achieve bandwidth performance comparable to full-speed LPDDR4x. This not only eliminates the high cost of PHY licensing but also allows the use of mature process nodes such as 28 nm or even 40 nm, achieving performance levels of 12-nm node.

This architecture is particularly suitable for AI SoCs or AI MCUs that come integrated with NPUs, enabling battery-powered TinyML edge devices. Combined with Micro Linux operating systems and AI model execution, it can be applied to low-power AI image sensor processor (ISP) edge scenarios such as IP cameras, AI glasses, and wearable devices, effectively achieving both system power optimization and chip area reduction.

Furthermore, SoCs without LPDDR4 PHY and only CUBE-light controller can achieve smaller die sizes and improved system power efficiency.

The architecture is highly suitable for AI SoCs—MCUs, MPUs, and NPUs—and TinyML endpoint AI devices designed for battery operation. The operating system is Micro Linux combined with an AI model for AI SoCs. The end applications include AI ISP for IP cameras, AI glasses, and wearable devices.

Figure 2 The above diagram chronicles the evolution of memory bandwidth with DRAM power usage. Source: Winbond

Memory bottlenecks in generative AI deployment

The exponential growth of generative AI models has created unprecedented constraints on memory bandwidth and latency. AI workloads, particularly those relying on transformer-based architectures, require extensive computational throughput and high-speed data retrieval.

For instance, deploying LLamA2 7B in INT8 mode requires at least 7 GB of DRAM or 3.5 GB in INT4 mode, which highlights the limitations of conventional mobile memory capacities. Current AI smartphones utilizing LPDDR5 (68 GB/s bandwidth) face significant bottlenecks, necessitating a transition to LPDDR6. However, interim solutions are required to bridge the bandwidth gap until LPDDR6 commercialization.

At the system level, AI edge applications in robotics, autonomous vehicles, and smart sensors impose additional constraints on power efficiency and heat dissipation. While JEDEC standards continue to evolve toward DDR6 and HBM4 to improve bandwidth utilization, custom memory architectures provide scalable, high-performance alternatives that align with AI SoC requirements.

Thermal management and energy efficiency constraints

Deploying large-scale AI models on end devices introduces significant thermal management and energy efficiency challenges. AI-driven workloads inherently consume substantial power, generating excessive heat that can degrade system stability and performance.

• On-device memory expansion: Mobile devices must integrate higher-capacity memory solutions to minimize reliance on cloud-based AI processing and reduce latency. Traditional DRAM scaling is approaching physical limits, necessitating hybrid architectures integrating high-bandwidth and low-power memory.
• HBM3E vs CUBE for AI SoCs: While HBM3E achieves high throughput, its power requirements exceed 30 W per stack, making it unsuitable for mobile and edge applications. Here, memory solutions like CUBE can serve as an alternative last level cache (LLC), reducing on-chip SRAM dependency while maintaining high-speed data access. The shift toward sub-7-nm logic processes exacerbates SRAM scaling limitations, emphasizing the need for new cache solutions.
• Thermal optimization strategies: As AI processing generates heat loads exceeding 15 W per chip, effective power distribution and dissipation mechanisms are critical. Custom DRAM solutions that optimize refresh cycles and employ TSV-based packaging techniques contribute to power-efficient AI execution in compact form factors.

DDR5 and DDR6: Accelerating AI compute performance

The evolution of DDR5 and DDR6 represents a significant inflexion point in AI system architecture, delivering enhanced memory bandwidth, lower latency, and greater scalability.

DDR5, with 8-bank group architecture and on-die error correction code (ECC), provides superior data integrity and efficiency, making it well-suited for AI-enhanced PCs and high-performance laptops. With an effective peak transfer rate of 51.2 GB/s per module, DDR5 enables real-time AI inference, seamless multitasking, and high-speed data processing.

DDR6, still in development, is expected to introduce bandwidth exceeding 200 GB/s per module, a 20% reduction in power consumption along with optimized AI accelerator support, further pushing AI compute capabilities to new limits.

Figure 3 CUBE, an AI-optimized memory solution, leverages through-silicon via (TSV) interconnects to integrate high-bandwidth memory characteristics with a low-power profile. Source: Winbond

The convergence of AI-driven workloads, performance scaling constraints, and the need for power-efficient memory solutions is shaping the transformation of the memory market. Generative AI continues to accelerate the demand for low-latency, high-bandwidth memory architectures, leading to innovation across DRAM and custom memory solutions.

As AI models become increasingly complex, the need for optimized, power-efficient memory architectures will become increasingly critical. Here, technological innovation will ensure commercial realization of cutting edge of AI memory solutions, bridging the gap between high-performance computing and sustainable, scalable memory devices.

Jacky Tseng is deputy director of CMS CUBE product line at Winbond. Prior to joining Winbond in 2011, he served as a senior engineer at Hon-Hai.

Special Section: AI Design

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