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Практикум-тренінг для викладачів закладів професійної освіти kpi ср, 05/14/2025 - 23:07

На війні загинув випускник нашого університету Олег Аксьоненко kpi ср, 05/14/2025 - 22:59

Finwave Semiconductor Inc of Waltham, MA, USA has announced a new $8.2m bridge investment round, led by Fine Structure Ventures, Engine Ventures, and Safar Partners, with strategic participation from technology partner GlobalFoundries. Finwave reckons that the new funding signals strong conviction from investors and industry leaders in the market potential of its unique GaN-on-Si technology as it transitions from a technology-centric innovator to a product-driven company...

I have made a schematic of analog FM receiver!! submitted by /u/Calm_Ground2578 [link] [comments]

submitted by /u/Kotsaros [link] [comments]

Frequent contributor Nick Cornford recently shared design ideas incorporating cool circuits for linear-in-pitch voltage-controlled oscillators (LPVCOs): 

• Revealing the infrasonic underworld cheaply: Part 1 and Part 2
• A pitch-linear VCO: Part 1 and Part 2

Wow the engineering world with your unique design: Design Ideas Submission Guide

The linear in pitch function, which makes output frequency proportional to the antilog of voltage, is interesting because it provides a better perceptual interface to the inherently logarithmic human ear than a linear frequency. 

One measure of the performance of an LPVCO is its octave range. That’s the ratio of highest to lowest frequency that its output spans, expressed as the binary (base 2) logarithm of the ratio. Two octaves (22 = 4:1) is good. Three octaves (23 = 8:1) is better. The LPVCO in Figure 1 does seven (27 = 128:1). 

Figure 1 A seven-octave LPVCO comprises Q1 Q2 antilog pair that converts the 0 V to 5 V Vin, to a 1 µA to 128 µA Ic2, for a proportional 27 = 128:1 change in C1 ramp rate and U1 oscillation frequency. Counter U2 then scales the U1 oscillation frequency by 4 and converts to a three-level, very vaguely “sine-ish,” output waveform.

Here’s how it works.

Control voltage Vin is scaled by a voltage divider (R1/R2 + 1) = 34:1 and applied to the Q1 Q2 exponential-gain current mirror. There, it is level-shifted and temperature-compensated by Q1, then anti-logged by Q2 to produce

Ic2 = 2(1.4Vin) µA. The resulting C1 timing ramp spans from 5 ms (for Vin = 0) to 40 µs (for Vin = 5 V). The ramp ends when it crosses analog timer U1’s 1.67-V trigger level and is reset via R5 and D1 to U1’s threshold level of 3.33 V, starting another oscillation cycle. The resulting sawtooth will therefore repeat at F = Ic2/(1.67C2) = 2(1.4Vin) µA / 5nCb = 200 (2(1.4Vin) ) Hz.

Nick’s lovely designs show that short pulses such as U1’s output spikes require conversion to a waveshape with a less intense harmonic content if we want to hear a listenable audio output. Therefore, U2’s switch-tail counter divides U1’s oscillation frequency by 4. This produces a hardly sinusoidal, but at least somewhat less annoying, tri-level 50 Hz to 6400 Hz final output.

Thanks go to Nick for a fun and well-conceived design topic, and of course to editor Aalyia for her friendly Design Idea department format that makes such enjoyable collaboration possible!

Stephen Woodward’s relationship with EDN’s DI column goes back quite a long way. Over 100 submissions have been accepted since his first contribution back in 1974.

 Related Content

• Revealing the infrasonic underworld cheaply, Part 1
• Revealing the infrasonic underworld cheaply, Part 2
• A pitch-linear VCO, part 1: Getting it going
• A pitch-linear VCO, part 2: taking it further
• Can a free running LMC555 VCO discharge its timing cap to zero?

The post Seven-octave linear-in-pitch VCO appeared first on EDN.

Казковий і предметний світи Като Лукач Інформація КП ср, 05/14/2025 - 14:57

At SID Display Week 2025 (13–15 May), fabless micro-LED company Porotech (a spin off from the Cambridge Centre for Gallium Nitride at the UK’s University of Cambridge that has developed porous GaN material and has an R&D center in Hsinchu, Taiwan) is leading the ‘One-Stop AR Solution Alliance’ alongside key partners Foxconn, Rayprus, GIS, and Jorjin with a grand showcase in booth 1208 at the San Jose McEnery Convention Center...

As it celebrates its fifth birthday, III–V Epi Ltd of Glasgow, Scotland, UK — which provides a molecular beam epitaxy (MBE) and metal-organic chemical vapor deposition (MOCVD) service for custom compound semiconductor wafer design, manufacturing, test and characterization — says that it has demonstrated consistent growth, establishing its reputation as a trusted supplier of III-V epitaxial structures through MBE and MOCVD...

Introduction

The computer mouse is a crucial tool for both work and playing games. Many brands are creating special designs to make using them better. In India, there is a wide variety of mice that suit different needs, such as professional tasks, simple internet browsing, or playing games competitively. This article will look at top 10 mouse brands available today. It will discuss where each brand began, highlight their main features, and also mention some of their popular model.

1. Logitech

Logitech, a swiss-based company, is known for its excellent computer peripherals, with top-selling mouse models like Logitech B170, M186, and G502(Gaming). Famous for its excellent computer peripherals, Logitech mice offer ergonomic shapes, precise tracking, and long battery life. Top-selling models are Logitech B170, M186, and G502(Gaming).

2. HP

HP, which has its base in the United States, offers reliable office and gaming mice like the HPX200 Wireless Mouse and OMEN Vector (Gaming). Offers reliable office and gaming mice with smooth silky performance, adjustable DPI adjustment, and wireless-connectivity. Best models include HPX200 Wireless Mouse and OMEN Vector (Gaming).

3. Dell

Dell, a US company, provides affordable and efficient mice like Dell MS 116 (Wired) and Alienware AW610M (Gaming). Provides affordable mice with plug-and play ease, LED tracking, and tough build. Top models are Dell MS116 (Wired) and Alienware AW610M(Gaming).

4. Lenovo

Lenovo is a Chinese organization which produces stylish and ergonomic mice like Lenovo    Legion M200 (Gaming) and Yoga Mouse. Designs stylish and ergonomic mice with DPI sensor, ambidextrous design, and wireless Bluetooth connectivity. Both models are Lenovo Legion M200(Gaming) and Yoga Mouse.

5. Zebronics

Zebronics, which is an Indian brand, offers budget- priced mice such as Zebronics Zeb-Jaguar and Blanc Slim. Indian brand known for budget-priced silent click, DPI- adjustable mice with elegant looks. Its top models include Zebronics Zeb-Jaguar and Blanc Slim.

6. Redragon

Redragon, a Chinese company, specializes in gaming peripherals, with products such as the Redragon M808 Storm and Cobra M711. Specializes in gaming peripherals with customizable buttons, RGB lights, ultra-fast sensors, and high DPI. Best-selling products include Redgraon M808 Storm and Cobra M711.

7. Razer

Razer Inc. is a global technology firm that deals in gaming hardware, consumer electronics. It is dual headquartered in Singapore and Irvine, California, USA. Razer is renowned for its high-performance gaming peripherals, such as mice, keyboards, headsets, and laptops.  A high-end gaming brand, providing high-performance mice with ultra-high- performance mice with ultra-sensitive sensors, programmable RGB lighting, and programmable buttons. Famous models are Razer DeathAdder V2 and Basilisk X Hyperspeed.

8. Apple

Apple’s mouse line comes from the United States, originally founded in 1976. Apple mice have come a long way, from the one-button Lisa Mouse in 1983 to the Magic Mouse 2, which brought laser tracking and multi-touch gestures. The newest iteration, the Magic Mouse, is a wireless, rechargeable mouse that features a multi-touch surface through which the user can swipe back and forth between web pages. Apple revised the Magic Mouse in 2024 with a USB-C port, replacing the earlier Lightning connector.

9. Microsoft

Microsoft’s mouse logo has its origins in the United States, as Microsoft was founded in 1975. Microsoft first launched a mouse in 1983, which had a steel ball for tracking. The newest models are the Surface Arc Mouse, an ultra-slim, lightweight mouse, it is connected via Bluetooth and includes a touch surface that allows users to scroll vertically or horizontally. Microsoft Pro IntelliMouse, which is right-handed, includes a 16000 DPI resolution, and includes high-speed tracking.

10. Corsair

Corsair is an American corporation based in Milpitas, California, USA. The organization majors in gaming hardware, peripherals with high performance, computer parts, and accessories like keyboards, mice, power supply units, coolers and streaming devices. Deals in gaming peripherals, with mice having high DPI optical sensors, programmable macros, and ergonomic grips. Famous models are Corsair Harpoon RGB and Dark Core Pro.

The market share distribution of mouse brands In India is as follows:

 

Brands	Market Share %
Logitech	25%
HP	18%
Dell	15%
Razer	10%
Zebronics	8%
Lenovo	7%
Corsair	5%
Redragon	4%
Microsoft	5%
Apple	3%

 

Conclusion

India’s market for computer mouse is growing at a steady pace, fuelled by rising demand for wireless and ergonomically-designed mice. The market for computing mouse is expected to expand by USD 3.43 billion from 2024 to 2029, at a Compound Annual Growth Rate (CAGR) of 14.1%. Top brands like Logitech, HP, and Dell continue to dominate the professional and high-end segments, while local brand like Zebronics cater to cost conscious customers with value-added offerings.

The post TOP 10 Mouse brands in India appeared first on ELE Times.

Add-on features are all the rage in electronic products. But are they actually handy or just embody bells and whistles? What’s their hardware and software cost? And more importantly, do they serve an actual value or merely add to the user-experience clutter? Bill Schweber looks at this user interface mystery and finds some answers.

Read the full story at EDN’s sister publication, Planet Analog.

Related content

• Coffee Teardown: Simple, Effective Design
• What’s the Impact of Medical-Design Mandates?
• Soft on/off is designer’s dilemma, user’s headache
• Extreme Analog Design: Don’t Forget Those Passives
• AVAS and the dilemma of ‘too good to be true’ designs
• Instrumented Hockey Puck is an Extreme Analog Design
• With so many mandates, can we still deliver a product design?

The post Add-on features in electronic products: The good part appeared first on EDN.

ST is launching the TeseoVI, our first single-die quad-band GNSS receiver, which also features anti-jamming and anti-spoofing technologies. As car makers demand more precision and reliability for applications like level 2 and level 3 autonomous driving, we also wanted to lower costs to make those technologies even more accessible to mainstream vehicles. Indeed, by offering a single-die system, we can significantly lower the bill of materials without compromising the smarter capabilities car makers bring to their drivers. The TeseoVI also features a pin-to-pin compatibility between its safety-capable (ASIL-B) and non-safety versions for greater design flexibility.

TeseoVI: Moving to a single die Why is a single die a challenge? TeseoVI (STA8600A) in a VFQFPN package

Most GNSS receivers for automotive feature multiple dies in one package. There’s the digital microcontroller, a baseband radio, and sometimes a third die for memory. The industry adopted this approach because it bypassed significant manufacturing challenges that come from putting everything on the same die. Moreover, adding enough memory can also lead to a big die size, lowering yields and making devices more expensive. Using multiple dies also makes optimizing the RF easier, which leads to greater precision. Single-die GNSS receivers are typical in smartphones and much smaller systems that don’t require as much accuracy but have remained a problem for cars.

How did TeseoVI overcome this challenge?

That’s why the TeseoVI is special. It brings the convenience and cost-effectiveness of the single-die approach that’s so popular on smartphones while overcoming the precision and reliability challenges that prevented such an approach from serving cars. To make this possible, ST optimized the RF and the phase-change memory (PCM), among other things. For the former, we employed a new generation of baseband processing, opening the door to new features (more on that later).

TeseoVI: Jamming protection What are the L1 and L5 signal bands?

One of the features brought on by the new baseband processor is the ability to track L1 and L5 signals independently. L1 is the oldest GNSS signal, using a frequency of 1575.2 MHz. It’s the slowest and doesn’t travel well through obstacles, but its maturity means it is a preferred signal for most satellite positioning applications. L5 uses the 1176 MHz frequency and is the most advanced GNSS signal. Launched in 2021, it targets critical applications, like aviation, but is also available for consumer systems. It offers greater bandwidth thanks to higher power levels, improved accuracy thanks to interference rejection, and better robustness. Indeed, thanks to its lower frequency, it features a longer wavelength that deals better with obstacles.

How to jam the L1 signal?

Another reason supporting L1 and L5 signals independently is essential is because it provides anti-jamming protection. Jamming happens when a signal overwhelms the receiver. It can result from unintentional electromagnetic interference from antennas or large infrastructure emitting intense radiation. There are also dedicated jammers to bypass fleet monitoring, insurance trackers, and more. The L1 frequency is very easy to jam. It doesn’t have redundancy features, and its low signal strength is easy to overwhelm, which causes the GNSS receiver to lose its lock on the signal, thus failing to acquire navigation data. It’s so easy that L1 jammers, although illegal in most countries, may cost less than US$20, according to The Resilient Navigation and Timing Foundation.

TeseoVI and anti-jamming

Interestingly, even GNSS receivers that track L5 signals may require the L1 signal. Indeed, many devices acquire timing data from the L1 signal during their boot sequence and then use it to lock onto the L5 signal. The problem is that even a low-cost jammer could prevent a device from acquiring data from the L1 signal, meaning the receiver can’t use the L5 band. The new baseband processing in the TeseoVI introduced an L5-only mode, meaning it doesn’t need L1 to acquire data on L5. Consequently, it can bypass jammers. Additionally, L5 is so robust some estimate it to be 30 times harder to jam than L1.

TeseoVI: Spoofing protection How to spoof a GNSS signal? TeseoVI+ (STA8610A)

The new TeseoVI also supports the open service navigation message authentication (OSNMA) from the Galileo constellation. In a nutshell, the feature prevents spoofing attacks by cryptographically authenticating the source of a message. Very simply, the technology uses a message authentication code (MAC) to guarantee the authenticity of a signal’s provenance. It doesn’t encrypt the whole message but sends a series of codes, which is a far more efficient use of the bandwidth. Consequently, since Galileo generates the code, hackers can’t fake it. Additionally, since the standard sends multiple codes over time, hackers can’t just grab one key and reuse it in a replay attack. By the time they do so, the key has expired.

How to support OSNMA?

To support OSNMA, hardware manufacturers must update their firmware and their software stack and offer enough processing power to handle the extra computations. This is why ST also provides extensive software implementations with its GNSS receivers. We know that taking advantage of new features can be complex. In this instance, decoding the OSNMA fields and managing the keys requires complex libraries that must pass audits and receive regular updates. Hence, the TeseoVI not only supports this anti-spoofing technology but enables developers to take advantage of it in their applications rapidly.

Making multiband more accessible More advanced features to mainstream cars Teseo-ELE6A

One of the greatest benefits of a single-die design is the ability to lower the cost of materials. In fact, since there’s no need for external RF and external memory, engineers may target a BOM cost of about a dollar. Obviously, this is only a general reference point. In practice, the price will vary based on the complexity of the design and volumes. However, in all cases, it means that previous customers who used to avoid multiband solutions because they were too expensive will now be able to jump on the bandwagon. For instance, we can expect level 2 and 3 autonomous driving features to reach more mainstream vehicles.

More flexibility to integrators Teseo-VIC6A

The TeseoVI is also the first GNSS receiver for automotives to have a pin-to-pin compatible version for safety applications, the TeseoAPP2 (STA9200MA), which features the same QFN56 package as the TeseoVI (STA8600A). As a result, developers can simply create one reference design and switch between the ASIL-certified and the non-certified part number, depending on their needs.

ST will also be offering the TeseoVI+ (STA8610A). It’s the same device as the TeseoVI, but the TeseoVI+ can welcome custom algorithms thanks to dual M7 Core Processing and External Memory Interface (Flash/RAM). Hence, teams wanting to use their application can do away with our positioning and measurement software. Finally, we also offer a module with a 6-axis inertial sensor, the Teseo-VIC6A, and its safety alter ego, the Teseo-ELE6A.

The post TeseoVI: ST’s 1st single-die quad-band GNSS receiver makes autonomous driving mainstream appeared first on ELE Times.

MOUs Signed with Indian Government and Inauguration of Renesas’ Bengaluru and Noida Offices Mark Investments to Accelerate Growth in India’s Key Semiconductor Hubs

Renesas Electronics Corporation announced its partnership with the Ministry of Electronics & Information Technology (MeitY), Government of India, to support local startups and academic institutions in the field of VLSI and embedded semiconductor systems. Renesas also celebrated the expansion of its offices in Bengaluru and Noida to accommodate its growing R&D teams, with the inauguration ceremonies. This strategic move underscores Renesas’ commitment to innovation and excellence in India and aims to drive continued growth in the region.

Renesas and the Centre for Development of Advanced Computing, an autonomous scientific society of MeitY, today signed and exchanged two Memoranda of Understanding (MOUs) under the MeitY Chips to Startup. These MOUs focus on 1) Supporting local startups by enabling them to drive technological advancement and promote local manufacturing in alignment with the Make in India initiative; and 2) Enhancing industry-academia collaboration by fostering an innovative, product-focused mindset among students.

India is a key market for Renesas, offering significant growth potential and access to a highly skilled talent pool. Recent collaborations include the OSAT factory project with CG power and Stars Microelectronics in Gujarat and the MOU with IIT Hyderabad. Renesas is also expanding its operations in India, with plans to increase its headcount to 1,000 by the end of 2025. This growth initiative reinforces Renesas’ long-term commitment to India and supports its ambition to become an employer of choice in this dynamic and fast-evolving market.

“The inauguration of our expanded offices marks a significant milestone for Renesas in India. It reflects our unwavering commitment to innovation, excellence, and the nurturing of local talent. By building products in India, for India and the world, we continue to drive growth and deliver meaningful impact across the Indian market,” said Malini Narayanamoorthi, India Country Manager and VP, MID Engineering, Analog & Connectivity Group at Renesas. “We are proud to sign two MOUs under the MeitY C2S programme, focused on advancing research, fostering innovation, and nurturing product-focused engineers. These strategic collaborations align with the Make in India initiative, aiming to strengthen local design and manufacturing capabilities and empower homegrown talent to drive the future of industry.”

MOUs under MeitY C2S programme

Renesas and C-DAC signed two MOUs to collaborate in the field of VLSI and embedded semiconductor systems, with the aim of supporting local startups and academic institutions to accelerate innovation and foster self-reliance in India’s semiconductor and product ecosystem. The C2S programme encompasses collaboration with over 250 academic institutions and R&D organizations across the country, including IITs, NITs, IIITs, government and private colleges, along with approximately 15 startups, creating a strong ecosystem for indigenous innovation.

• MOU for Startups: Renesas will help strengthen the product engineering capabilities of local startups by providing Renesas development boards and Altium Designer,the leading PCB design software.
• MOU for Academic Institutions: Renesas will support experiential learning by offering development boards, PCB education and training, Altium Designer software, and access to the Altium 365 cloud platform, aiming to empower the next generation of electronics engineers and nurture a community of innovators.

The post Renesas Partners with Indian Government to Drive Innovation Through Startups and Industry-Academia Collaboration, Strengthening India’s Semiconductor Ecosystem appeared first on ELE Times.

submitted by /u/9551-eletronics [link] [comments]

Infineon Technologies AG introduces PSOC 4100T Plus, an Arm Cortex-M0+ microcontroller (MCU) with Multi-Sense. The new microcontroller offers a rich blend of analog and digital capabilities, featuring 128K Flash, 32K SRAM, and Infineon’s high-performance Multi-Sense technology, which includes CAPSENSE, inductive sensing and liquid level sensing. PSOC 4100T Plus also boasts enhanced reliability and is equipped with a range of enhancements and advanced sensing capabilities to form a complete solution for system control and human-machine interface applications.

“Infineon is committed to delivering best-in-class system control and HMI solutions with enhanced reliability,” says Vibheesh Bharathan, Director and Project Lead for PSOC 4 Multi-Sense from Infineon. “Our Multi-Sense capability represents a paradigm shift, driving next-generation sensing solutions for HMI and system control use cases. In this way, we are enabling the digitalization solutions of tomorrow for consumer and industrial applications.”

PSOC 4100T Plus can be used as a standalone general-purpose microcontroller, providing a robust platform for system control and management OR it can be utilized as a specialized HMI MCU, enabling the creation of intuitive and interactive interfaces. Alternatively, PSOC 4100T Plus can serve a single chip solution for both system control and touch HMI.

In its HMI MCU configuration, the device supports a range of sensing applications, including capacitive sensing for detecting user touch or proximity, inductive sensing for enabling touch over metallic surfaces, Machine Learning based liquid level sensing for monitoring liquid presence or levels, and CAPSENSE-based hover touch for detecting finger touch through a large airgap, making it a powerful tool for creating innovative and user-friendly interfaces.

PSOC 4100T Plus is a versatile and powerful platform designed to support a broad range of applications. For example:

Home appliances: Reliability is the top priority for home appliances. The PSOC 4100T Plus series addresses this critical requirement with significant enhancements, including 6500 V best-in-class electrostatic discharge protection and a 1% internal main oscillator accuracy. In addition, the advanced HMI features, such as hover touch, provide a solution to several design challenges, including the need for simplified and cost-effective stack up, touch operation through airgap. With the combination of complementary sensing technologies of Multi-Sense, designers can effectively address the design challenges they face.

Consumer electronics: PSOC 4100T Plus series elevates the human-machine interface capabilities in consumer electronics by providing a compact and efficient solution for sensor designs. Leveraging its 5th Generation CAPSENSE technology, the PSOC 4100T Plus offers high signal-to-noise ratio and low power consumption. Additionally, its waterproof design enables the device to operate reliably in harsh environments, including outdoor applications.

Touchpad and touchscreen applications: PSOC 4100T Plus series offers a high resolution 2D finger tracking user interface, enabling the creation touchpads and touchscreens. With 32 sensor inputs, the device can be configured to support up to 256 nodes, allowing for a wide range of design possibilities. For example, a touchpad can be designed with an 80mm x 80mm surface area with a 5mm diamond pitch, resulting in a high-resolution multi-finger tracking. Similarly, a 4-inch touchscreen can be driven by PSOC 4100T Plus for multi-finger use. Both touchpad and touchscreen user interfaces supported with built-in, configurable gesture engine.

To support the development of multi-sense applications, a comprehensive suite of software tools and resources are offered. The CAPSENSE Tuner allows designers to easily configure and optimize capacitive sensing applications, while the Inductive Sensing Design Guide and Liquid Level Sensing Design Guide provide detailed guidance on implementing these technologies. Additionally, the ML-based liquid level sensing model trainer enables developers to overcome challenges like manufacturing variations, varying airgaps with removable tanks.

The post PSOC 4100T Plus microcontroller offers advanced sensing capabilities and system control in a single chip appeared first on ELE Times.

This is my final semester at community college. I wil be attending a 4 year university this fall, as a junior, to finish off my bachelor's in electrical engineering. My final project is an analog function generator. It is capable of generating a sine wave, triangle wave, and a square wave. It is based on an online project called "Analog Function Generator" by "laserjocky". The circuit consists of op-amps, resistors, capacitors, transistors, potentiometers, and switches. The images are of the initial wave created by a specific op-amp and the final wave generated at the final output. submitted by /u/Accomplished_Pace860 [link] [comments]

Midsummer AB of Järfälla, near Stockholm, Sweden – a developer and manufacturer of flexible, lightweight copper indium gallium diselenide (CIGS) thin-film solar cells and roofs for building-integrated photovoltaics (BIPV) as well as equipment for their production – has received an order worth SEK143.5m (€13.1m; US$14.8m) from a Swedish industrial and defense group for a turnkey production line for the manufacturing of thin-film solar cells...

Luminus Devices Inc of Sunnyvale, CA, USA — which designs and makes LEDs and solid-state technology (SST) light sources for illumination markets — has launched the CFT-50X Series, an extensive product line of high-performance LEDs designed specifically for medical, life sciences, and industrial applications. Available now through authorized distributors, the new series offers versatility, with 10 distinct SKUs spanning from UVA (405nm) to Red (638nm), meeting the demanding requirements of medical endoscopy, biophotonic, fluorescence microscopy and machine vision markets...

A new software combines connectivity, scalability and data-driven artificial intelligence (AI) capabilities to push the boundaries of the IC verification process and make chip design teams more productive. Questa One aims to address the verification productivity gap for large, complex designs spanning IP to IC to systems.

The steadily increasing complexity of 3DICs, chiplet-based designs, and software-defined architectures is further compounded by a critical talent shortage and growing demands for enhanced security and lower power consumption. “Questa One uses new technical advances to deliver the fastest functional, fault, and formal verification engines available,” said Abhi Kolpekwar, VP and GM of digital verification technologies at Siemens EDA.

Figure 1 Questa One strives to redefine IC verification from a reactive process into an intelligent, self-optimizing system. Source: Siemens EDA

A recent Wilson Research Group survey suggests that one in seven IC projects achieves first-time silicon success. Chris Giles, director of product management for static and formal at Siemens EDA, calls this a jaw-dropping and staggering drop. “Our approach is to enable engineers to do more with less, with not just faster engines but also faster engineers with fewer workloads,” he said.

Figure 2 Here is a view of the decline in first-time silicon success and the increase in FPGA bugs. Source: Wilson Research Group

Giles spoke with EDN to explain the technology fundamentals of this new verification tool.

Quest One’s three tenets

Giles said that Questa One has been developed around three core principles:

1. Scalable verification: It allows engineers to speed verification closure. Giles noted that the semiconductor industry is struggling to tackle large designs. “That’s why we see a decline in first-time silicon success,” he added. “Chip designs are getting so large that it’s difficult to verify them in one piece.” Questa One verification aims to allow engineers to work on large chip designs.
2. Data-driven verification: It leverages data for AI-powered analytics to bring new insights and to improve verification productivity. “It collects datasets that allow verification tools to either make recommendations or directly decide what to do next and do it productively,” said Giles.
3. Connected verification: Questa One connects EDA tools and verification IP to form a cohesive ecosystem for robust verification, validation, and test operations. In other words, it uses a broad set of technologies and analyses to provide insights and raw verification power.

Figure 3: Questa One offerings are shown with three main value propositions summed up at the bottom. Source: Siemens EDA

Quest One’s four components

Questa One has the following focus areas:

1. Questa One simulator: This simulator engine is built from the ground up. It performs functional and fault simulation for RTL, GLS, and DFT applications with parallel processing and profiling add-ons.
2. Questa One SFV: The stimulus-free verification (SFV) solution delivers user productivity through synergistic combinations of static and formal analyses, AI, automation, and parallelization. “The current static and formal technology is very fragmented, challenging high productivity,” Giles said. “SFV integrates static and formal analyses, AI, and parallelization to address this challenge.”
3. Questa One verification IQ: It’s a coverage solution that utilizes generative, analytic, and prescriptive AI to drive verification closure faster with fewer workloads. “It features an intelligent interface that provides insight into the entire verification ecosystem,” Giles added.
4. Questa One Avery VIP: The solution, based on Avery’s high-quality VIP and high-coverage compliance test suites (CTS), offers protocol-aware debug and coverage analytics to help increase productivity. It supports 3DIC and chiplet verification from IP to system-on-chip (SoC) design.

Figure 4 Four main components of Questa One include a simulator, a static and formal verification solution, a verification intelligence coverage analysis solution, and an Avery identifier. Siemens EDA

Questa One in works

Semiconductor IP supplier Rambus acknowledged an improved verification experience in managing data center workloads like generative AI while implementing IPs for PCIe, CXL, and HBM interfaces. Rambus particularly mentioned Questa One’s simulation, static and formal analysis, and verification IP technologies.

Then there is Arm, which used Questa One simulator to reduce regression time in its latest AArch64 architecture. “The Questa One verification solution has improved our verification productivity across traditional on-premises and cloud deployments,” said Karima Dridi, head of productivity engineering at Arm.

MediaTek, another early user of Questa One, has utilized its formal verification and simulation technologies. “Questa One Property Assist utilizes generative AI to save us weeks of engineering time, and Questa One Regression Navigator predicts which simulation tests are most likely to fail, runs them first, and saves days of regression and debugging time,” said Chienlin Huang, senior technical manager of Connectivity Technology Department at MediaTek.

Questa One claims to yield step-function gains in smart regression, smart analysis, smart engine, and smart debug domains. Design testimonials from Arm, MediaTek, and Rambus are a good start.

Related Content

• How Do You Verify IC Performance?
• Integrate tools for effective verification
• The profile of a data-driven IC design verification tool
• Why verification matters in network-on-chip (NoC) design
• IC design: A short primer on the formal methods-based verification

The post IC verification tool addresses design complexity, productivity gap appeared first on EDN.

На ФЕЛ вдосконалюють електрохірургічні установки Інформація КП вт, 05/13/2025 - 17:55