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Intel ups the advanced packaging ante with EMIB-T

Embedded Multi-die Interconnect Bridge-T (EMIB-T) was a prominent highlight of the Intel Foundry Direct Connect event. Intel is promoting this advanced packaging technology as a key building block for high-speed chiplet designs and has partnered with major EDA and IP houses to accelerate implementations around EMIB-T technology.
As the nomenclature shows, EMIB-T is built around the Embedded Multi-die Interconnect Bridge (EMIB) technology, a high-bandwidth, low-latency, and low-power interconnect for multi-die silicon. EMIB-T stands for EMIB-TSV and it supports high-bandwidth interfaces like HBM4 and Universal Chiplet Interconnect Express (UCIe). In other words, it’s an EMIB implementation that uses the through-silicon via (TSV) technique to send the signal through the bridge with TSVs instead of wrapping the signal around the bridge.
Figure 1 EMIB-T, which adds TSVs to the bridge, can ease the enablement of IP integration from other packaging designs. Source: Intel
Another way to see EMIB-T is the combination of EMIB 2.5D and Foveros 3D packaging technologies for high interconnect densities at die sizes beyond the reticle limit. Foveros is a 3D chip stacking technology that significantly reduces the size of bump pitches, increasing interconnect density.
All three major EDA powerhouses have joined the Intel Foundry Chiplet Alliance Program, which is intrinsically linked to EMIB-T technology. So, all three are working closely with Intel Foundry to develop advanced packaging workflows for EMIB-T. Start with Cadence’s solution, which helps streamline the integration of complex multi-chiplet architectures.
Next, Siemens EDA has announced the certification of a TSV-based reference workflow for EMIB-T. It supports detailed implementations and thermal analysis of the die, EMIB-T and package substrate, signal and power integrity analysis, and package assembly design kit (PADK)-driven verification.
Synopsys is also collaborating with Intel Foundry to develop an EDA workflow for EMIB-T advanced packaging technology using its 3DIC Compiler. In addition to the EDA trio, Intel Foundry has engaged other players for EMIB-T support. For instance, Keysight EDA is working closely with Intel Foundry to bolster the chiplet interoperability ecosystem.
Figure 2 The EMIB-T advanced packaging technology promises power, performance, and area (PPA) advantages for multi-die chiplet designs. Source: Intel
The EMIB-T silicon bridge technology is a major step toward harnessing advanced packaging for the rapidly emerging chiplets world. Intel Foundry Direct Connect highlighted how the Santa Clara, California-based chipmaker sees this advanced packaging technology in its future roadmaps. More technical details about EMIB-T are likely to emerge later in 2025.
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- Intel Foundry: We Are Listening and Learning from Our Customers
The post Intel ups the advanced packaging ante with EMIB-T appeared first on EDN.
Infineon expands its GaN power portfolio with EasyPACK CoolGaN power modules for high-voltage applications
With the rapid growth of AI data centers, the increasing adoption of electric vehicles, and the ongoing trends in global digitalization and reindustrialization, global electricity demand is expected to surge. To address this challenge, Infineon Technologies AG is introducing the EasyPACK CoolGaN Transistor 650 V module, adding to its growing GaN power portfolio. Based on the Easy Power Module platform, the module has been specifically developed for high-power applications such as data centers, renewable energy systems, and DC electric vehicle charging stations. It is designed to meet the growing demand for higher performance while providing maximum ease of use, helping customers accelerate their design processes, and shorten time to market.
“The CoolGaN based EasyPACK power modules combine Infineon’s expertise in power semiconductors and power modules,” says Roland Ott, Senior Vice President and Head of the Green Energy Modules and Systems Business Unit at Infineon. “This combination offers customers a solution that meets the increasing demand for high-performance and energy-efficient technologies in applications such as data centers, renewable energy, and EV charging.”
The EasyPACK CoolGaN module integrates 650 V CoolGaN power semiconductors with low parasitic inductances, achieved through compact die packing enabling fast and efficient switching. Delivering up to 70 kW per phase with just a single module, the design supports compact and scalable high-power systems. Furthermore, by combining Infineon’s .XT interconnect technology with CoolGaN options, the module enhances both performance and reliability. The .XT technology is implemented on a high-performance substrate, significantly reducing thermal resistance, which in turn translates to higher system efficiency and lower cooling demands. This results in increased power density and excellent cycling robustness, even under demanding operating conditions. With support for a broad range of topologies and customization options, the EasyPACK CoolGaN module addresses diverse requirements in industrial and energy applications.
The post Infineon expands its GaN power portfolio with EasyPACK CoolGaN power modules for high-voltage applications appeared first on ELE Times.
Vishay Intertechnology 1 Form A Solid-State Relays Offer Continuous Load Current to 5 A in Compact SOP-4 Package
Space-Saving, Industrial-Grade Devices Combine Load Voltages to 60 V With Isolation Voltage of 3750 VRMS and Low Leakage Current of < 1 µA
Vishay Intertechnology, Inc. introduced two new industrial-grade 1 Form A solid-state relays in the surface-mount SOP-4 package. The Vishay Semiconductors VO1401AEFTR and VOR1003M4T combine high continuous load current of 550 mA and 5 A, respectively, with load voltages of 60 V and 30 V, isolation voltage of 3750 VRMS, and low leakage current of < 1 µA typical.
With their high current capability, the devices released are ideal for replacing electromechanical relays, which are susceptible to damaging vibrations, with contactless optical relays that provide robust, vibration-proof switching for higher reliability and a longer service life. In addition, their high isolation voltage allows them to be used in harsh environments.
Offering typical turn-on and turn-off times of 1.3 ms and 0.15 ms for the VO1401AEFTR, and 0.5 ms and 0.1 ms for the VOR1003M4T, the relays will provide fast switching for industrial automation systems and controls; security systems; medical instrumentation; and broadcasting equipment. In these applications, the devices’ compact package saves board space, while their low leakage current translates into higher efficiency by helping to keep the sensitive load on the output side turned off.
The post Vishay Intertechnology 1 Form A Solid-State Relays Offer Continuous Load Current to 5 A in Compact SOP-4 Package appeared first on ELE Times.
Infineon introduces new CoolSET System in Package (SiP) in a compact design for highly efficient power delivery up to 60 W for wide input voltage range
Infineon Technologies AG is launching its new CoolSET System in Package (SiP), a compact, fully integrated system power controller for highly efficient power delivery of up to 60 W at universal input voltage range of 85 – 305 VAC. Housed in a small SMD package, the high-voltage MOSFET with low RDS(ON) eliminates the need for an external heat sink, reducing system size and complexity. The CoolSET SiP supports zero-voltage switching flyback operation, which enables low switching losses and low EMI signature, while also enhancing system reliability and robustness. This makes it an ideal solution for applications such as major home appliances and AI servers. In addition, the controller makes it easier for developers to meet stringent energy standards, supporting future-proof power solutions for modern designs.
The CoolSET SiP integrates a 950 V startup-cell, an 800 V avalanche rugged CoolMOS P7 SJ MOSFET, a ZVS primary flyback controller, a secondary-side synchronous rectification controller, and reinforced isolated communication enabled by Infineon’s proprietary CT Link technology. This high level of integration supports the development of more sophisticated end products by significantly reducing the number of discrete components, lowering the bill of materials, and minimizing PCB space requirements. A comprehensive set of advanced protection features simplifies system integration and allows designers more flexibility to optimize their solutions and enhance the overall user experience.
The post Infineon introduces new CoolSET System in Package (SiP) in a compact design for highly efficient power delivery up to 60 W for wide input voltage range appeared first on ELE Times.
ESG-REBOOT: освіта, інженерія та екологія
У КПІ ім. Ігоря Сікорського відбувся перший ESG-REBOOT: освіта, інженерія та екологія — в єдиній системі відповідальності.
Це перша масштабна подія в межах співпраці з ESG Liga PAEW та Офісом сталих рішень, ініціатором якої став Інженерно-хімічний факультет (ІХФ).
Weekly discussion, complaint, and rant thread
Open to anything, including discussions, complaints, and rants.
Sub rules do not apply, so don't bother reporting incivility, off-topic, or spam.
Reddit-wide rules do apply.
To see the newest posts, sort the comments by "new" (instead of "best" or "top").
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Single sideband generation, Part 2

The generation of single sideband (SSB) signals first came to my attention via ham radio back in the early 1960s. My call was then and still is WA2IBH. The best phonetic I had for that call sign was “WA2 I’ve Been Had” but that’s merely a side note.
Most voice communication through ham radio back then was done by amplitude modulation or AM signals. When you heard someone on the air with an AM signal, the voice quality was usually pretty good. As I recall, the E.F. Johnson Viking Ranger transmitter was thought of as having the very best audio quality. Of course, when you had many signals on the air at the same time with different carrier frequencies, heterodyne squeals were an unpleasant fact of life which often degraded the intelligibility of the person whom you wanted to hear.
Enter into service, SSB.
To demodulate an SSB signal, a receiver needs to reinsert a carrier signal to replace the carrier signal that the sender is NOT transmitting. The resultant sound is intelligible, but the idea of audio quality is a lost cause. A human voice in a demodulated SSB transmission is difficult to linguistically describe. Perhaps it might be thought of as listening to a cross between Donald Duck and Mickey Mouse. A big improvement, though, is that there are no heterodyne squeals. All you hear from multiple signals coming through at the same time are distorted but intelligible voices. This is a MAJOR improvement. However, the acceptance of SSB in ham radio was not universally enthusiastic.
Short-wave receivers produced up through the 1950s would have automatic gain control (AGC) built in, but the response times of the AGC function were not well suited to SSB service. Modern AGC designs have “fast attack and slow decay,” meaning that the receiver gain is reduced very quickly upon arrival of an overly strong signal and that receiver gain is subsequently restored slowly. Since SSB signals have amplitudes that are “spiky,” meaning high peak amplitude to average amplitude ratios, the AGC circuits of these older receivers could be “pumped” by SSB signals, even if the receiver were not tuned exactly to the SSB signal’s exact frequency. Reception of pretty much anything else could and often was very badly affected. Modern AGC control is much better.
Many non-SSB users confronted by AGC pumping incorrectly assumed that SSB users were guilty of “splatter,” the descriptive term for the spectral spread of an overmodulated (> 100%) AM transmission. Derogatory terms such as “splatter sideband” and “silly sideband” were in common use.
Today, ham radio voice communication is dominated by SSB.
John Dunn is an electronics consultant, and a graduate of The Polytechnic Institute of Brooklyn (BSEE) and of New York University (MSEE).
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The post Single sideband generation, Part 2 appeared first on EDN.
Infineon adds EasyPACK CoolGaN power modules for high-voltage applications
Gate driver enables flexible EV inverter design

The STGAP4S galvanically isolated automotive gate driver from ST connects to an external MOSFET-based push-pull buffer to scale gate current capability. This architecture enables control of inverters with varying power ratings, including high-power designs with multiple parallel power switches.
The STGAP4S can deliver gate drive currents in the tens of amperes using small external MOSFETs and handles operating voltages up to 1200 V. It integrates an ADC, a flyback controller, programmable protections, and comprehensive diagnostics. The device is AEC-Q100 and ISO 26262 qualified, supporting system designs up to ASIL D.
Advanced diagnostics in the STGAP4S include self-checks for connections, gate-drive voltages, and internal circuitry such as desaturation and overcurrent detection. Faults are reported via SPI and two diagnostic pins. Protections like active Miller clamping, UVLO, OVLO, desaturation, overcurrent, and over-temperature detection ensure robust designs. Configurable thresholds, deadtime, and deglitch filters—programmable through SPI—enable flexibility while meeting ISO 26262 up to ASIL D.
Now in production, the STGAP4S is available in a SO-36W wide-body DIP, priced from $4.66 each in lots of 1000 units.
The post Gate driver enables flexible EV inverter design appeared first on EDN.
CGD demos ICeGaN in motor drives, data centers and EVs at PCIM
Work in progress Nixie Wrist Watch project!
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Навчальний практикум-тренінг «Монтаж теплових насосів» у рамках проєкту з GIZ
У КПІ ім. Ігоря Сікорського відбувся завершальний день триденного навчального практикуму-тренінгу для тренерів — «Монтаж теплових насосів».
Navitas launches GaNSense Motor Drive ICs for home appliances and industrial drives up to 600W
Partstat and WIN Semiconductors forge strategic partnership
Why is the 2N3904 transistor still up after 60 years?

In the ever-dynamic and fast-moving world of semiconductors, why do some old transistors like 2N3904 keep on going for decades? Bill Schweber takes a closer look at this remarkable premise while analyzing why design engineers still prefer these tried-and-tested devices to reduce risk, cost, and sourcing hassles.
Read the full story at EDN’s sister publication, Planet Analog.
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The post Why is the 2N3904 transistor still up after 60 years? appeared first on EDN.
Nexperia shrinks Schottky footprint with CFP2-HP

Sixteen planar Schottky diodes for automotive and industrial use are now available from Nexperia in compact CFP2-HP packages. These clip-bonded FlatPower (CFP) packages offer a smaller, high-performance alternative to legacy SMA, SMB, and SMC packages, delivering improved heat dissipation while maintaining a compact 3.45 mm² footprint—particularly in space-constrained automotive designs.
This portfolio extension includes eight industrial-grade parts, such as the PMEG6010EXD, and eight AEC-Q101 qualified automotive-grade parts, such as the PMEG4010EXD-Q. The Schottky diodes provide reverse voltages ranging from 20 V to 60 V and average forward currents of 1 A and 2 A.
Rated for junction temperatures up to 175°C, the CFP2-HP package combines an exposed heatsink and copper clip to enhance thermal performance in a small 2.65×1.3×0.68-mm (including leads) form factor. An optimized lead design ensures consistent solder joints suitable for automated optical inspection.
To learn more about Nexperia’s planar Schottky diodes in CFP2-HP packaging, click here.
The post Nexperia shrinks Schottky footprint with CFP2-HP appeared first on EDN.
SiC MOSFETs trim on-resistance and gate losses

Infineon’s 750-V CoolSiC G2 MOSFETs enhance system efficiency and power density in automotive and industrial power conversion. The second-generation G2 technology provides typical on-resistance values up to 60 mΩ, supporting a wide range of applications such as onboard chargers, DC/DC converters, xEV auxiliaries, and solar inverters. A best-in-class RDS(on) of 4 mΩ is available in the top-side cooled Q-DPAK package, which delivers strong thermal performance and reliability.
G2 technology also offers low RDS(on) × Qoss and RDS(on) × Qfr values, reducing switching losses in both hard- and soft-switching topologies, with strong efficiency in hard-switching use cases. Lower gate charge enables faster switching and reduces gate drive losses, improving performance in high-frequency applications.
The 750-V MOSFETs provide a high VGS(th) of 4.5 V and a low QGD/QGS ratio, enhancing protection against parasitic turn-on. They also support gate voltages down to -11 V, offering extended design margins and improved compatibility with other devices.
Samples of the 750-V CoolSiC G2 MOSFETs in Q-DPAK packages, with RDS(on) values of 4 mΩ, 7 mΩ, 16 mΩ, 25 mΩ, and 60 mΩ, are now available for order. For more information, click here.
The post SiC MOSFETs trim on-resistance and gate losses appeared first on EDN.
Module combines triband Wi-Fi 6E with BLE

Murata has begun mass production of the Type 2FY combo module featuring 2.4-GHz, 5-GHz, and 6-GHz Wi-Fi 6E and Bluetooth LE 5.4. Built on Infineon’s CYW55513 combo chipset, the Type 2FY dual-radio module combines a compact form factor with low power consumption to suit space-constrained IoT devices.
The Bluetooth subsystem of the Type 2FY wireless module—supporting BR, EDR, and LE—enables LE Audio, Advanced Audio Distribution Profile (A2DP), and Hands-Free Profile (HFP) for high-quality audio streaming. It delivers PHY data rates up to 3 Mbps for Bluetooth and 2 Mbps for Bluetooth LE. The WLAN subsystem complies with 802.11a/b/g/n/ac/ax standards and achieves PHY data rates up to 143 Mbps. It uses an SDIO 3.0 interface, while the Bluetooth section connects via a high-speed 4-wire UART and PCM for audio data.
Pin-compatible with Murata’s Type 1MW (CYW43455), the Type 2FY offers a drop-in upgrade that requires no hardware redesign. Its compact 7.9×7.3×1.1-mm form factor is made possible by Murata’s proprietary packaging technology. Although based on the Wi-Fi 6E standard, the module limits bandwidth to 20 MHz to reduce cost.
To learn more about the Type 2FY wireless combo module, click here.
The post Module combines triband Wi-Fi 6E with BLE appeared first on EDN.
Rectifiers meet automotive quality standards

Taiwan Semiconductor offers two series of high-voltage rectifiers, both manufactured to AEC-Q101 standards for reliable automotive performance. The fast-recovery HS1Q series provides a repetitive peak reverse voltage of 1200 V, a forward current of 1 A, and a reverse recovery time of 75 ns. The standard-recovery SxY series includes 1600-V rectifiers with forward currents of 1 A (S1Y) and 2 A (S2Y). Both series are also available in commercial-grade versions.
These devices operate within a junction temperature range of -40°C to +175°C and feature a low forward voltage drop and high surge current capability. They are well-suited for bootstrap, freewheeling, and desaturation functions in IGBT, MOSFET, and wide-bandgap gate drivers, particularly in electric vehicles and high-voltage battery systems.
The HS1Q and SxY rectifiers are available from distributors, including Mouser, Arrow Electronics, and DigiKey. Lead time for production quantities is 8 to 14 weeks. Production part approval process (PPAP) documentation is available.
The post Rectifiers meet automotive quality standards appeared first on EDN.
EDA powerhouses align offerings with Intel’s 18A node

The EDA trio—Cadence, Siemens EDA, and Synopsys—was prominent at the Intel Foundry Direct Connect 2025 while lining up AI-driven analog and digital design flows for Intel’s 18A process node. The offerings also included IPs ranging from SerDes to DDR5 to Universal Chiplet Interconnect Express (UCIe).
Next, these EDA outfits inked advanced packaging partnerships by offering workflows for Intel Foundry’s Embedded Multi-die Interconnect Bridge-T (EMIB-T) technology, which combines the benefits of EMIB 2.5D and Foveros 3D packaging technologies for high interconnect densities at die sizes beyond the reticle limit.
Let’s start with EDA flows.
Cadence has certified its RTL-to-GDS flow for 18A process design kit (PDK), which includes the Cerebrus Intelligent Chip Explorer, Genus Synthesis solution, Innovus Implementation System, Quantus Extraction solution, Quantus Field Solver, Tempus Timing solution, and Pegasus Verification System.
Siemens EDA has certified its Calibre nmPlatform sign-off tool and Solido SPICE and Analog FastSPICE (AFS) software tools for 18A production PDK. Likewise, the qualification of Calibre nmPlatform and Solido Simulation Suite offerings for the Intel 18A-P process node is now underway. These EDA tools are also part of the Intel 14A-E process definition and early runsets already available.
Figure 1 Synopsys unveiled an EDA and IP collaboration roadmap with Intel Foundry at the event.
IP and advanced packaging liaison
Cadence has announced a broad range of IPs for the 18A process node. That includes 112G extended long-reach SerDes, 64G MP PHY for PCIe 6.0, CXL 3.0, and 56G Ethernet, LPDDR5X/5 – 8533 Mbps with multi-standard support, and UCIe 1.0 16G for advanced packaging.
Besides IP offerings, Cadence is partnering with Intel Foundry to develop an advanced packaging workflow to leverage EMIB-T technology. This workflow will streamline the integration of complex multi-chiplet architectures while complying with standards.
Figure 2 Cadence is certifying EDA toolsets and IPs for Intel’s 18A process node.
Meanwhile, Siemens EDA has announced the certification of a reference workflow for EMIB-T technology using through silicon via (TSV) technique. It’s driven by the company’s Innovator3D IC solution, which provides a consolidated cockpit for constructing a digital twin. It also features a unified data model for design planning, prototyping, and predictive analysis of complete package assembly.
Synopsys is also employing its 3DIC Compiler to facilitate a reference workflow that enables efficient EMIB-T designs with early bump and TSV planning and optimization. It also features automated UCIe and HBM routing for high quality of results and fast 3D heterogeneous integration. Here, the 3DIC Compiler facilitates feasibility and partitioning, prototyping and floorplanning, and multiphysics signoff in a single environment.
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The post EDA powerhouses align offerings with Intel’s 18A node appeared first on EDN.
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