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Ceva’s RealSpace Elevate is a Microsoft-certified Windows Audio Processing Object (APO) that enables spatial audio for PC gaming headsets. Unlike OS-level solutions that offer limited differentiation or branded third-party applications that restrict customization, the production-ready APO gives OEMs full control over performance and product identity. This includes customizable tuning and presets optimized for gaming and entertainment use cases such as music, movies, and podcasts.

Leveraging Ceva’s RealSpace spatial audio technology, the APO integrates precise sound localization and natural externalization within the Windows APO framework for seamless deployment on Windows PCs. It is optimized for gaming headset use cases, combining rich entertainment audio with competitive gameplay enhancements.

RealSpace Elevate supports 7.1 multichannel rendering with pinpoint accuracy and a realistic soundstage. Gaming-focused enhancements include controls to highlight critical in-game sounds such as footsteps or gunshots.

The licensable APO is available now. 

RealSpace Elevate product page  

Ceva

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A 3D direct ToF LiDAR module, the VL53L9CX from STMicroelectronics offers 2.3k-zone resolution for low-compute edge AI systems. This compact all-in-one module integrates a SPAD array, post-processing SoC, two VCSELs, a BCD VCSEL driver, infrared filters, metasurface optical elements (MOEs), and PMIC. It enables high-resolution spatial awareness in robotics, industrial automation, smart buildings, and healthcare.

The VL53L9CX provides 2,268 ranging zones (54×42) across a wide 55°×42° field of view, allowing detailed 3D depth mapping and precise detection of small objects, contours, and edges. With stacked BSI SPAD sensors and MOEs, the module delivers fast, accurate ranging from less than 5 cm to 8.8 m with up to 1% accuracy and frame rates up to 100 fps.

Dual-scan flood illumination reduces motion artifacts and eliminates dead zones while enhancing small-object detection. It also combines 2D infrared and 3D depth imaging, simplifying post-processing and enabling edge AI applications to run on small MCUs.

The VL53L9CX is supplied in a miniature reflowable package. Mass production is scheduled for July 2026.

VL53L9CX product page 

STMicroelectronics

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The R&S PR300 portable monitoring receiver provides 125 MHz of real-time bandwidth and a scanning speed of more than 500 GHz/s. It is designed for field-based spectrum monitoring, interference hunting, high-speed signal detection, and direction finding (DF) with a directional antenna in complex RF environments.

Covering 8 kHz to 8 GHz, the PR300 supports segmented panorama scanning, embedded spectrum analysis, and time-gated direction finding. The frequency range extends to 20 GHz or 33 GHz when used with the HE400DC or HE800-DC30 handheld directional antennas, respectively. With the ADDx07 series compact DF antenna, the system achieves direction-finding accuracy better than 1° from 9 MHz to 20 GHz.

Gapless capture and analysis of wideband communication signals support applications such as radio monitoring in accordance with ITU recommendations, QoS verification, and interference hunting in 5G and LTE networks. The PR300-ZS time-domain measurement option provides simultaneous time-domain data and a corresponding time-gated frequency spectrum, useful for analyzing burst, intermittent, and transient signals.

For more information, visit the PR300 product page.

Rohde & Schwarz  

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D-Wave Quantum has announced a gate-model quantum computing simulator for error-aware programming and algorithm development. The cloud-based simulator provides tools for modeling quantum processor behavior, error detection, and real-time control. It supports up to 21 qubits, ideal and hardware emulation modes, and integration with D-Wave’s Ocean SDK.

Built around D-Wave’s dual-rail technology, the simulator gives developers greater visibility into errors so they can design applications and workflows that reflect real processor behavior. It also enables Monte Carlo simulation of real-time quantum system dynamics, development of error-correction routines, and evaluation of advanced error-correction approaches based on dual-rail qubits.

D-Wave plans to offer quantum development bundles that provide access to its forthcoming gate-model quantum simulator and quantum computing systems. Available in Starter and Premium tiers, the bundles include monthly usage allocations and technical guidance from D-Wave. Pricing is available upon request.

The simulator is scheduled to be available through D-Wave’s Leap cloud platform in September 2026. Learn more and request future access here.

D-Wave Quantum 

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Qualcomm’s Snapdragon Reality Elite spatial computing processor delivers 48 TOPS of AI performance for video-see-through (VST) headsets and tethered optical-see-through (OST) glasses. The processor can run large vision models (LVMs) and large language models (LLMs) locally, reducing dependence on cloud-based processing for XR applications.

Snapdragon Reality Elite supports photorealistic avatars using Gaussian Splatting, LLM-based agents, and real-time, LVM-driven object generation. These AI capabilities enable more context-aware XR experiences with natural interaction while improving head and hand tracking in see-through devices.

According to Qualcomm, the Snapdragon Reality Elite provides 60% higher GPU performance, up to 30% better CPU performance, and up to 160% greater NPU performance than the Snapdragon XR2+ Gen 2. It also enables up to 20% longer battery life at the same workload and reduces chipset temperature by up to 12°C under load. The increased power efficiency allows the design of lighter, cooler headsets and glasses that can be worn comfortably for extended periods.

Support for visuals up to 4.4K per eye at 90 fps enables sharper detail, smoother motion, and improved color fidelity. VST enhancements enabled by IP hardening, including the EVA block, reduce latency and improve image quality.

For more information, visit the Snapdragon Reality Elite product page.

Qualcomm Technologies 

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Artificial intelligence (AI) is accelerating semiconductor innovation at a pace that is forcing a rethinking of conventional production test strategies. The rapid scaling of graphics processing units (GPUs), AI accelerators, and heterogeneous compute architectures is increasing not only device complexity, but also the amount of test content required to validate performance, reliability, and quality across the manufacturing flow.

As AI infrastructure investments continue to expand, semiconductor manufacturers are building increasingly sophisticated devices that combine massive transistor counts, advanced packaging, high-bandwidth memory (HBM), chiplet architectures, and emerging co-packaged optical (CPO) interfaces. These devices are redefining the relationship between design, validation, and production test.

The result is a new test paradigm in which test content, infrastructure, and analytics are distributed dynamically across multiple insertions—from wafer sort through system-level test (SLT)—to balance cost-of-test, defective-parts-per-million (DPPM), and time-to-market objectives.

 

AI devices driving a step change in test requirements

The transition from monolithic devices to heterogeneous multi-die systems has substantially increased the burden on automated test equipment (ATE). AI processors now incorporate far more compute engines, memory bandwidth, and power-delivery complexity than previous generations of high-performance devices.

At the same time, traditional transistor scaling no longer delivers the same gains once associated with Moore’s Law. To continue improving system performance, designers are adopting More-than-Moore integration strategies that combine chiplets, 3D packaging, integrated voltage regulation, and advanced interconnect technologies within increasingly dense package architectures. These changes are producing several cascading effects on tests.

First, scan and functional test workloads are growing dramatically as transistor counts increase. Modern AI devices require extremely large volumes of scan vectors that must be delivered at gigabit-per-second speeds through either massively parallel digital channels or high-speed serial interfaces such as PCIe and USB.

Second, power requirements are rising rapidly. Device power supplies must now support kiloamp-class current delivery while maintaining tight regulation and accuracy under highly dynamic loading conditions. Flexible power architectures capable of extensive channel ganging are becoming increasingly important as final-test power envelopes continue to climb.

Thermal management is becoming equally critical. AI devices entering production are expected to push package-level power dissipation into multi-kilowatt ranges, making active thermal control essential throughout the test flow. In advanced environments, thermal systems are increasingly paired with predictive analytics capable of anticipating thermal excursions before they occur, enabling proactive cooling and tighter junction-temperature management.

Advanced packaging complicates multisite test

Migration toward larger 2.5D and 3D packages is also changing the physical realities of production test. As package sizes expand to accommodate more chiplets, HBM stacks and photonic components, device handling and multisite efficiency become more difficult to optimize. Larger sockets consume increasing amounts of device-under-test (DUT) board real estate, constraining routing resources and limiting tester scalability.

In parallel, manufacturers are moving toward larger tray formats carrying fewer devices per tray because of package dimensions and handling constraints. These shifts reduce some of the traditional efficiencies associated with high-parallelism production environments.

The addition of photonic and CPO technologies introduces another layer of complexity. Optical interfaces require integrated electro-optical validation across multiple stages of manufacturing, extending test coverage well beyond conventional electrical characterization. As a result, optical instrumentation is increasingly being introduced at wafer probe, optical-engine test, final package test, and SLT insertions.

Test engineering becoming more software- and data-centric

The growing complexity of AI devices is changing not only hardware requirements, but also the nature of test engineering itself. In other words, engineering organizations are under pressure to accelerate bring-up, reduce debug cycles, and maintain quality targets despite rapidly increasing test content volumes. This is driving tighter integration between design, silicon validation, and manufacturing teams.

As a result, AI-assisted software tools are beginning to play a larger role in test-program generation, debug optimization, and adaptive workflow management. Real-time analytics platforms can now aggregate data across multiple insertions, enabling faster correlation of failures and more intelligent allocation of test coverage throughout the production flow.

In these environments, test content is no longer statically assigned to a single insertion. Instead, coverage increasingly shifts throughout the flow depending on where defects can be detected most efficiently and economically. This distributed approach to test is becoming essential as AI devices scale toward trillion-transistor complexity.

Shifting test left reduces packaging risk

One major trend is the movement of more test content earlier in the manufacturing flow. For advanced AI devices, packaging costs now represent a substantial portion of total product cost because of technologies such as HBM and chip-on-wafer-on-substrate (CoWoS) integration. Packaging defective die into expensive multi-die assemblies can significantly increase material waste and reduce yield.

To mitigate this risk, manufacturers are pushing more coverage to wafer-level and die-level test insertions to improve known-good-die confidence before assembly. Figure 1 illustrates how test distribution increasingly spans the entire workflow, with tighter interaction between design, validation, and production environments.

Figure 1 Test distribution has expanded to accommodate growing need for test across the manufacturing ecosystem—beginning with silicon validation and extending through system-level test. Source: Advantest

This shift-left strategy (Figure 2) includes broader scan coverage and expanded fault modeling at speed testing, and increasingly system-aware functional validation at the die level. Some workflows also incorporate calibration, trimming, and memory repair operations prior to package assembly.

Figure 2 Shifting test content left enables more coverage at wafer and die test stages to improve known-good-die screening before package assembly. Source: Advantest

In more advanced implementations, active thermal control capabilities are also migrating closer to singulated-die test stages. The objective is straightforward: identify marginal or defective components before they enter expensive advanced-packaging flows.

System-level test expanding

At the same time, other forms of coverage are shifting later in the process. As devices become more heterogeneous and application-specific, certain failure mechanisms emerge only under realistic operating conditions involving software execution, thermal loading, timing interactions, or high-bandwidth traffic patterns.

These conditions are often difficult—or impossible—to replicate during traditional structural or functional test insertions. Consequently, SLT is becoming increasingly important for AI and HPC devices. System-level environments can expose defects associated with workload execution, protocol interactions, and real-world operating states that are not observable during earlier production stages.

New approaches, including scan-over-PCIe methodologies and highly parallel SLT architectures, are helping manufacturers improve coverage while attempting to control the significant test times associated with these environments. Figure 3 illustrates the corresponding shift-right strategy.

Figure 3 Shifting test content right enables additional test coverage to be executed after packaging to further reduce DPPM before shipment. Source: Advantest

Real-time analytics enabling adaptive test distribution

The increasing fragmentation of test insertions is creating demand for tighter orchestration across the production floor. Modern test infrastructures are evolving toward highly connected environments in which data streams continuously between validation, wafer sort, final test, and SLT operations. Real-time analytics platforms can then use this data to optimize insertion decisions, adapt test limits, and improve yield-learning cycles.

GPU-accelerated edge inferencing and AI-based decision engines are also enabling faster adaptive responses during production. In some cases, computation can be offloaded from the tester itself to remote compute infrastructure, allowing more sophisticated analytics without compromising throughput.

This level of coordination requires consistent software frameworks and portable test content capable of moving seamlessly between insertions and platforms. So, shared execution environments and unified debug tools are becoming increasingly important as manufacturers attempt to reduce engineering overhead while accelerating deployment.

Optical test adds new workflow stages

CPO and photonic integration introduce additional challenges because optical functionality must be validated alongside traditional electronic behavior. Unlike conventional semiconductor devices, photonic systems often require multiple dedicated insertion points throughout manufacturing. These may include photonic wafer test, dual-sided probing of electronic and photonic die, optical-engine characterization, and additional packaged-module validation after integration with ASICs.

As with electrical tests, much of this optical validation is shifting earlier in the flow to ensure known-good optical engines prior to final assembly. However, full electro-optical verification often still requires additional socketed final-test and SLT insertions after system integration.

Figure 4 highlights how optical test introduces additional insertion points spanning photonic wafer test, optical-engine validation, final package test, and SLT.

Figure 4 For testing CPO devices, test content shifts left for three insertions and right for final socketed device test. Source: Advantest

Test distribution is becoming a strategic optimization problem

AI is transforming semiconductor tests from a relatively linear production step into a highly distributed optimization challenge involving power, thermal management, data analytics, packaging economics, and workflow orchestration. Meeting future quality and throughput requirements will require closer collaboration across the semiconductor ecosystem, including design teams, ATE suppliers, packaging providers, and system integrators.

As AI devices continue scaling in complexity, test infrastructure must evolve from traditional defect screening toward intelligent, adaptive validation environments capable of making real-time decisions across the manufacturing flow. In that sense, the future of semiconductor test may depend as much on data movement and workflow intelligence as on the tester hardware itself.

Fabio Pizza is business segment manager at Advantest Europe.

Related Content

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• Optimizing Automated Test Equipment for Quality and Complexity
• Advanced verification: unlocking the door to a new era of AI chips
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• From Defect Images to Die Prediction: How Intel Is Scaling AI in Advanced Manufacturing

The post How AI is driving a new paradigm in test distribution appeared first on EDN.

An only slightly less simple followup circuit also ratios sensor capacitance to a reference capacitor to measure micrometers…this time linearly.

A few weeks ago, Design Ideas published a simple circuit of mine that provides an analog interface to capacitive position sensors. Figure 1 shows that basic design with its separate complementary outputs: Out and –Out.

Wow the engineering world with your unique design: Design Ideas Submission Guide

Figure 1 The U1a and U1b cross-coupled Schmidt trigger timers form a ~1MHz RC multivibrator. The Tsense pulse width is inversely proportional to sensor displacement (Tref/Tsen= Cref/Csen = d).

Figure 2 shows the “Simple Simon” method it offered for acquisition of the sensor position signal: passive RC averaging of the Tsense pulse train.

Figure 2 Passive RC averaging of the Tsense output yields the analog position output.

The resulting analog output, as shown in figure 3, provides good range and resolution but is nonlinear.

Figure 3 This graph shows the sensor performance when Out is connected to a 12bit ADC using +5V for its reference. The black curve (left axis) equals the plate separation (d) in millimeters. The red curve (right axis) equals the ADC lsb resolution in micrometers.

So, I got to thinking about linearization and the advantages it would provide, and wondering how tough it would be.  It turned out to be not that difficult. 

Figure 4 shows the resulting interface with added linearization circuitry.  Just an added opamp, three resistors, and two non-critical caps did the trick.  Here’s how it works.

Figure 4 Averaging integrator A1 linearizes the displacement sensing response.  R5 is shown as a precision type, albeit just out of force of habit.  It, like the ON resistances of U2’s switches, actually cancels out.

Each capacitance measurement cycle, the 500ns Tref pulse causes 4066 switch U2d to deposit a quantum of charge on integrator A1’s summing node of Qref = Tref/R5.  Meanwhile the sensor-capacitance proportional Tsen pulse subtracts Qsen = Tsen(Vout – 1)/R5.  The charge balance is forced by A1 to maintain Qsen = Qref, therefore Tsen(Vout – 1)/R5 = Tref/R5, and Vout – 1 = Tref/Tsen = Cref/Csen = d. Note that R5 magically (?) disappears from the math.

Figure 5 shows the straight-as-an-arrow-in-zero-gravity result.

Figure 5 In this graph of the enhanced circuit results, the black curve equates to the sensor readout d in mm, with red at a constant 1 mV per micron resolution.

Stephen Woodward‘s relationship with EDN’s DI column goes back quite a long way. Over 200 submissions have been accepted since his first contribution back in 1974.  They have included best Design Idea of the year in 1974 and 2001.

Related Content

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• Capacitor matchmaker
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• From gap to signal: Non-contact capacitive displacement sensors
• Simple circuit interfaces differential capacitance sensor

The post Capacitive position sensor with linearized output appeared first on EDN.

In high-volume consumer electronics, the margin between a feature and a failure mode is increasingly narrow.

As the architecture of form-factor constrained devices becomes more tightly integrated, the traditional modularity of hardware systems breaks down. Thermal behavior, RF performance, mechanical tolerances, and power delivery are no longer independent domains because small sub-system shifts cascade across the entire system.

When the thermal envelope of a system-on-chip (SoC) directly impacts the signal integrity of a nearby 5G antenna, or when a mechanical tolerance stack-up in a camera module creates parasitic capacitance on a display flex, validation can no longer be a post-design activity.

Today, the complexity of modern hardware validation is a direct consequence of early architectural decisions. As highlighted in McKinsey’s analysis on handling technical complexity, upfront product architecture misjudgements inevitably compound into severe downstream bottlenecks during the integration phase.

Cost of coupling: Architectural debt

In loosely coupled systems, validation scales linearly. Components can be tested independently, and integration risk is bounded. However, in tightly coupled systems, validation scales exponentially. For instance, in a loosely coupled architecture where the display, power management IC (PMIC), and RF modem operate within encapsulated boundary interfaces, validating state transitions across 4 operating modes requires an additive test matrix, totaling 12 unique test permutations.

However, when these 3 subsystems are tightly coupled, where transient voltage drops from a 5G RF burst could force dynamic updates to the display’s refresh logic and PMIC power rails, the test matrix explodes up to 48 unique test permutations for the same feature set, a 4x increase in test overhead.

Decisions to integrate a new module, compress an existing subsystem, or optimize the overall system introduce a new set of interdependencies to be de-risked. For example, a custom-design ASIC may require entirely new silicon-level validation infrastructure in collaboration with the chip manufacturer before meaningful system integration can begin.

In parallel, a complex PCB stack-up can increase the risk of parasitic coupling and desense, requiring exhaustive EMI testing. Furthermore, high-density packaging may compress thermal margins, necessitating sophisticated workload throttling to maintain performance metrics.

When architecture teams prioritize power, performance, and area (PPA) without explicitly accounting for validation and verification, they incur architectural debt. This simply refers to an acceptance of long-term trade-offs (the debt) in exchange for immediate product architecture wins.

This debt is often paid off during engineering validation builds and volume ramp. Gamliel and Barron (2026) empirically analyzed high-complexity new product introduction (NPI) environments and found that early organizational and architectural blind spots are the primary upstream drivers that later materialize as volatile downstream ‘non-quality costs,’ directly yielding schedule deviations, material waste, and collapsed margins during volume manufacturing transitions.

Figure 1 In loosely coupled systems, validation effort grows linearly with added complexity. In tightly coupled systems, interdependencies cause exponential growth. The gap is architectural debt. Source: Author

Supplier co-development: Moving handshake upstream

At flagship scale, global supply chain provides co-engineering support in addition to its legacy logistics execution function. Supply chain is tightly integrated with system architecture. Here, a common failure mode in NPI treats suppliers strictly as a black box expected to deliver components to fixed specifications.

Meanwhile, in tightly coupled systems, critical risks are bound to emerge from sub-components within the system. Mitigating these risks require moving validation alignment upstream and creating an earlier validation handshake during system architecture. This includes:

• Joint validation planning between system teams and suppliers to align on defining success at component and system levels.
• Infrastructure sharing where suppliers are provided with realistic system conditions, enabling them to test and de-risk components in system-level simulation models.
• Transparent yield modeling between system teams and suppliers to accommodate the supplier’s manufacturing variance in system design.

If this handshake happens later, validation becomes reactive. If earlier, architecture becomes more robust and more tolerant to real-world variations.

Validation infrastructure as a design tool

In leading programs, the minimum viable product (MVP) for validation comes much earlier than the first system hardware. Validation infrastructure is set up to serve as a de-risking tool prior to the first prototype build. This infrastructure includes the employment of virtual systems that enable high-fidelity simulations for validating system behavior in digital twin environments.

Digital models can uncover thermal coupling, signal integrity issues, and power interactions early in the design cycle. Modular breadboards and development platforms also enable early development of firmware, software, and tests while final mechanical enclosures are still being designed.

Additionally, pre-silicon emulation allows teams to explore system behavior early in the loop with accelerated simulation layers, even before physical prototypes exist. Pre-silicon environments allow software and power-state validation before tape-out. This is particularly essential because silicon tape-out schedules often come in advance of overall system readiness.

By the time the first “steel-tooled” builds are available, most integration risks should already be understood, bounded, or mitigated. Programs that rely on physical builds to discover system behavior are effectively deferring architectural decisions into the most expensive phase of development.

However, even with the right infrastructure, organizations still need a decision framework to ensure validation is treated as a first-class architectural constraint. That’s where governance comes in.

Governance: Where architecture and validation converge

Enforcing validation as a first-class architectural priority is more of a leadership mandate than a technical hurdle. System engineering program managers and technical leaders must establish the structural authority to elevate validation readiness to a non-negotiable, first priority directive within early architectural decision-making.

When new features are proposed, the validation path required to support them must also be considered. If a design introduces dependency on new validation infrastructure that cannot be developed within the program timeline, an architectural risk and debt has just been introduced.

Validation should be shifted from a milestone to a gating function. Architectural reviews should explicitly evaluate validation complexity, infrastructure readiness, and integration risk alongside performance and cost. Below is a simple governance checklist:

• Is the validation path defined before architecture sign-off?
• Are suppliers’ validation plans aligned with system-level requirements?
• Is there a rollback option if validation reveals unmanageable complexity?

Without this shift, teams unintentionally accept risk that will surface later as schedule slips, yield instability, or late-stage redesign.

Figure 2 With making validation a gating function, every architectural decision must include a credible validation plan before approval. Source: Author

From validation to architecture

As systems become more integrated, the relationship between architecture and validation becomes inseparable. Validation is no longer the mechanism that ensures a design works. It’s the lens through which architectural risk is exposed.

Organizations that recognize this shift can realize design systems that are inherently more testable, more manufacturable, and more predictable at scale. And those that don’t, continue to discover risk at the point where it’s most expensive to resolve.

When you sit in an architecture review next time, ask one question before approving any new feature: ‘What is the validation path, and is it ready today?’ If the answer is anything but ‘yes,’ you are already in debt.

Ayokunle Oni is a system engineering program manager at Apple, where he helps coordinate the iPhone hardware design and engineering process across cross-functional teams. He specializes in system integration and validation and has led complex engineering programs from concept through production, working closely with global manufacturing and vendor partners.

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• Design-Stage Analysis, Verification, and Optimization for Every Designer

The post Relationship between architecture and validation in system design appeared first on EDN.

Here’s a neat and novel way of using a long-tailed pair to drive not just two but three LEDs.

As everyone knows, rainbows always have pots of gold at their ends. This Design Idea reverses that, starting with a pot (no gold, alas) and ending with a rainbow.

Wow the engineering world with your unique design: Design Ideas Submission Guide

Bi-color LEDs can be useful animals for indicating circuit balance or battery condition, and the common-cathode types are easily driven with a long-tailed pair, with various proportions of red and green giving oranges and yellows. Tri-color (RGB) types, capable of producing a much wider spectrum, usually need three separate drive sources.

So what happens if we drive drive the red and blue LEDs with a modified long-tailed pair, adding in the green as some function of the other two? Read on to find out.

Figure 1 shows the first attempt.

Figure 1 The red and blue LEDs are driven by a long-tailed pair and controlled by pot (potentiometer) R4, whose wiper voltage varies according to its position and is used to control the green LED’s drive, producing a decently wide spectrum.

Figure 2 gives plots of the three LED currents as calculated by LTspice, which did most of this Design Idea’s heavy lifting. When pot R4’s wiper is at either end of its travel, Q1 or Q2 will be fully on and the voltage across R5 will be high (~3 V). When it’s centered, Q1 and Q2 and thus the red and blue LEDs will be largely off, but the top of R5 will fall to ~1.7 V. That 3 V is enough to hold the Darlington-pair current source Q3/4 off, while reducing it towards 1.7 V gently turns it on, proportionately driving the green LED.

Figure 2 This graph plots the LED currents against pot rotation.

This result is optimized, meaning it’s the best that Figure 1 can do, but is still rather unsatisfactory because the drives for intermediate colors—oranges, lemons, and the interesting cyans and turquoises—are badly matched, giving rather sludgy shades compared with the pure ones. Breadboarding confirmed the problem.

Take two

Some thought and a rearrangement of the circuit gave Figure 3.

Figure 3 Rearranging the circuit and adding an op-amp to drive the green LED gives better, more linear control of the LED currents.

The pot now gives a lower, more linear, drive to Q1/Q2, the green-controlling voltage being picked off from the tail resistor R1. Obviously, the voltage across R1 is at a maximum with the pot at either extreme and falls to near zero with the pot centered, when red and blue LEDs are off. A1 amplifies that voltage and drives the green LED through R7.

Figure 4 shows the sim plot, which implies that it should work much better when built…

Figure 4 The response of the revised design has more linear curves, giving a smoother spectrum.

…as indeed it does! Owing to brightness mismatches in my 10 mm diffused LEDs (common to most tri-color types) I had to drop the green drive by increasing R7 to 1k2. That drive is also affected by LED1_G’s forward voltage; turning A1 into a proper current source worked well but added more components and didn’t look any better. After fixing R7, the brightness was fairly constant over the whole available spectrum.

A rainbow, or only a portion thereof?

Ah, that weasel word “available”! This can never quite match a real rainbow or other white-light spectrum because the deepest reds and the furthest indigos and violets are outside its range—even rainbows have rather a limited palette compared with a full RGB mix. Swapping the LEDs around gives some interesting spectra (to use the word loosely) in other parts of the chromaticity diagram.

A digital departure

While the basic analog circuit may find applications where three interdependent values need to be controlled by a single pot, there is a better way to drive LEDs like this: use a micro that can read the voltage tapped from a pot and generate appropriate PWM signals to drive the LEDs, perhaps indirectly should you need kilo-lumen rainbows. This approach would also allow direct voltage control of the effects.

I have some solar-powered garden lights that use this principle to span the whole (again, “available”) RGB gamut, using what looks like my my favorite PIC 12F1501 nanocontroller containing a mere 64 bytes of RAM, but more peripherals than pins. Internal demons crank three virtual pots up and down, although low-powered operation means a low and flickery PWM rate. Time to put on the coding hat—waterproof, because rainbows imply rain—and have some digital fun doing it properly.

—Nick Cornford built his first crystal set at 10, and since then has designed professional audio equipment, many datacomm products, and technical security kit. He has at last retired. Mostly. Sort of.

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The post A pot of many colors appeared first on EDN.

Helen Duncan’s father took her to a trade show in London when she was 10 years old. She was fascinated by watching CNC machines make large mechanical parts without human involvement. Her father worked in mechanical engineering as a skilled toolmaker and later as an estimator, and he encouraged Helen to help him with car maintenance.

Helen Duncan is CEO of Blueshift Memory, a Cambridge, England-based design outfit that optimizes memory architecture to more efficiently handle large datasets and time-critical data. Its Cambridge Architecture for stored-program machines is designed to replace the current modified Harvard architecture and to overcome the traditional constraints of the von Neumann bottleneck.

Helen was talking to EDN on the eve of “International Women in Engineering Day,” which is celebrated on 23 June this year. When asked what motivated her to enter the engineering world, she pointed to physics being one of her favorite subjects in high school. “When we had to make an electric motor from scratch in a practical lesson, mine was the only one in the class that worked,” she recalled. “I was thrilled by this.”

At 13, Helen decided that electrical and electronic engineering was what she wanted to study. The more some of her teachers tried to discourage her, the more determined she became to pursue that course. “My wonderful physics teacher, Mr. Wood, a Star Trek fan, was unfailingly supportive though,” Helen acknowledged.

In the field

Helen joined the workforce in the late 1970s when only 1-2% of electronics engineers were women. “With a good degree, I had a choice of several jobs, and I accepted a position as an R&D engineer with Plessey, working on RF and microwave projects for both defense and commercial applications,” she told EDN.

Over there, direction-sensing Doppler radar modules for automatic door openers were an early design project. Later, she became a product engineering manager and hence the design authority for all the company’s microwave source products, including two mmWave subsystems for airborne radar. During those days, there was only one other female engineer working alongside Helen: a Turkish lady a few years older than her, who had a PhD from Oxford University.

Figure 1 Helen Duncan began her design work on RF and microwave projects for defense and commercial applications.

By the mid-1980s, Plessey had recruited several new graduate engineers, and surprisingly, women then made up around 25% of the engineering department, much more than the national average, which was still less than 10% at that time. “I like to think that, as I was a member of the interview panel, they were encouraged to see me as a role model who was already in a management position,” Helen recounted.

Mistaken as a caterer

When asked about the challenges of being a minority in those early days and the advantages as well, Helen said she was incredibly lucky to have some very supportive managers. “Within the company, I was unfailingly treated with respect.”

However, sometimes it was more of a problem with outsiders meeting her for the first time. Helen recalled a senior Royal Air Force officer visiting with a defense procurement team; he mistook her for a member of the catering staff, but then instantly recognized his mistake when she stood up to give a presentation.

When asked for a piece of advice she could give to young female engineers entering the electronics industry, Helen said: Believe in yourself and your abilities, and don’t allow others to undermine you or try to mansplain. “Always remain open to any opportunities that may come along, as your career may not always take the course you would expect,” she added.

Figure 2 EDN spoke with Helen Duncan, CEO of Blueshift Memory, on the eve of the “International Women in Engineering Day,” observed on June 23, 2026.

Career advice for female engineers

EDN concluded the talk with Helen by asking her which areas and disciplines female engineers should consider for long-term career prospects. “In general, I would say that no disciplines are off limits for female engineers,” she said. “However, it can be easier to progress in some of the areas that require better communication skills or a more consultative management style.”

She recalled her career trajectory over the years: she has worked in marketing at both Plessey and Rohm, and then in journalism as editor-in-chief of Microwave Engineering. “I have also been a semiconductor market analyst, a technical conference organizer, and a marketing consultant,” she said. “And I managed some of these roles concurrently.”

Most recently, Helen was headhunted for a marketing role at Blueshift Memory and later became CEO. Blueshift targets its smart memory architecture at CPU vendors, AI chip companies, and memory manufacturers; it can be used in combination with GPUs or AI accelerators, or anywhere the von Neumann bottleneck is a problem.

Figure 3 Blueshift Memory appointed Helen Duncan as its CEO in October 2024.

My career has been full of surprise opportunities and unexpected role changes, but it’s been an exciting journey,” she concluded. “And if I were starting today, I wouldn’t change anything.” That’s quite a career statement.

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The post Women in engineering: Helen Duncan’s journey from design engineer to CEO appeared first on EDN.

High power density power-supply modules based on gallium nitride (GaN) devices are core components in the automotive, industrial and data-center sectors. As their integration level and power density continue to rise, the issue of dissipation of concentrated internal heat becomes increasingly prominent. Device overheating leads to thermal failure and degrades system reliability; therefore, sound thermal design is of paramount importance.

Thermal resistance analysis and power-loss calculations form the theoretical foundation of thermal design. The thermal resistance (RQJA) of a complex power system represents a coupling of the thermal resistances of numerous components, however, making it difficult to calculate precisely using theoretical formulas alone. Thermal simulation software can directly yield the coupled RQJA of the system and rapidly identify a significant operating condition – the maximum power dissipation sustainable at a given ambient temperature – thereby providing precise data guidance for thermal designs. Figure 1 shows the simulation of temperature distribution of a GaN-based power-supply system using Ansys Electronics Desktop (AEDT) Icepak software. By referring to the temperature color scale on the left, we can intuitively observe the temperature distribution and heat dissipation status of different areas based on their colors.

Figure 1 This simulation of the temperature distribution of a GaN-based power-supply system uses Ansys’ Electronics Desktop Icepak software. Source: Texas Instruments

Understanding conduction, convection and radiation RQJA

Heat transfer in a power supply occurs in three forms: conduction, convection and radiation. Thermal resistance is the core parameter for characterizing the ease or difficulty of heat transfer. Within a power supply, heat generated by semiconductor chips is transferred layer by layer through the package, solder joints, printed circuit board (PCB) copper traces, thermal interface materials and heat sinks – a process that constitutes classic thermal conduction but requires direct physical contact between materials. Equation 1 gives the thermal conduction resistance as:

where L is the length of the conduction path, k is the thermal conductivity, and A is the cross-sectional area of heat transfer.

Once heat reaches a material surface, it is transferred to the surrounding air. Taking a heat sink as an example, its fins transfer heat to the adjacent air, which rises upon heating to form natural convection, or is driven by a fan for forced convection cooling. Convective thermal resistance represents the resistance to heat exchange between a solid surface and a cooling medium, expressed in Equation 2 as:

where h is the convective heat-transfer coefficient and A is the convective heat-transfer surface area.

In addition, heat radiating from the enclosure and heat sink rises toward cooler surrounding walls or the ambient environment. Particularly under natural cooling conditions with a high temperature rise, radiated heat can account for 20% to 30% or even more of the total heat dissipation and therefore requires attention. Equation 3 gives the radiative heat flux as:

where ε is the surface emissivity, σ is the Stefan-Boltzmann constant, A is the radiating surface area, Ts is the absolute temperature of the solid surface, and Tsurf is the absolute temperature of the surrounding ambient walls.

In a practical power-supply thermal design, the three conduction, convection and radiation modes of heat transfer occur simultaneously and are mutually coupled: heat from the chip first reaches the heat sink by conduction and then flows into the environment from the heat sink’s surface by convection and radiation. Thoroughly understanding their physical meanings and governing equations is the foundation for performing thermal design and estimating RQJA.

Calculating MOSFET and magnetic component power losses as heat sources

The heat sources in a power supply originate from the power losses of its core devices, which constitute the fundamental input to thermal design.

The losses of a GaN metal-oxide semiconductor field-effect transistor (MOSFET) consist primarily of conduction losses and switching losses. Conduction loss (Pcond) is the loss produced by the root-mean-square (RMS) drain current flowing through the on-state resistance during conduction, calculated using Equation 4:

Equation 5 and Equation 6 calculate the turnon (Pon) and turnoff (Poff) losses of the MOSFET, respectively:

where VDS is the drain-to-source voltage before turnon or after turnoff; tfv and tri are the drain-to-source voltage fall time and current rise time during turnon; fsw is the switching frequency; and trv and tfi are the drain-to-source voltage rise time and current fall time during turnoff. Equation 7 expresses the total losses of each MOSFET as:

The losses of magnetic components such as transformers and inductors are the sum of core losses and winding losses. Core losses (Pcore) comprise hysteresis losses and eddy current losses, while winding losses (Pcoil) comprise DC losses and AC losses, making it one of the primary heat sources in high-frequency power supplies. Equation 8 and Equation 9 are the relevant expressions:

where PCV is the volumetric core loss, Ve is the effective core volume, RDC is the DC winding resistance, Icoil(RMS) is the RMS winding current, and RAC is the AC winding resistance.

Using Icepak simulation to extract RΘJA and determine the maximum current and temperature limits

The RΘJA of a complex power system is difficult to solve precisely through analytical methods. Icepak, a thermal simulation software package for electronic equipment from Ansys, enables system-level modeling and thermal field solving, allowing you to directly obtain the total RΘJA from simulation results, thereby compensating for the limitations of theoretical calculations.

The Icepak thermal simulation workflow comprises three broad steps:

• Model construction, which retains the heat-generating components and thermal-management structures (including chips, PCBs, magnetic components, heat sinks and enclosures); assigns the corresponding material thermal parameters; and generates the mesh.
• A boundary condition setup that applies theoretically calculated device losses as heat sources and specifies the ambient temperature, air-domain boundaries and convection mode.

Solution and output: after iterative solving, the Icepak tool obtains the temperature field distribution and junction temperatures of important devices, which it then uses to compute the total RΘJA along with the heat dissipation path from chip to ambient. Equation 10 is the formula for RΘJA:

where Tj is the chip’s junction temperature, Ta is the ambient temperature, and Ploss is the chip’s power dissipation.

After obtaining RΘJA through simulation, Equation 11 is the fundamental heat-transfer equation:

Applying this formula determines the most significant operating conditions of the power supply, yielding both the maximum permissible power dissipation at different ambient temperatures and the maximum safe ambient temperature at the rated power dissipation.

Here is an example. As shown in Figure 2, under a certain working condition, the GaN device’s power consumption is 1.16W, the ambient temperature is 70°C, and the simulation results show that the chip’s temperature is about 95°C. According to the thermal resistance formula, RΘJA is 21.55°C/W.

Figure 2 The temperature distribution of chips and the PCB they’re mounted on commonly varies. Source: Texas Instruments

After obtaining the RΘJA parameter, it is possible to calculate the chip’s power dissipation based on the specified junction temperature and ambient temperature. The chip’s power dissipation formula then determines the maximum current that can pass under different operating conditions (for calculation convenience, assume that the chip’s power dissipation equals the conduction losses, although in reality they are different). Table 1 shows the maximum allowable load current under various ambient and junction temperatures.

Tj (°C)	Ambient temperature (°C)	Power losses per GaN (W)	RDS(on) (Ω)	Imax (A)
150	25	5.80	0.00210	74.33
110	70	1.86	0.00188	44.4
125	25	4.64	0.00196	68.8

Table 1 This table documents the maximum allowable load current under various ambient and junction temperatures.

Conclusion

Thermal design is one of the most important steps to help ensure the reliability of high-power-density power supplies. Theoretical calculations of power losses and thermal resistance can clarify the heat generation and heat-transfer behavior of individual components, but cannot accurately characterize the coupled thermal resistance of complex systems.

Thermal simulation software enables efficient extraction of the total system RQJA, rapidly determining operating boundaries under varying power dissipation and ambient temperature conditions, and achieving quantitative analysis and precise optimization of thermal design.

The combination of theoretical calculation and simulation represents an efficient methodology for modern power-supply thermal design and can significantly enhance heat dissipation capability and system reliability, particularly for high-power-density GaN-based designs.

Bert Zhang (Haobo Zhang) currently works as a systems engineer in Texas Instruments’ Power Design Services team to develop power solutions using thermal simulation, magnetic simulation, and power design techniques. He earned a Master’s degree from Nankai University.

 

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The post Power Tips #154: Finding the thermal and current limits of high-power GaN devices through simulation appeared first on EDN.

In the modern engineering landscape, the definition of a “complete lab” is undergoing a radical transformation. It’s no longer measured by the square footage of your workbench or the number of cooling fans humming in the background, but by the versatility of the gear in your bag.

As universal standards like USB bridge the gap between consumer tech and professional hardware, the barrier to high-performance analysis is collapsing. We are entering an era where ownership means having world-class diagnostic power available anywhere, at any time, redefining what it means to be a “ready” engineer.

Death of the benchtop monolith

Remember the days when an oscilloscope wasn’t just a tool, but a structural component of your lab bench? We called them “Boat Anchors” for a reason—those massive, whirring monoliths that required a two-person lift and a dedicated circuit breaker just to warm up the CRT. But the era of the benchtop titan is fading.

Today, the core premise has shifted: USB is no longer just a port; it’s a design philosophy. We are witnessing a fundamental migration where the “guts” of our test and measurement (T&M) gear are shrinking from heavy chassis directly into our pockets. This isn’t just a win for portability or cluttered desks; it’s a technical milestone where the fundamentals of high-speed data transfer and power delivery have finally caught up to the rigorous demands of precision engineering.

Figure 1 Tektronix 564B anchors the lab bench as a 1969 solid-state refinement of the classic tube-based 564 storage scope. Source: TekWiki

USB: More than just a connector

To understand why USB has successfully staged this takeover, we have to look past the plastic housing and into the silicon. At its core, the modern USB-C connector is a marvel of high-density engineering, packing 24 pins into a footprint smaller than a fingernail. Within that cramped space, it manages multiple high-speed differential pairs capable of gigabit-per-second throughput while maintaining strict signal integrity—a necessity for streaming raw, high-resolution waveform data to a host PC without lag.

But speed is only half the story; the real game changer is the evolution of USB Power Delivery (PD). We’ve come a long way from the meager 2.5-W limits of USB 2.0, which could barely keep a mouse alive. With the advent of USB PD 3.1, the interface can now negotiate up to 240 W of power. This massive overhead allows engineers to run high-performance FPGAs and sophisticated analog front-ends directly from the port, eliminating the need for bulky external power bricks.

However, with great power comes the “ownership” challenge. Designing for USB means the instrument must effectively “own” its power rail. In T&M, the primary enemy is a noisy laptop power supply. To prevent switching noise from leaking into the signal chain and ruining the noise floor of a sensitive 16-bit ADC, modern USB instruments must employ sophisticated internal isolation and filtering.

It’s a delicate balancing act: leveraging the convenience of a universal port while building a fortress around the precision electronics to ensure the data stays as clean as it would on a dedicated benchtop rig.

Figure 2 A compact power supply accepts both USB-PD and standard DC inputs, facilitating high-precision power delivery in both lab and field environments. Source: Fnirsi

Pocket T&M: The “software-defined” revolution

This shift in hardware is fueled by a fundamental change in architecture: the rise of software-defined instrumentation. In this new paradigm, the pocket-sized device serves primarily as a high-precision hardware front-end—responsible for signal conditioning and high-speed digitization—while the heavy lifting of signal processing, rendering, and complex analysis is offloaded to the host PC.

By leveraging the gigahertz-class processors and high-resolution displays, we already carry in our laptop bags, these instruments provide a user interface that is often more responsive and intuitive than the embedded systems of traditional benchtop gear.

The real turning point for this revolution was the leap in interface speed. While legacy ports like RS-232 or even USB 2.0 acted as frustrating bottlenecks, USB 3.x and USB4 changed the game. Bandwidth is king in T&M; if you can’t move the data fast enough, you can’t see the signal in real time.

A technical note: To put this in perspective, consider a 100 MHz real-time sample stream. At 8-bit resolution, you are looking at a raw data throughput of roughly 800 Mbps. Legacy USB 2.0, with its theoretical max of 480 Mbps (and much lower real-world performance), simply couldn’t keep up, forcing instruments to rely on expensive internal memory and “burst” captures. USB 3.0, providing 5 Gbps and beyond, handles that stream with room to spare, allowing for continuous, gapless data visualization.

So, why are engineers flocking to this setup? The analytics are clear: portability and seamless laptop integration have become the top priorities for the modern “on-the-go” engineer. Whether you are debugging a sensor array in a remote field, troubleshooting an automotive ECU in a cramped cabin, or simply moving between lab benches, the ability to have your entire diagnostic suite integrated directly into your primary workstation isn’t just a luxury, it’s the new standard for efficiency.

Figure 3 A PC-based USB oscilloscope, specifically designed for automotive diagnostics, uses the computer’s monitor and processing power to display and analyze waveforms. Source: Hantek

The benchtop perspective: USB as the “host”

While “portable” might be the buzzword of the decade, the heavy-duty benchtop gear isn’t going extinct—it’s evolving. Even the most robust, high-bandwidth oscilloscopes and analyzers have stopped treating USB as a mere port for firmware updates and thumb drives. Today, the benchtop instrument has effectively become a USB host, centralizing control over an increasingly modular desk.

The back panel of a modern benchtop unit now looks more like a high-end workstation, unlocking key use cases that are redefining workflow. We’ve moved past the era where every accessory needed its own bulky wall wart.

Manufacturers now offer high-performance current probes that pull both power and data directly from scope’s USB bus, simplifying the cable spaghetti that usually plagues complex setups. Furthermore, we are seeing the rise of LXI over USB, allowing instruments to maintain sophisticated triggering and synchronization while utilizing a ubiquitous physical connection.

The manual era is ending as direct-to-PC automation becomes the standard. Using Python and the VISA protocol, engineers can bridge the gap between a standalone box and a PC in seconds, allowing the benchtop unit to function as a high-speed data acquisition node that streams results directly into a script for real-time analysis.

This shift represents a strategic move in design ownership. Manufacturers are increasingly moving away from generic interfaces in favor of specialized, high-performance USB peripherals. By designing proprietary USB-based ecosystems—like specialized active probes or smart sensors—vendors are creating a locked-in environment.

While this can feel restrictive, the trade-off is significant: by controlling the entire signal path from the probe tip through the USB bus to the processor, they can guarantee a level of signal integrity and auto-calibration that generic components simply cannot match. In this new world, your benchtop gear isn’t just a tool; it’s the hub of a bespoke, high-speed digital network.

Challenges: “Fun” in the fundamentals

The transition to USB-centric instrumentation isn’t without its technical hurdles, often referred to by seasoned engineers as the “fun” part of the design process. The most notorious of these is the dreaded ground loop. When you connect a benchtop scope ground to a PC ground via a standard USB cable, you are often inadvertently tying two different power system references together.

This can create a low-impedance path for circulating currents, which at best introduces significant noise into your measurements and at worst leads to a “recipe for disaster” involving magic smoke and fried motherboards.

To combat these reference issues, galvanic isolation has become a cornerstone of high-quality USB T&M design. This process involves physically separating the input and output sections of the measurement circuit to ensure there is no direct conduction path, usually through the use of optoisolators or transformer-based coupling.

Without robust isolation, a USB instrument is essentially a bridge that can carry high-voltage transients from the device under test (DUT) directly into the heart of your laptop. Implementing this isolation while maintaining high data throughput is one of the most expensive and critical engineering feats in modern portable gear.

Figure 4 An ADuM4160 USB isolator module reflects the industry’s shift toward “hardened” portability by shielding sensitive PC-based instruments from high-voltage transients. Source: Author

Beyond grounding, maintaining signal integrity at the physical layer presents its own set of problems. As T&M gear pushes into the territory of USB 3.2 and beyond, we are dealing with multi-gigabit transfer rates that are incredibly sensitive to electromagnetic interference.

Maintaining a stable 10-Gbps link in a noisy lab environment—surrounded by high-frequency switching power supplies and RF emitters—requires meticulous shielding and advanced equalization techniques. If the physical link degrades, the “real-time” nature of the instrument vanishes, replaced by dropped packets and frustrating latency that can mask the very signal anomalies you are trying to find.

Engineer’s watchouts for USB T&M

The USB-centric test gear delivers impressive portability, but engineers must stay alert to practical hurdles. Real-world throughput rarely matches theoretical USB 3.x speeds, so designs should budget for only 70–80% of the rated bandwidth.

Galvanic isolation remains essential to prevent destructive ground loops, though it adds cost and complexity. Power delivery noise from laptop supplies can easily corrupt sensitive ADC measurements unless robust filtering and regulation are in place. At multi-gigabit rates, electromagnetic interference becomes a serious threat, demanding meticulous shielding and equalization to preserve real-time performance.

Finally, proprietary USB ecosystems may feel restrictive, yet they ensure calibration and signal-path integrity from probe tip to processor—something generic setups often struggle to guarantee.

The future is universal

The evolution of T&M has made one thing clear: to own the design of a tool in the modern era is to own its USB implementation. We have reached a point where the physical box is secondary to the interface that connects it to the user. By mastering the complexities of power delivery, isolation, and high-speed data transfer, manufacturers aren’t just making gear smaller; they are creating a seamless, software-defined ecosystem that lives in your pocket but performs on the bench.

If the fundamental goal of T&M is to measure the world, USB is the bridge that finally makes that world portable. It has transformed the industry from a collection of isolated, heavy machines into a fluid network of high-performance peripherals.

As we look forward, the distinction between “benchtop” and “mobile” will continue to blur until the only thing that matters is the integrity of the data and the speed at which we can see it. The universal port has lived up to its name, becoming the definitive backbone of the next generation of engineering discovery.

So, to the makers and engineers standing at the bench: the barrier to entry has never been thinner, but the complexity has never been higher. Don’t just be a consumer of these new portable ecosystems—challenge them. Use these high-speed interfaces to push your projects out of the basement and into the field; but stay sharp on the fundamentals of isolation and noise that the marketing glossies tend to skip over. The world is now your lab; go out and measure it.

T. K. Hareendran is a self-taught electronics enthusiast with a strong passion for innovative circuit design and hands-on technology. He develops both experimental and practical electronic projects, documenting and sharing his work to support fellow tinkerers and learners. Beyond the workbench, he dedicates time to technical writing and hardware evaluations to contribute meaningfully to the maker community.

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The post The USB takeover: Why modern T&M is moving to your pocket appeared first on EDN.

Line scan cameras occupy a distinctive niche in machine vision: rather than freezing a full frame, they assemble an image one line at a time as the subject moves past the sensor. This scanning method makes them indispensable for inspecting continuous materials, fast conveyor flows, and wide surfaces where resolution and throughput must work in tandem.

In this post, we will offer a glimpse into how line-scan imaging turns motion into precision, sharing a few practical clues along the way.

Line scan camera imaging principles

An industrial line scan camera is a specialized imaging device that uses a single line of pixels instead of a two-dimensional sensor. Unlike conventional cameras, which capture an entire frame at once, a line scan camera records one line at a time in rapid succession. To build a two-dimensional image, the object must move relative to the camera—either conveyed past the sensor or kept stationary while the camera itself moves.

Operating at very high speeds (10–400 kHz), these cameras can scan moving objects without motion blur. Because of their extremely short exposure times, they require bright, uniform line illumination to ensure accurate imaging.

As with conventional 2D imaging, a line scan camera requires both a lens and dedicated line illumination to ensure accurate image capture. Several sensor configurations are available: a single sensor line is typically sufficient for producing monochrome images, while dual-line or quad-line sensors can capture the same image multiple times to increase brightness. This approach reduces the intensity of illumination required, making image acquisition more efficient.

So, in a nutshell, a line scan camera consists of a single row of pixels—or multiple rows in certain configurations—that captures one line of an image at a time. As the object moves past the camera or the camera scans across the object, the system constructs a complete image line by line.

This arrangement is particularly effective in conveyor-based or web inspection systems, where materials move continuously in a linear path. For precision inspection and high-speed applications, line scan cameras are indispensable in modern industrial imaging, delivering continuous, high-resolution images of fast-moving objects or large surfaces with remarkable accuracy.

Figure 1 Pencil sketch demonstrates a line scan camera capturing a flat object line by line to assemble a complete, high-resolution image during continuous motion. Source: Author

As a worthy aside, maintaining image proportions in line scan systems requires precise synchronization between the camera and the movement of the subject. This is typically managed by a rotary encoder, a mechanical sensor connected to the conveyor system that sends electrical pulses to the camera.

These pulses act as external triggers, ensuring that the camera captures each new line only when the object has travelled a specific, pre-defined distance. Without this hardware-level coordination, any fluctuations in the conveyor’s motor speed would cause the resulting image to appear vertically stretched or compressed.

Suitable applications for line scan cameras

Line scan cameras excel in scenarios where continuous movement and fine detail must be monitored with precision. In web inspection, they track paper, textiles, and films for defects across wide surfaces. In electronics manufacturing, they ensure accuracy in PCB production by detecting misalignments or flaws at high speed.

They are equally valuable in glass and surface evaluation, where even subtle scratches or irregularities must be identified. In food and beverage packaging, they verify labeling and seal integrity on fast conveyor lines.

Recycling and sorting operations also benefit, as line scan systems can distinguish materials in real time for efficient separation. Across these varied domains, technology delivers speed, reliability, and resolution that conventional imaging methods cannot match.

Line scan vs. area scan cameras

Choosing the right camera technology is a critical step in designing a machine vision system, and the decision often comes down to whether a line scan or an area scan camera is better suited to the task.

Line scan cameras capture images one line at a time, making them ideal for continuous inspection of fast-moving objects or large surfaces, such as materials on conveyor belts or webs of paper, textiles, and films. Their strength lies in producing seamless, high-resolution images without motion blur, even at very high speeds.

Area scan cameras, on the other hand, use a two-dimensional sensor to capture an entire frame in a single exposure. This makes them well suited for applications where objects are stationary or where the field of view is limited, such as component placement verification, barcode reading, or general object recognition.

In essence, line scan technology excels in continuous, high-speed imaging of extended surfaces, while area scan technology is more versatile for static or discrete object inspection. The choice depends on the nature of the material flow, the required resolution, and the inspection environment.

Figure 2 Line scan and area scan cameras drive machine vision efficiency by capturing high-fidelity visual data for real-time processing. Source: Author (composite); individual images belong to their respective producers

Power and I/O interfaces

Line scan cameras depend on robust power and data interfaces to ensure seamless integration with machine vision systems. Camera Link delivers deterministic, low-latency transmission for high-speed inspection tasks, while CoaXPress (CXP) combines ultra-fast data throughput with power delivery over coaxial cable.

GigE Vision, built on standard LAN/Ethernet infrastructure, is widely adopted because it supports cable runs up to 100 m, scales easily across factory networks, and leverages cost-effective switches and routers. HD-SDI enables real-time, uncompressed video transmission over coaxial lines, often used in broadcast or specialized imaging environments.

For simpler or lower-bandwidth setups, USB 3.0/3.1 provides plug-and-play connectivity with broad compatibility. The choice of interface depends on throughput, cable length, synchronization, and system architecture, with LAN-based GigE Vision standing out as a versatile option for PCB inspection and other industrial imaging applications.

Architecture of linear image sensors in line scan systems

Linear image sensors form the foundation of line scan cameras, capturing one row of pixels at a time to assemble seamless two-dimensional images of moving objects. Charge-coupled device (CCD) sensors shift accumulated charge through a common output register, preserving signal integrity and delivering high dynamic range—a valuable trait for detecting subtle defects on fast conveyor lines.

In contrast, CMOS sensors have become the dominant choice in modern industrial imaging. By converting charge to voltage directly at each pixel, CMOS sensors achieve faster readout speeds, lower power consumption, and greater integration flexibility, making them well suited for today’s extreme production line velocities. Note at this point that while CCDs remain a niche choice for specific scientific spectroscopy, CMOS has become the industry standard due to its superior speed, integration, and cost-efficiency.

For color imaging, line scan cameras often employ a trilinear architecture, consisting of three parallel rows of pixels filtered for red, green, and blue. As the target moves beneath the sensor, each row captures its respective color channel in sequence, and the system reconstructs a full-color line. Advanced designs may also use prism-based multi-sensor configurations to enhance color fidelity.

Figure 3 The S13774 CMOS linear image sensor enables high-speed industrial imaging for machine vision and inspection. Source: Hamamatsu

Because the final image is generated line by line, precise synchronization between the sensor’s line rate and the object’s motion is essential. Any mismatch can introduce spatial distortion, while perfect timing ensures distortion-free, high-resolution composite images. This architecture makes linear sensors indispensable for high-speed inspection tasks such as web monitoring, bare PCB analysis, print verification, and sorting, where continuous imaging of moving materials is required.

Evolution and role of contact image sensors

In modern industrial imaging, contact image sensor (CIS) has advanced from a basic document-scanning component into a high-performance alternative to traditional line scan cameras. Unlike reduction-type CCDs that rely on lenses to project a wide field of view onto a small chip, an industrial CIS functions as a 1:1 imaging system spanning the full width of the production line.

This compact design integrates a dense sensor array, gradient-index fiber lenses, and high-intensity LED lighting into a single housing. Because the sensor matches the width of the material being inspected, CIS modules eliminate edge distortion and uneven illumination often seen in conventional optics.

Over time, CIS technology has become the primary choice for web inspection—monitoring continuous materials such lithium-ion battery electrodes, solar wafers, and high-speed print rolls. Mounted just millimeters from the target, CIS units save valuable machine space while delivering uniform, high-resolution data across wide surfaces without the need for complex stitching software. Although they lack the depth of field offered by CCD-and-lens systems, their ability to provide distortion-free imaging over massive widths has made them the dominant standard for flat-surface industrial automation.

Repurposing surplus sensors for discovery

Whether you’re a seasoned tinkerer or just beginning to explore the world of line scan cameras, this session invites you to see electronic waste through a new lens. Hidden inside discarded flatbed scanners is a frontier of high-speed discovery: a high-resolution CCD, a precision-engineered slice of silicon that once mapped physical reality into the digital realm with sub-millimeter accuracy.

For makers, these surplus sensors aren’t leftovers—they’re the eyes of new projects. Repurposed linear arrays can power DIY Raman spectrometers to identify chemical substances, serve as “finish line” cameras for high-speed photography, even build experimental line scan cameras, or form the core of custom laser-based 3D scanners. It’s a chance to work directly with the physics of light, transforming a few dollars’ worth of surplus electronics into professional-grade instruments that reveal one thin, brilliant line at a time.

From my lab diary, I experimented some time ago with the CJMCU TSL1401CL module, along with discrete linear sensors such as the ILX555K, TCD1304AP, and KLI-8023. Those sessions helped me grasp the subtleties of line scan imaging—from timing control and signal conditioning to noise suppression and optical alignment.

Figure 4 The TCD1304AP CCD Linear Image Sensor upholds its legacy as a POS scanner workhorse by utilizing a precision electronic shutter to stabilize signal output against the unpredictability of ambient lighting. Source: Toshiba

Each component revealed its own quirks, turning datasheet specifications into hands-on lessons. That tinkering not only deepened my understanding of sensor behavior but also gave me the confidence to repurpose surplus parts into meaningful experiments, bridging theory with practical discovery.

This marks the end of the post. The journey through line scan cameras may also reveal a gateway to learning, invention, and the thrill of seeing light itself transformed into knowledge one line at a time.

T. K. Hareendran is a self-taught electronics enthusiast with a strong passion for innovative circuit design and hands-on technology. He develops both experimental and practical electronic projects, documenting and sharing his work to support fellow tinkerers and learners. Beyond the workbench, he dedicates time to technical writing and hardware evaluations to contribute meaningfully to the maker community.

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The post Line scan cameras: Fundamentals in focus appeared first on EDN.

Providing power via contact-closure circuits historically required a new third wire, but perhaps no longer.

Say the words “solid-state relay” (SSR) and most engineers also naturally think of two unspoken adjectives: “optical” and “isolation” (although the galvanic isolation can also be implemented using magnetic, capacitive, RF, or other techniques).

But that doesn’t have to be the case, as an SSR can also be non-isolated as well as non-optical. An example is a small IC introduced by Littelfuse, Inc. in late 2025: the CPC1601M, a 60 V, 2 A normally open (1-Form-A) solid-state latching relay targeting critical integration and power challenges in thermostat, HVAC, and building automation wiring (Figure 1).

Figure 1 The block diagram of the Littelfuse CPC1601M solid-state latching relay shows its basic input and output connections as well as internal function blocks. (Image source: Littlefuse)

What’s the problem here that needs solving? It’s largely a legacy issue and one that sounds simple enough – but it’s not.

Consider the classic two-wire thermostat still in use in millions of homes. It’s simple, reliable, and easy to troubleshoot. These thermostats provide a “dry” contact closure to call for heat when the sensed temperature drops below their setpoint. The heating system provides 24 VAC to this contact-closure loop via an AC-line transformer; when the circuit is closed, the 24 V energizes the coil of an electromechanical relay that turns on the 120 V/240V heating system.

Note: Dry contacts have a power source going through them that is independent of the power in the circuit they are controlling (often done by a relay). In a “wet” circuit, the controlling switch  or element is directly handling the full load current and voltage. A standard wall light switch is a wet circuit, as that switch handles the 120 VAC that goes to the light bulb. The terms “wet” and “dry” are holdovers from the pre-electronics days of electricity when wet electrochemical cells were used as higher-voltage batteries.

But there’s the problem with this elegantly simple two-wire dry scheme: when the homeowner wants to upgrade from the unpowered contact-closure unit to a better thermostat with digital readout or a smart Wi-Fi-enabled thermostat, that thermostat needs a power source. However, there is no power source in the open loop that thermostat controls: when the loop is open, there is no current flow.

In many such “upgrade” situations, the unpleasant solution is to run a new third wire for needed power, designated as the “common” or “C” wire. (Note that this “common” in unrelated to what electronic circuit designers called circuit common, as the HVAC industry has its own terms and designations.

Of course, running that third wire can be difficult, especially in a house with multiple floors and rooms. It often involves cutting openings in the walls to snake the wire around obstacles such as framing, fire stops, wiring conduits, and plumbing.

Littelfuse maintains that CPC1601M is the first PCB-mounted solid-state relay of its kind that combines load-powered operation with a latching architecture in a 3 × 3 mm DFN IC package. It can harvest operating power directly from the load or draw less than 1 μA from the system supply, thus enabling zero-power operation while dramatically extending battery life or eliminating the need for batteries altogether.

Solving missing-power challenge, CPC1601M relay can obtain operating power from the open-circuit load or system power supply. When power is supplied by the load, the relay opens periodically to obtain power via the open-circuit load voltage. In most applications this very short interruption is transparent to the load (Figure 2).

Figure 2 In basic load-powered mode, relay K1 is controlled by turning the CPC1601M relay on and off. (Image source: Littlefuse)

Its use is not limited to thermostats; it is also a viable solution to upgrading other contact-closure designs such as fire-control panels, security systems, and building automation subsystems.

What about the lack of galvanic isolation? That’s easy: it’s not needed here. The electromechanical relay that activates the heating system provides the needed isolation between the thermostat control loop and the 120/240 VAC heating system power (relays easily provide thousands of volts of isolation).

If you do need galvanic isolation – a requirement in dual-transformer HVAC systems where the transformer returns are separate and isolated from each other – it can be implemented with the addition of a few capacitors providing capacitive coupling of a PWM signal (Figure 3).

Figure 3 In the galvanically isolated configuration, the system microcontroller generates several multiple cycles of a PWM signal that is capacitively coupled by isolation capacitor C1. This PWM signal is filtered by R2 and C2 thus creating a DC signal that is used to trigger the SET input of the CPC1601M. (Image source: Littlefuse)

Additionally, the CPC1601M provides a power output pin that can supply external circuits with a maximum of 10 mW of power. The CPC1601M can sense whether it is powered by the load or by the system power supply automatically by monitoring the HVCC input pin. The load-powered mode of operation applies to an AC source, such as a 24 VAC transformer secondary voltage.

If all this seems confusing – and even simple circuits can be, depending on context – Littelfuse offers the LEB-0024 Evaluation Board with full documentation (Figure 4). The kit includes input and load-circuit terminal blocks along with switches for mode selection and manual relay operation.

Figure 4 The LEB-0024 Evaluation Board makes it easy to “play around” with the CPC1601M to better understand its functions in each application. (Image source: Littlefuse)

Have you ever had to deal with an upgrade issue where a conceptually simple requirement such as “just add another wire” had a ripple effect with respect to design-in, installation, bill of materials, or retrofit issues? How did you resolve these challenges?

References

• Worth HVAC Training, “What are ‘Dry Contacts“
• Control by Web, “Understanding Dry Contacts and How to Monitor Them”
• Electrical4U, “Dry Contacts: What is It?”
• High Performance HVAC, “How to Wire a Thermostat | HVAC Control”
• High Performance HVAC, “Running New Thermostat Wire | HVAC Heating and Cooling”
• High Performance HVAC, “Programmable Thermostat Wiring Diagrams | HVAC Control”

—Bill Schweber is a degreed senior EE who has written three textbooks, hundreds of technical articles, opinion columns, and product features. Prior to becoming an author and editor, he spent his entire hands-on career on the analog side by working on power supplies, sensors and signal conditioning, and wired and wireless communication links. His work experience includes many years at Analog Devices in applications and marketing, and he also developed significant mechanical-engineering insight while designing control electronics for large materials-testing systems.

Related Content

• Relays Are Great, But There’s No Need to Let Them Waste Power
• Electromechanical relays: an old-fashioned component solves modern problems
• The pulse of power: Mastering the PWM relay

The post A non-isolated SSR solves a not-so-simple “simple” power problem appeared first on EDN.

Going the MVNO route involves potential risks for cellular companies and their customers alike…but also lots of possible upsides.

In conjunction with my recent deeper re-engagement with EDN from an employment standpoint, I not only reconfigured an existing computer in a LAN-isolating fashion but also set up a separate work mobile phone line. For hardware, I pulled out of storage the Google Pixel 7 that I’d mothballed at the conclusion of my prior “day job”. And since I was now on my own from a cellular provider-and-plan selection standpoint, I decided to finally give Google Fi Wireless a try.

The enemy of my enemy is my friend?

Originally known as Project Fi, then Google Fi (with “Wireless” more recently stuck on the end), this particular provider is, like US Mobile and others both in the US and around the world, a Mobile Virtual Network Operator (MVNO). Wikipedia’s entry starts by describing a MVNO as:

A wireless communications services provider that does not own the wireless network infrastructure over which it provides services to its customers. An MVNO enters into a business agreement with a mobile network operator (MNO) to obtain bulk access to network services at wholesale rates, then sets retail prices independently. An MVNO may use its own customer service, billing support systems, marketing, and sales personnel, or it could employ the services of a mobile virtual network enabler (MVNE).

That high-level description doesn’t dive into the minutia of various MVNO implementation variants, nor do I plan to do so here. Broadly speaking, I’ll stick with the high-level observation that it’s an intriguing business model that sometimes leads to startup company “flameouts”. Other times, it results in acquisitions by prior partners, with the MVNO either fully subsumed by the purchaser or maintaining a separate marketing identity and subsequently referred to as a “flanker brand” or as a “captive” versus prior “independent” MVNO. And some companies, such as Google Fi Wireless, remain independent MVNOs long-term.

MVNOs, perhaps obviously, don’t need to shoulder the substantial incremental costs of building out and maintaining a nationwide cellular network. Nor do they need to spend the money necessary to both secure and retain spectrum licenses. And, because they’re generally smaller, their promotional budgets are also leaner than their Mobile Network Operator (MNO) partners. But they also can’t be freeloaders, leading to the obvious next question…what’s in it for the MNO? Incremental revenue (taking the form of bulk, per-customer and/or per-packet regular payments) from MVNO partners, generated by the incremental use of any available excess network resources that would otherwise lie fallow, i.e., go to waste.

Therein lies the potential risk with MVNOs: if the MNO’s own customers consume the entirety of network capacity, there’ll be none left over for the MVNO’s own customers. Averting this outcome requires both upfront and ongoing negotiations between the MVNO and MNO, with “throttling” (dynamic bandwidth adjustments in reaction to capacity utilization changes) an interim step prior to, and hopefully also preventing, MVNO service shutoffs at heavy-use times.

An encouraging first date…

Google initially launched its MVNO service in 2015 alongside the Nexus 6 smartphone, in partnership with both Sprint and T-Mobile; the latter subsequently acquired the former in 2020. Google Fi Wireless currently comes in four plan tier options, all delivering 5G data rates:

• Flexible (“Pay for the data you use”)
  • $35 per month for 2 lines + data ($18 per line + $10/GB), for example, or $20 per month for 1 line + data
  • Data for $10/GB
  • High-speed hotspot tethering
  • International data in 200+ destinations
  • Connectivity for tablets and laptops
  • Full connectivity for select smartwatches
• Unlimited Essentials (“Our most affordable plan”)
  • $60 per month for 2 lines ($30 per line), for example, or $35 per month for 1 line
  • 30 GB of high-speed data
  • Full connectivity for select smartwatches
• Unlimited Standard (“Hotspot tethering for your devices”)
  • $80 per month for 2 lines (or $40 per line), for example, or $50 per month for 1 line
  • 50 GB of high-speed data
  • 25 GB of high-speed hotspot tethering
  • International data in Canada and Mexico
  • Full connectivity for select smartwatches
• Unlimited Premium (“Maximum perks & global connectivity”)
  • $110 per month for 2 lines (or $55 per line), for example, or $65 per month for 1 line
  • 100 GB of high-speed data
  • 50 GB of high-speed hotspot tethering
  • International data in 200+ destinations
  • Connectivity for tablets and laptops
  • Full connectivity for select smartwatches
  • 6 months of YouTube Premium
  • 100 GB of storage with Google One

The above pricing is standard; transient and varying-details pricing promotions that dip below the “MSRPs” are common. I’d even suggest that promotions are the rule versus the exception, not only with Google Fi Wireless but other MVNOs more broadly, further extending to all mobile operators more generally. For my new work line (in which, judging from the phone calls, voicemails and text messages I’ve subsequently received, I inherited a phone number formerly used by a Verizon customer named Robert with really bad credit), I went with the Unlimited Standard plan, since it included hotspot support as well as data support for my Pixel Watch. And at the time I signed up, since I was bringing my own phone, Google was offering half-off the published monthly rate for the first year. $25 per month for one line of service: not too shabby.

…led to a deeper relationship

After a few weeks of trying out the Google Fi Wireless, positively assessing both the company’s customer service and coverage robustness (particularly important in my Rocky Mountains foothills rural locale), I belatedly switched my personal line from AT&T over to Google Fi Wireless, too. I’d been on AT&T since mid-2010 (I’d switched to it from T-Mobile, ironically; nothing like going full circle!) the data portion of the monthly fee was “true” unlimited (i.e., non-throttled) and originally $30. By the time I canceled nearly sixteen years later, it had risen to $45/month but added visual voicemail and had also migrated from 3G (UMTS HSPA) to (4G LTE). More generally, here’s a breakdown of what I was paying per month:

I’d (too long) clung to it primarily due to its true-unlimited data nature; AT&T no longer offered this specific plan option, but I was “grandfathered” in as long as I didn’t cancel. As just noted, AT&T had upgraded it from 3G to 4G at no incremental charge (at the time; the $15/month adder was tacked on later as multiple $5/month increments). But the company declined to further upgrade it to 5G (not just gratis but at all); the “5GE” icon on my phone was marketing fluff, instead reflecting 4G LTE Advanced service. And since my plan didn’t support hotspot capabilities and the data allotment was therefore restricted to use solely by the phone itself, I was woefully undershooting its “unlimited” usage potential each month, anyway.

Instead, this time I went with Google Fi Wireless’s “Unlimited Premium” plan. Twice as much high-speed data included in the base price per month, twice as much of that also shareable with other devices via integrated hotspot support. Now’s as good a time as any to describe what Google Fi Wireless means by “unlimited”, i.e., what happens after you hit a plan’s per-month included-data threshold (save for the “Flexible” plan, where you pay $10/GB from the get-go):

• The data actually keeps flowing at no extra charge, albeit at a substantially “throttled” rate: 256 Kbps downstream.
• If you want more high-speed data within that month, you can incrementally purchase it at the $10/GB rate shown in the earlier bullet lists.

Data details

Speaking of data, the “Unlimited Premium” plan also includes up to four data-only SIMs at no extra charge, usable in cellular-cognizant devices such as my Surface Pro X and Surface Pro 7+/8 laptops, as well as my various iPad tablets (one’s in my 11” iPad Pro now, in fact) along with any dedicated cellular hotspot devices. Their data usage, in addition to that of my smartphone (both natively and via hotspot) and watch cumulatively goes against the plan’s per-month usage limit.

And speaking of dedicated cellular hotspot devices, the high-end NETGEAR Nighthawk M6 MR6110 I talked about back in mid-March:

is carrier-locked to AT&T. And although the mid-range Franklin A50 also covered there:

initially seemed to be third-party-unlockable, Unlocklocks wasn’t able to get me an unlock code after all (although to its credit, the company quickly refunded me in full after I submitted an order with the device IMEI). The low-end (LTE-only) Franklin T9, on the other hand:

is natively a T-Mobile-centric device. And since Google Fi Wireless runs on T-Mobile’s network, I was able to get up and running straightaway after ordering, receiving and activating a data SIM. For 5G purposes, I sprung for two more used hotspot devices (this time T-Mobile supportive), in both cases bought off eBay and manufactured by Inseego: the high-end MiFi X Pro 5G M3000:

and mainstream M2000 5G MiFi:

Pinching pennies

How much did this all cost? That’s perhaps the best part of all. For one thing, I’m getting $10/month off the normal $65 monthly service rate for the first two years. And I’m also getting a free Pixel 10 (the one below is “Indigo”, mine’s “Obsidian”):

a smartphone I’d initially covered during last August’s intro and I’ll write more about next week. Normally $799 for my 128 GByte variant, Google did an upfront-acquisition discount to $499. That’s a notable markdown as-is, although given that the Pixel 11 family is seemingly enroute, I’ve already seen discounts (although not to this degree) elsewhere already, too. The remaining to-free discount amount takes the form of monthly credits against the service cost, again spread out over 24 months. My Pixel 7 phones are scheduled to fall off the supported device list next October (a two-year extension to the original expiration, mind you), so I’d already been looking for a replacement anyway. I already have a Pixel 9a, which I’d traded in my earlier Pixel 6a to acquire, queued up as the eventual replacement for the “work” Pixel 7; I’ll keep both of them as spares.

There’s also one other monthly expense reduction that I’m considering as well. Conceptually, at least, the data service delivered by the Google Fi Wireless “Unlimited Premium” plan’s data-only SIMs is functionally redundant with the AT&T 5G data service that I still have active. Granted, I’m getting a $20/month discount from AT&T off the normal $55 plan rate. And the fact that just a few months ago, I spent a few hundred dollars on AT&T-only hotspots and accessories (extra batteries, cases, etc.) is also giving me pause. But the AT&T 5G plan, although remarkably fast especially on the external antennae-supportive high-end hotspot device, only provides 5 GBytes per month at the nominal fee rate. And a bit more than a dollar per day, $420/year said another way, is money that I could redirect elsewhere or “bank” for the future.

Not a shill

In closing, in case you were wondering, Google doesn’t have any idea that I’ve written this piece. I’m just a happy (so far, at least) customer who also finds the overall MVNO business model interesting. Analogies to the MVNO-and-MNO relationship that come to mind include:

• The semiconductor foundry model, although in this case, TSMC and its foundry-only kin aren’t simultaneously also acting as merchant chip suppliers, and
• Deep learning model developers who license them for use by other software-and-services providers, although in this case, open-source model alternatives also exist

Ironically, in looking back at the June 2010 post that had kicked off my move to AT&T as I wrapped up this writeup, I realized that I’d started it out as follows:

Ever experience one of those situations where, afterward, you wonder why it took you so long to tackle the undertaking? That’s what I’m feeling right about now.

With respect to my current situation, I couldn’t have said it any better myself. Wait…I did. Let me know your thoughts in the comments!

—Brian Dipert is the associate editor, as well as a contributing editor, at EDN.

Related Content

• De-commingling LAN equipment: It’s all in what you call it
• From T-Mobile To AT&T: It Couldn’t Have Been More Easy
• Verizon’s (and others’) 5G: underwhelming is putting it mildly
• Cellular hotspots: Multi-option evaluation thoughts
• If you made it through the schtick, Google’s latest products were pretty fantastic

The post Try Google Fi (Wireless)? The perks-for-the-price are why appeared first on EDN.

Every PCB designer has experienced it. A design progresses through schematic capture and layout only to reveal problems during verification, simulation, design review, or manufacturing preparation. A differential pair violates a critical constraint. A return path is compromised. A fabrication limitation was overlooked. A proven solution from a previous design was recreated rather than reused.

The result is familiar: additional iterations, schedule delays, increased costs, and engineering resources consumed by preventable rework.

For decades, many organizations have accepted this cycle as a normal part of PCB development. As design complexity continues to increase, however, this approach is becoming increasingly difficult to sustain. High-speed interfaces, power integrity requirements, signal integrity challenges, miniaturization, manufacturability demands, and compressed development schedules are all converging simultaneously. The traditional response—adding more reviews, more manual checks, and more engineering effort—does not scale.

In today’s design environment, productivity can no longer be measured by the amount of effort expended. It must be measured by how effectively engineering knowledge is captured, applied, reused, and enforced throughout the design process. This is where automation and abstraction are fundamentally changing how successful engineering organizations approach PCB design.

Rethinking productivity in PCB design

Historically, productivity improvements were often achieved by increasing engineering resources or extending design schedules. While those approaches may provide temporary relief, they do little to address the root causes of inefficiency. The reality is that many PCB development processes remain heavily dependent on manual intervention.

As design complexity increases, these manual approaches create significant risk. Constraints are often defined inconsistently. Verification occurs after implementation. Design knowledge resides primarily with individual engineers. Reuse is informal and dependent upon who remembers what was done on a previous project. The challenge is not a lack of engineering talent. The challenge is that manual processes struggle to keep pace with the increasing demands placed on modern electronic systems.

True productivity improvements come not from performing more work, but from eliminating unnecessary work altogether. More importantly, they come from preventing problems before they occur.

Automation: Enforcing design intent in real time

Automation represents a shift from manual execution to intelligent process control. Automation-assisted PCB design environments provide the ability to define electrical, physical, manufacturing, and reliability requirements as constraints that are continuously enforced throughout implementation.

Rather than relying on engineers to manually identify violations after routing is complete, constraint-driven design environments can evaluate compliance in real time. This enables:

• Continuous enforcement of electrical and physical design rules
• Real-time verification during placement and routing
• Guided routing aligned with signal and power integrity requirements
• Automated validation of manufacturing constraints
• Automated generation of manufacturing deliverables

The significance of this shift extends beyond simple efficiency gains. When design rules are evaluated continuously throughout implementation, engineers spend less time identifying problems and more time solving higher-value design challenges. Design intent becomes embedded within the process itself rather than residing solely in engineering documentation or individual expertise.

The result is improved design quality, reduced rework, greater predictability, and shorter development cycles. Simply put, designs become correct by construction rather than corrected after construction.

Engineering knowledge should not leave with the engineer

One of the most significant challenges facing engineering organizations today is the management of institutional knowledge. Many companies still depend heavily on the experience of senior engineers to ensure successful implementation of complex designs. While expertise remains invaluable, this approach creates an inherent scalability problem.

When critical knowledge exists primarily in the minds of individual contributors, organizations become vulnerable to personnel changes, inconsistent execution, and repeated mistakes. The departure of a key engineer should not result in the loss of years of accumulated design intelligence. Automation provides a mechanism for capturing and institutionalizing engineering knowledge.

Constraints, routing strategies, manufacturing requirements, design guidelines, and verification methodologies can be embedded directly within the design environment. Rather than relying on tribal knowledge, organizations can create repeatable engineering processes that consistently produce successful outcomes. The objective is not to replace engineering expertise. The objective is to amplify it and make it scalable across teams, programs, and future generations of designers.

Abstraction: Simplifying complexity through reuse

As systems become more sophisticated, managing every design detail at the individual net level becomes increasingly inefficient. This is where abstraction becomes a powerful productivity enabler. Abstraction allows engineers to work at higher levels of design intent by encapsulating proven solutions into reusable building blocks.

Examples include:

• Reusable hierarchical design blocks
• Standardized constraint templates
• Proven interface implementations
• Reference architectures
• Verified subsystem designs
• Reusable placement and routing methodologies

Design reuse is often misunderstood as simply copying circuitry from a previous project. Effective reuse goes much further. It involves capturing validated circuitry, proven constraints, routing topologies, placement strategies, manufacturing knowledge, and verification data so that future projects can build upon prior success rather than recreating it from scratch.

The difference is significant. Instead of repeatedly solving the same problems, engineering teams can focus their efforts on innovation and differentiation. This transforms design knowledge from a project-specific asset into an organizational asset.

From design automation to intent-driven design

Individually, automation and abstraction provide substantial benefits. Together they enable a more profound transformation: intent-driven design.

In an intent-driven workflow, engineers focus on defining system objectives, performance requirements, and design constraints. The design environment then continuously enforces those requirements throughout implementation. This reduces reliance on manual interpretation while improving consistency across teams and projects.

Intent-driven methodologies help ensure that:

• Design requirements remain aligned throughout implementation
• Constraints are applied consistently
• Reuse strategies are standardized
• Verification becomes continuous rather than sequential
• Manufacturing considerations are addressed earlier in the process

The result is a more predictable design flow that reduces ambiguity and improves overall engineering effectiveness.

Overcoming the adoption barrier

Despite the benefits, many organizations hesitate to adopt advanced automation and abstraction methodologies. The most common concern is the upfront investment required to define constraints, establish reusable design frameworks, and standardize engineering processes. From the perspective of an individual project, these activities can appear to add time. From the perspective of the organization, however, they represent investments in long-term scalability.

Every reusable design block created today can eliminate future engineering effort. Every validated constraint template can prevent future design errors. Every automated verification process can reduce future iterations. Over time, these benefits multiply.

Organizations that continue relying primarily on manual processes often find themselves trapped in a cycle where increasing complexity demands increasing effort. Organizations that invest in automation and abstraction create systems that scale with complexity, rather than being overwhelmed by it.

Connecting design intent across the product lifecycle

The value of automation and abstraction extends beyond PCB layout. Today’s products are increasingly developed within digital engineering ecosystems where requirements, simulation, design, manufacturing, and test activities must remain connected.

Traditional workflows often rely on disconnected tools and fragmented data sources. This creates opportunities for miscommunication, inconsistent implementation, and costly delays. On the other hand, a connected digital thread helps maintain continuity of design intent throughout the product lifecycle by linking:

• System requirements
• Architecture development
• PCB design and layout
• Simulation and verification
• Manufacturing preparation
• Test and validation

This continuity improves traceability, reduces information loss, and supports a model-based engineering approach where decisions are informed by connected data rather than isolated activities. As organizations continue advancing toward digital engineering and digital twin methodologies, the ability to maintain and leverage design intelligence throughout the lifecycle will become increasingly important.

Capture, reuse, and apply design intelligence

The future of PCB design will not be defined by how many hours engineers spend pushing traces or performing repetitive verification tasks. It will be defined by how effectively organizations capture, reuse, and apply engineering intelligence throughout the design process.

Automation and abstraction are not about replacing engineering expertise. They are about amplifying it. When constraints are defined once and enforced consistently, when proven design knowledge can be reused across programs, and when design intent remains connected throughout the product lifecycle, engineering teams gain something far more valuable than incremental productivity improvements: they establish predictability.

The organizations that embrace this shift will be better positioned to manage increasing design complexity, accelerate development cycles, and deliver higher-quality products with greater confidence. In an industry where complexity continues to grow faster than available engineering resources, success will increasingly belong to those who can transform engineering knowledge into scalable engineering intelligence.

Stephen V. Chavez is a principal printed circuit engineer with over three decades of experience. He is acknowledged globally as an industry Subject Matter Expert (SME) in PCB design. He is also an author, blogger, podcast host and is currently a principal technical product marketing manager with Siemens EDA.

Related Content

• It’s Time for AI in PCB Design
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• How to Achieve Excellence in High-Current PCB Design
• Design guidelines for effective automated PCB assembly
• EDA AI Agents: Intelligent Automation in Semiconductor and PCB Design

The post How automation and abstraction are transforming PCB design appeared first on EDN.

Allegro DVT’s Pulsar D400 series of multi-format video decoder IP now supports real-time AV2 decoding for advanced SoCs and ASICs. AV2, developed by the Alliance for Open Media, is an open, royalty-free video compression specification designed for next-generation streaming applications. As the successor to AV1, it improves compression efficiency, delivering high-quality video at significantly lower bitrates.

With AV2 capability, the Pulsar D400 series enables streaming applications up to 8K resolution with ultra-low-latency decoding (down to the sub-frame). Its multi-codec architecture supports H.264, HEVC, VVC, VP9, and AV1, while reducing silicon footprint, DDR memory bandwidth requirements, and power consumption.

 Allegro DVT also provides AV2 development and validation tools, including the Sirius AV2 Test Suites and Astralis AV2 Bitstream Analyzer, along with silicon-proven IP and compliance expertise.

Pulsar D400 product page 

Allegro DVT 

The post AV2 decoder joins multi-codec IP family appeared first on EDN.

EPC’s EPC99132 evaluation board is a GaN-based three-phase inverter for small BLDC motor drives in drones and robotic wrists. The design is built around the EPC33110, a 100-V, 20-A three-phase ePower Stage module that integrates three half bridges (six eGaN FETs), gate drivers, level shifters, and bootstrap circuitry in a 6×6.5-mm QFN package.

The EPC33110 co-packaged module requires a 5-V supply and supports 3.3-V or 5-V logic inputs. Its integrated eGaN FETs feature typical on-resistance values of 11.7 mΩ (high-side) and 13 mΩ (low-side). Performance testing demonstrated continuous current delivery of 11 ARMS per phase in a 48-V robotic joint at switching frequencies up to 100 kHz.

The EPC91132 evaluation board operates from a 10-V to 60-V DC input and integrates an MCU, regulated power supplies, DC bus voltage sensing, and current sensing. It also includes an onboard magnetic encoder for rotor position and speed control. The inverter is 23 mm in diameter, making it suitable for small drone motors.

The EPC91132 is priced at $406.25. Design support materials, including schematics, bill of materials, and Gerber files, are available for download on the product page.

EPC99132 product page

Efficient Power Conversion 

The post GaN inverter board drives compact BLDC motors appeared first on EDN.

GigaDevice offers the GD32E512 and GD32E252 MCUs purpose-built for high-speed and low-speed optical modules, respectively. The devices target applications in AI data centers, cloud infrastructure, telecommunications networks, and access networks.

The GD32E512 features an Arm Cortex-M33 core operating at 120 MHz and integrates I3C support for high-bandwidth, low-latency, high-density communications in next-generation optical modules. Its peripheral set includes two 12-bit ADCs, up to eight 12-bit DACs, two comparators, two op amps, three I²C interfaces, and one MDIO interface, enabling monitoring, control, and management functions in a compact 3×3-mm chip-scale package.

Powered by an Arm Cortex-M23 core operating at 72 MHz, the GD32E252 delivers a balance of performance, integration, and efficiency for cost-sensitive and lower-speed optical connectivity applications. The MCU integrates one 12-bit ADC, four 12-bit DACs, one comparator, one I²S interface, and three I²C interfaces in a choice of QFN package options. 

GD32E512 product page 

GD32E252 product page

GigaDevice

The post MCUs optimize control in optical modules appeared first on EDN.

A smart load switch from Diodes features low on-resistance for reliable power sequencing and rail control in automotive applications. Designated the DML1012ALDSQ, it integrates an N-channel MOSFET with 8-mΩ RDS(ON), minimizing conduction losses and reducing heat generation. The single-channel device is well suited for ADAS, infotainment platforms, and display clusters.

The switch supports a 0.8-V to 1.5×VBIAS input range and operates from a 3.2-V to 5.5-V bias supply, allowing flexibility across subsystem power rail domains. A junction-to-case thermal resistance of 8°C/W enables up to 6 A of continuous output current under appropriate thermal conditions, while low 28-µA quiescent current from VBIAS improves efficiency during power gating and reduces standby power consumption. Together, these features deliver precise system-level power sequencing.

For automotive power management applications, the DML1012ALDSQ integrates controlled output voltage slew rate, quick output discharge, and undervoltage lockout (UVLO) protection features. Controlled slew rate minimizes inrush current during startup, while quick output discharge fully discharges downstream components during shutdown. UVLO disables operation when the supply voltage falls below a safe threshold, helping ensure predictable system behavior.

Prices for the DML1012ALDSQ start at $0.17 each in 1000-piece quantities.

DML1012ALDSQ product page

Diodes Inc.

The post Smart switch simplifies automotive power sequencing appeared first on EDN.