Microelectronics world news

The UK semiconductor industry is at a critical stage in its evolution, according to Martin McHugh, CEO at Compound Semiconductor Applications (CSA) Catapult (a not-for-profit center of excellence established in 2018 by government agency Innovate UK that specializes in the measurement, characterization, integration and validation of compound semiconductor technology spanning power electronics, advanced packaging, radio frequency and microwave, and photonics applications). As Europe, the USA, China, Japan and South Korea invest, there is a significant risk of the UK being left behind, he adds...

Discrete semiconductor and passive electronic component maker Vishay Intertechnology Inc of Malvern, PA, USA is investing £51m in Newport Wafer Fab in South Wales (the UK’s largest semiconductor wafer fabrication facility, which it acquired from Nexperia in March for $177m, or about £142m), bringing new product range capabilities and skilled job opportunities to what is now Newport Vishay...

After completing due diligence, the US Department of Commerce has finalized two direct funding awards under the CHIPS Incentives Program’s Funding Opportunity for Commercial Fabrication Facilities...

The semiconductor industry is undergoing a major realignment to serve artificial intelligence (AI) and related environments like data centers and high-performance computing (HPC). That’s partly because AI chips mandate new design skills, tools, and methodologies.

As a result, IP suppliers, chip design service providers, and AI specialists are far more prominent in the AI-centric design value chain. Below are four design use cases that underscore the realignment in chip design models serving AI applications.

1. LG engages Tenstorrent

LG Electronics has partnered with Tenstorrent to enhance its design and development capabilities for AI chips tailored to its products and services. The Korean conglomerate aims to link its system design capabilities with AI-related software and algorithm technologies and thus enhance its AI-powered home appliances and smart home solutions.

Tenstorrent is known for its HPC semiconductors for specialized AI applications. The two companies will work together to navigate the rapidly evolving AI landscape to secure competitiveness in on-device AI technology. Meanwhile, LG has established a dedicated system-on-chip (SoC) R&D center focusing on system semiconductor design and development.

Figure 1 Tenstorrent CEO Jim Keller joined LG CEO William Cho at the LG Twin Towers in Yeouido, Seoul, to announce AI chip collaboration.

2. Arm-based AI chiplet

Egis Technology and Alcor Micro are leveraging Neoverse Compute Subsystems (CSS)—part of the Arm Total Design ecosystem—to develop new chiplet solutions targeting the HPC and generative AI applications. “As generative AI applications continue to proliferate, the demand for HPC is rising faster than ever,” said Steve Lo, chairman of Egis Group.

Figure 2 Neoverse Compute Subsystems (CSS) offer a speedier way to produce Arm-based chips by including more pre-validated components besides processor cores. Source: Arm

Egis will provide UCIe IP, an interconnect interface for chiplet architecture, while Alcor will contribute expertise for Chip-on-Wafer-on-Substrate (CoWoS) advanced packaging services and chiplet design. Arm will offer its latest Neoverse CSS V3 platform to enable high-performance, low-latency, and highly scalable AI server solutions.

3. OpenAI’s in-house chip

Tech industry darling OpenAI is working with chip designer Broadcom and chip manufacturer TSMC to create a chip specifically for its AI systems. The Silicon Valley upstart, one of the largest buyers of AI chips, uses chips to train models for AI to learn data and carry out inference where AI applies the data to make decisions or predictions.

According to a Reuters story, OpenAI has been working with Broadcom for months to build its first AI chip focusing on inference. The AI powerhouse has assembled a team of about 20 chip designers, which includes designers who developed Google’s famed tensor processing units (TPUs); Thomas Norrie and Richard Ho are prominent names in this design team.

4. Sondrel wins HPC chip contract

Sondrel recently announced a multi-million design win for a high-performance computing (HPC) chip project. HPC is in a huge demand for AI, data center, and scientific modeling applications that require tremendous computing power. The Reading, U.K.-based chip design service provider has started front-end, RTL design and verification work on this HPC chip.

Figure 3 In HPC chips, it’s imperative that data flow is balanced and that processors are not stalled waiting for data. Source: Sondrel

As Sondrel’s CEO Ollie Jones puts it, HPC designs require large, ultra-complex custom chips on advanced nodes. These chips require advanced design methodologies to create billion-transistor designs at leading manufacturing process nodes.

HPC designs require multicore processors running at maximum clock frequencies while utilizing advanced memory and high-bandwidth I/O interfaces. Then there is network-on-chip (NoC) technology, which enables data to move between processors, memory and I/O while allowing the processors to reliably share and maintain data available in their caches.

The coming AI disruption

Every decade or so, a new technology transforms the semiconductor industry in profound ways. This time around, AI and relating technologies such as HPC and data centers are reshaping chip fabrics to cater to unprecedented data flows inside these semiconductor devices.

It’s a trend to watch because the AI revolution is just getting started.

Related Content

• Special report: HPC enables innovation
• The role of cache in AI processor design
• AI boom and the politics of HBM memory chips
• The Future of Medical Research: HPC, AI & HBM
• Enhancing the Efficiency of AI and HPC Data Centers

The post Four tie-ups uncover the emerging AI chip design models appeared first on EDN.

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Aelum Inc of Goleta, CA, USA – which uses compound semiconductor materials on large-diameter substrates to develop technologies for mobile, automotive, AI, defense & aerospace, communication and quantum computing – has joined Optica, the global society dedicated to advancing optics and photonics worldwide. The corporate membership aligns Aeluma with a network of industry leaders in light science and technology...

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Having already examined the Colpitts oscillator, we now look at its first cousin, the Clapp oscillator.

Please consider the following illustration in Figure 1.

Figure 1 A Clapp oscillator where the passive components are arranged on the right-hand side for easier viewing. Source: John Dunn

There is an R-L-C network of passive components and an active gain block. This circuit differs from the Colpitts by now using a third capacitor (C3) in series with the inductance (L1) and by now needing a DC path: R2, to ground for the gain block. The output impedance of the gain block is zero and the value of its gain (A) is nominally unity or perhaps a little less than unity. The resistance R1 models the output impedance that a real-world gain block might present.

To analyze this circuit, we take the passive components, redraw them as on the right in Figure 1 and where G1 = 1 / R1, G2 = 1 / R2, and the term S = j / ( 2*π*F), we use node analysis to derive the transfer function E1 / Eo.

The analysis for the Clapp circuit is rather more involved than it was for the Colpitts circuit so for the sake of clarity, I have omitted it here. However, my handwritten notes of that analysis can be seen at the end of this essay. Try not to strain your eyes.

The end result is an expression of the transfer function in a useful form as follows in Figure 2.

Figure 2 Algebraic expression of transfer function for the Clapp oscillator shown in Figure 1. Source: John Dunn

Note that the denominator of this equation is fourth order. It is a fourth order polynomial because there are four independent reactive elements in the circuit, L1, C1, C2 and C3.

Please also note that the order of the polynomial MUST match the number of independent reactive elements in the circuit. If we had come up with an algebraic expression of some other order, we would know we’d made a mistake somewhere.

Graphing the ratio of E1/Eo versus frequency, we see the following in Figure 3.

Figure 3 E1/Eo versus frequency from algebraic analysis. Source: John Dunn

The transfer function of the passive R-L-C network has a pronounced peak at a frequency of 1.62 MHz and a null at a slightly lower frequency. When we run a spice simulation of that transfer function, we find very nearly the same result (Figure 4). I blame the differences on software numerical accuracy issues.

Figure 4 E1/Eo versus frequency from SPICE Analysis. Source: John Dunn

When we let our gain block be a voltage follower—a JFET source follower in the following example—we see oscillation at the frequency of that transfer function peak as shown in Figure 5.

Figure 5 Clapp Oscillator simulation after letting our gain block be a voltage follower. Source: John Dunn

The algebraic derivation of the Clapp oscillator transfer function is shown in handwriting in Figure 6.

Please forgive the handwriting. I just didn’t have the patience to turn this into a printout.

Figure 6 John Dunn’s transfer function derivation. Source: John Dunn

John Dunn is an electronics consultant, and a graduate of The Polytechnic Institute of Brooklyn (BSEE) and of New York University (MSEE).

Related Content

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• Emitter followers as Colpitts oscillators
• Simulation trouble: Bode plotting an oscillator
• Oscillator has voltage-controlled duty cycle

The post Clapp oscillator appeared first on EDN.

AlixLabs AB of Lund, Sweden — which was spun off from Lund University in 2019 and has developed the Atomic Layer Etching (ALE) Pitch Splitting technology (APS) — is participating at SEMICON Japan 2024 at Tokyo Big Sight (11–13 December), marking the public debut for its 300mm wafer process chamber. Its Made in Sweden APS (ALE Pitch Splitting) tools are aimed at allowing the semiconductor industry to scale down to sub-7nm manufacturing processes in a more sustainable way, and is positioned as an alternative to costly double patterning or EUV (extreme ultraviolet) solutions...

Automotive technology firm Valeo and ROHM Semiconductor are collaborating by using their combined expertise in power electronics management to optimize next-generation power modules for electric motor inverters. As a first step, ROHM will provide its 2-in-1 silicon carbide (SiC) molded module TRCDRIVE pack to Valeo for future powertrain solutions...

Sheffield University spin-off Phlux Technology —which designs and manufactures 1550nm avalanche photodiode (APD) infrared sensors — has won an Institute of Physics (IOP) Business Start-Up Award 2024. Presented at the Houses of Parliament in London, the award celebrates young companies leveraging physics for innovation and impact. It recognized Phlux’s Aura family of Noiseless indium gallium arsenide (InGaAs) infrared (IR) sensors, which is said to have set new standards for sensitivity and performance in optical systems such as LiDAR, laser range finders, and optical fiber communications test equipment...

As a genre, DACs are low power devices with power and current output capabilities limited to the milliwatt and milliampere range. There is, of course, no fundamental reason they can’t be teamed up with suitable power output stages, which is indeed common practical practice. Problem solved.

Wow the engineering world with your unique design: Design Ideas Submission Guide

But just for fun, this design idea takes a different path to power by merging a venerable (the “L” stands for “legacy!”) LM337 regulator into a simple (just two generic active chips) 8-bit PWM DAC to obtain a robust 1.5-A capability. It also enjoys the inherent overload and thermal protection features of that time-proven Bob Pease masterpiece.

As an extra added zero cost feature, output voltage accuracy is (mostly: ~90%) determined by the + 2% (guaranteed, typically much better) precision of the LM337 internal voltage reference, rather than relying on the sometimes-dodgy stability of a logic supply rail as basic PWM DACs often do.

Figure 1 shows the circuit.

Figure 1 LM337 joins forces with 4053 CMOS switch to make a macho PWM DAC.

 Metal gate CMOS SPDT switches U1a and U1b accept a 10-kHz PWM 5v signal to generate a +1.25 V to -8.75 V “ADJ” control signal for the U2 regulator. ADJ = +1.25 V causes U2 to output 0 V. It has always struck me somehow strange that a negative regulator like the 337 sometimes needs a positive control signal (in this case for Vout less negative than -1.25 V), but it does. ADJ = -8.75 V makes it make -10 V. 

U1c generates an inverse of the PWM signal, providing active ripple cancellation as described in “Cancel PWM DAC ripple with analog subtraction.”

Current source Q1 reduces zero offset error by nulling the ~65 µA (typical) ADJ pin bias current. The feedback loop established via R2 and R3 makes full-scale -10 V output proportional to U2’s internal reference as previously mentioned.

This does, however, make output voltage a nonlinear function of PWM duty factor with functionality (DF from 0 to 1): Vout = -1.25 DF / (1 – 0.875 DF) as graphed in Figure 2.

 Figure 2 Graph of Vout (0 V to -10 V) versus the PWM duty factor (0 to 1).
[Vout = -1.25 DF / (1 – 0.875 DF)]

 Figure 3 plots the inverse of Figure 2, yielding the PWM DF required for a given Vout.

 Figure 3 Graph of the PWM duty factor (0 to 1) versus Vout (0 V to -10 V).
[PWM DF = Vout / (0.875*Vout – 1.25)]

For the corresponding 8-bit PWM setting Dbyte = 256 DF = 256 Vout / (0.875*Vout – 1.25).

The negative supply rail (V-) can be anything between -13 V (to accommodate U2’s minimum headroom requirement) and -15 V (in recognition of U1’s maximum voltage rating). DAC accuracy will be unaffected. 

U2 should be adequately heatsunk as dictated by heat dissipation equal to output current multiplied by the V- to Vout differential. Up to double-digit Watts are possible. The 337s go into thermal shutdown at junction temperatures above 150oC, so make sure it will pass the wet-forefinger-sizzle “spit test!”

Stephen Woodward’s relationship with EDN’s DI column goes back quite a long way. Over 100 submissions have been accepted since his first contribution back in 1974.

 Related Content

• Cancel PWM DAC ripple with analog subtraction
• Cancel PWM DAC ripple with analog subtraction—revisited
• Cancel PWM DAC ripple with analog subtraction but no inverter
• Cancel PWM DAC ripple and power supply noise
• Fast PWM DAC has no ripple
• Fast-settling synchronous-PWM-DAC filter has almost no ripple
• Minimizing passive PWM ripple filter output impedance: How low can you go?

The post 0 V to -10 V, 1.5 A LM337 PWM power DAC appeared first on EDN.

I wanted to share a reminder that you don’t need a dedicated workbench, shop, or even a large table to work on electronics projects. I don’t have the space or budget for a full setup, so I work at my desk while watching videos. However, constantly running back and forth to grab parts was frustrating and made setup and cleanup take forever. To solve this, I built a portable workbench that I can easily place on my desk or store on a shelf when not in use. Here’s what I did: I used glued wood planks cut to 40cm x 50cm. Made a small shelf for my soldering station by gluing wood scraps together, then secured it with screws. Added a hole at the back for the power supply, handles for easy carrying, and rubber feet to keep it stable on any surface. Screwed my soldering equipment onto the board so everything stays in place. Now, I can set up and start working in seconds, and so far, it’s been a game-changer! front view top view shelf view submitted by /u/Alfagun74 [link] [comments]