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Пам'яті Федіра Федоровича Дубровки kpi чт, 08/14/2025 - 21:40

New AI upscaling tech points to a 2026 mobile graphics future driven by on-chip inference.

Digital acquisition instruments like oscilloscopes and digitizers are incorporating increasingly large acquisition memories. Acquisition memories with lengths in the gigasample (GS) range are commonly available. The advantage of long-acquisition memories is that they can capture longer-time records. They also support higher sampling rates at any given record duration, providing better time resolution.

The downside of these long records is the time required to analyze them. Most users couple the instrument to a host computer and transfer the data records to the host computer for post-acquisition analysis.

The longer the record, the longer the transfer time and the slower the testing. Many instruments have added tools to allow internal analysis within the instrument, allowing only the results of the analysis to be transferred instead of all the raw data. This can save a great deal of time during testing. This article will investigate the use of several of those analysis tools.

Case study: The startup of an SMPS

Testing the startup of a switched-mode power supply (SMPS) provides an example of a relatively long acquisition. Figure 1 shows an example of a 10-ms acquisition covering the startup of an SMPS.

Figure 1 A 10-ms acquisition showing the startup of an SMPS, including the drain-to-source voltage (channel 1-yellow), drain current (channel 2-red), and gate drive voltage (channel 3-blue) of the FET switch. Source: Art Pini

This record, sampled at 250 megasamples per second (MS/s), has 2.5 million samples per channel. That is a lot of data to render on a screen with a 1920 x 1080 pixel resolution. The oscilloscope acquires and stores all the data, but when more than 1920 samples are being displayed, it compacts the displayed data. Rather than just sparse the signal records, which might cause the loss of significant data points, it detects the significant peaks and valleys and includes those values on the display. This enables users to find significant events within the compacted displays.

Basic measurements

There are three acquired waveforms. The drain-to-source voltage (VDS), drain current (ID), and gate-to-source voltage (VGS) of the primary FET switch. The test will look at the variation in these signals as the power supply controller powers up the supply. Some basic measurements of the signal amplitudes are made and displayed. The peak-to-peak amplitudes of VDS and ID, as well as the amplitude of VGS, are shown as parameters P1, P2, and P3, respectively.

The frequency of the VGS signal and the number of edges contained in the acquisition appear as parameters P4 and P5. Amplitude measurements are taken once per acquisition. Time measurements such as frequency, period, width, and duty cycle are made once per waveform cycle. So, the frequency measurement includes all 1163 cycles acquired. This is an example of “all instance measurements.” This feature ensures that every cycle in the signal is captured in the measurement.

Zoom in on the details

All the acquired data is stored in the instrument’s acquisition memory and can be expanded using zoom traces to see the details, as shown in Figure 2.

Figure 2 Zoom traces provide horizontally or vertically expanded views of the acquired traces, allowing detailed study of the elements of each acquired waveform. Source: Art Pini

In the figure, the zoom traces of the acquired waveforms are horizontally expanded and displayed at 5 ms per division, with a horizontal expansion of 200:1. The zoom traces are taken from the area of the acquired waveform highlighted with higher intensity. The SMPS uses pulse width modulation (PWM) to control its output power.

The zoom traces show the variations in the amplitude and duty cycle of the waveforms just after the gap at 456 ms in the acquired waveforms. The zoom traces are locked together to keep the displayed waveform time synchronous. They can be scrolled horizontally or vertically to show the details in any part of the source waveforms.

Finding desired events in long records

The question of locating areas of interest in these long acquisitions has several answers. Histograms of measured parameters can display the range of values and the number of measurements made by the instrument. A measurement track displays any measurement value versus time. The track can be aligned with the source waveform to show where in the acquisition that value occurs. Some instruments offer scanning functions to map where, in the long record, specific values of a measured parameter occur. These features are extremely useful in analyzing long records.

Histograms

A histogram plots the number of measured values occurring in a small range of measured values (known as a bin) against the nominal measured value. It counts the number of measurements in each bin. Figure 3 shows a histogram measuring the duty cycle of the VGS waveform.

Figure 3 The histogram of the duty cycle measurement of the VGS waveform shows the distribution of measured values with a mean value of 28.4%, a maximum value of 38.9%, and a minimum value of 0.3%. Source: Art Pini

The histogram shows the range of values encountered in a measurement. This example shows that the most commonly occurring value of the duty cycle is 31.6%. This is read from the X@peak parameter (P4). The range of duty cycle values is from 0.3 to 38.9%. This data is based on 1164 measurements shown in the total population measurement (totp – P8). How is the location of the maximum value of the duty cycle found? A measurement track matches measurements to a specific cycle in the acquired waveform.

Measurement track

A measurement or parameter track is a waveform comprised of a series of measured parameter values plotted against time at the same sample rate as the source waveform on which the measurement was made. It is time synchronous with the source waveform.

Figure 4 is an example of a measurement track based on the duty cycle at level (duty@lv) measurement of the VGS waveform.

Figure 4 The trace F1 is the track of duty@lv parameter (P1) values over the entire acquisition. It is time synchronous with the trace of channel 3. Source: Art Pini

The track function, located beneath the source waveform, illustrates how the duty cycle of the gate drive signal changes over time during SMPS startup. After a brief gap, it rises steadily until it reaches a plateau, then drops to a relatively stable value.

The parameter maximum (max-P2) reads the maximum value of the duty cycle as 38.59%. The parameter horizontal location of the maximum (x@max-P3) locates the maximum at 3.12 ms after the trigger (zero time). The parameter markers (blue dashed lines) mark these values on the track display. The center of the zoom traces can be set to 3.12 ms, and the zoom traces are expanded about that point to show the specific cycle of each waveform with the maximum duty cycle.

The VGS voltage appears in zoom trace Z3. The duty cycle at level is read for that specific cycle of the VGS signal in parameter P4, confirming that it is the cycle with the maximum duty cycle value. The track function helps locate specific waveform events within the long record without manually scrolling through the whole waveform to find them.

Tracks can show a variety of characteristics, such as peaks, valleys, periodicity, or rate of change. Periodicity in a track of frequency or phase provides information about frequency or phase modulation, respectively. In this example, the track has a nearly linear slope as the controller adjusts the duty cycle. The rate of change is of interest and can be easily measured, as shown in Figure 5.

Figure 5 Using the relative horizontal cursors to determine the rate of change of the duty cycle of the VGS waveform over the linearly changing portion of the track. Source: Art Pini

The relative horizontal cursors read the slope of the waveform between the cursor lines. This value is displayed and highlighted by an orange box in the waveform annotation box for the math trace F1 as 7.03 k% per second (7% per millisecond).

WaveScan—automatic scan and search of long waveforms

The oscilloscope used in this example has a scan and search engine called WaveScan that can locate unusual events in a single capture or scan for a specific measurement event in multiple acquisitions over a long period. WaveScan has over twenty search modes for analog or digital channel acquisition events. Figure 6 shows an example of a search using WaveScan to find all instances of a duty cycle measurement greater than 38%.

Figure 6 Using WaveScan, an automatic search tool, to search the VGS waveform for duty cycle values greater than 38%. Source: Art Pini

The WaveScan setup dialog box shows the search criteria set up to find duty cycle values greater than 38%. WaveScan can search based on measurements, waveform edges, non-monotonic edges, and serial data patterns. A numeric search, such as those on measurements, can be based on values greater, less, than, within a range, outside of a range, or for the rarest events.

In the example, the search is based on measuring the duty cycle at level with values greater than 38%. The search results are marked with red lines on the source trace and appear in the table in the upper left corner. Each event matching the search criteria is listed in the table in the order of occurrence. The maximum duty cycle value of 38.859%, located previously, is item 3. The table entries are hyperlinked to the Zoom trace, and if one is selected, it will center that event in the Zoom trace. In the example, event six is selected. The zoom trace Z1 has been centered on the sixth cycle with a duty cycle greater than 38%, highlighting its location at 3.2295 ms.

Post-acquisition analysis tools

Modern instruments offer longer acquisition times and include a host of tools to aid in analyzing the data generated. Features such as compaction, zoom, histograms, track, and WaveScan enable various analyses and measurements. The tools also augment the measurements by annotating them numerically or graphically on the display. These features enable local analysis, which accelerates testing and reduces the amount of data that needs to be transferred to external computers.

Arthur Pini is a technical support specialist and electrical engineer with over 50 years of experience in electronics test and measurement.

 Related Content

• Why deep memory matters
• Understanding the importance of acquisition memory
• Oscilloscope special acquisition modes
• FFTs and oscilloscopes: A practical guide
• Basic oscilloscope operation

The post Analysis of large data acquisitions appeared first on EDN.

As technology rapidly evolves, deep learning a subset of machine learning that uses neural networks to model and understand complex patterns in data has emerged as a transformative force across industries, powering innovations from autonomous vehicles to intelligent automation;

A deep learning framework is a software library that simplifies building and training neural networks by providing pre-built components like layers, optimizers, and tools for automatic differentiation. A deep learning framework operates in four key stages: model definition involves specifying the neural network architecture using a programming interface; forward propagation processes input data through the network to generate predictions; loss calculation and backpropagation compute errors and adjust weights using automatic differentiation; and optimization trains the model using algorithms like SGD or Adam, followed by deployment to various platforms. These frameworks support both training and inference, enabling smooth transition from experimentation to production.

Major AI applications are powered by well-known deep learning frameworks: Google Translate’s neural machine translation is powered on TensorFlow, whereas PyTorch facilitates OpenAI’s GPT models and Meta’s research. Keras is utilized in the classification of instructional images; MXNet makes it possible for Amazon Alexa to recognize voice; Caffe aids medical image analysis; JAX handles physics simulations and protein modeling; and ONNX helps deploy models across platforms like PyTorch to TensorFlow for edge devices

Here are the top 10 deep learning frameworks-

1. TensorFlow

Developed by Google Brain, TensorFlow is put forward across many consumers as the most famous deep learning framework in 2025. It was first used by Google internally for some research and development projects back in 2015, but after seeing the immense potential of the framework, it was decided that an official public release would be made. It is a highly scalable and flexible framework supporting multiple programming languages and hardware platforms including CPUs, GPUs, and TPUs. TensorFlow sees many applications including image recognition, speech synthesis, and fraud detection. Its lightweight mobile offerings TensorFlow Lite and TensorFlow.js bring AI to phones and browsers.

2. PyTorch

PyTorch, created by Meta AI, is beloved by researchers for dynamic computation and intuitive design. Initiated in 2016 by a group of individuals from Facebook’s AI lab comprising Adam Paszke, Sam Gross, Soumith Chintala, and Gregory Chanan, the framework powers the latest NLP models such as ChatGPT and BERT. It is largely deployed in academic research, autonomous driving systems, and in real-time computer vision applications.

3. Keras

Keras is designed to be a high-level API for easily and quickly building and training neural networks. First made public in 2015 as part of the ONEIROS project (Short for Open-ended Neuro-Electronic Intelligent Robot Operating System).

Being a frontend for TensorFlow, it is great for beginners and rapid prototyping. Because of the simple handling of pre-trained models, Keras is commonly found in tasks involving sentiment analysis, recommendation engines, and medical image classification.

4. MXNet

MXNet excels for multi-GPUs setup, supported now by Apache Software Foundation and Amazon. It is used for real-time object detection in retail, multilingual NLP models, and voice assistants, including Alexa. The fact that it supports multiple languages means it’s an excellent option for global development teams.

5. Caffe

Created by the Berkeley Vision and Learning Center (BVLC), Caffe is a deep learning framework well renowned for its speed and modularity in image processing tasks. It found popular uses with an expressive architecture and efficiently implemented CNNs. Caffe is popular for real-time image classification, facial recognition systems, and visual search engines.

6. JAX

Created by Google Research, JAX is a pretty cool toolkit. It offers NumPy-like syntax combined with automatic differentiation and GPU/TPU adaptations. It can be used for scientific computations, custom ML algorithms, and large-scale training of neural networks.

7. Theano

Theano was one of the first frameworks for deep learning, developed by the Montreal Institute for Learning Algorithms (MILA). It discontinued maintenance after some time. Today, though mostly abandoned, Theano’s legacy still lives in the other popular frameworks like TensorFlow and PyTorch. Theano is still used actively for symbolic differentiation and efficient GPU numerical computation in some academic research.

8. MindSpore

MindSpore, developed by Huawei, is targeted for AI across cloud, edge, and devices. It finds applications in natural language processing, computer vision, and autonomous systems. Due to its favorable attention toward privacy protection and efficient deployment, MindSpore is catching up in sectors like healthcare and smart manufacturing.

9. Deeplearning4j (DL4J)

Developed by Skymind, DL4J is tailored for Java-based enterprise AI solutions. It’s applied in financial modeling, cybersecurity threat detection, and customer churn prediction. Its integration with Hadoop and Spark makes it ideal for big data analytics.

10. Chainer

Developed by Preferred Networks in Japan, Chainer is recognized for its flexibility in defining networks of all kinds. Reinforcement learning for gaming purposes, bioinformatic research, and robotics are ways in which this application develops capabilities. Its “define-by-run” architecture is supposed to allow dynamic learning systems. It is loved by the experimental kinda-AI set.

Conclusion:

The importance of selecting a framework may increase as deep learning continues to influence the technologies of the future. There are several different ecosystems, each with its own unique set of advantages. TensorFlow chose production-grade scalability, while the other chose a research-friendly strategy. The combination of cloud integration, open-source innovation, and hardware acceleration will guarantee that deep learning remains at the forefront of AI advancements across a range of industries well into 2025.

The post Top 10 Deep Learning Frameworks appeared first on ELE Times.

Vibration motors are the silent workhorses behind tactile feedback in wearables and handheld devices. These compact actuators convert electrical signals into physical cues, enriching user interaction. Whether you are prototyping or troubleshooting, understanding their behavior and integration is key to designing responsive, reliable hardware.

Let’s start with the basics: How they generate vibration, and what sets different types apart.

ERM and coin vibration motors

As is often valuable to design engineers, vibration motors can be categorized by form factors to simplify selection and integration. The two primary types are eccentric rotating mass (ERM) vibration motors and coin vibration motors.

ERM vibration motors generate vibration by spinning a mass that is offset from the center of rotation. This off-center mass creates an imbalance, producing the desired vibration effect. These motors typically have a cylindrical form factor, with the rotating shaft and eccentric mass often exposed. Their design is straightforward and well-suited for applications where space constraints are less critical.

Coin vibration motors, sometimes referred to as “pancake” motors, also rely on an offset rotating mass to produce vibration. However, they feature a flat, compact, and fully enclosed form factor. Internally, they contain a short shaft and a flat mass that is offset from the center of rotation, allowing the mechanism to fit within the coin-shaped housing.

Although coin motors operate on the same ERM principle, industry convention typically distinguishes them by form: the exposed cylindrical type is commonly referred to as an ERM vibration motor, while the flat, enclosed type is known as a coin or pancake vibration motor.

Figure 1 ERM and pancake vibration motors generate haptic feedback via eccentric rotating mass. Source: Author

LRA vibration motors

While our primary focus has been on vibration motor form factors, there is another important category worth highlighting: linear resonant actuator (LRA) vibration motors. In terms of external appearance, LRAs often resemble coin vibration motors, sharing the same flat, compact form factor. This visual similarity can be misleading, as the underlying mechanism is fundamentally different.

Unlike ERM motors, which rely on a rotating offset mass driven by a unidirectional current, LRAs operate using a linearly oscillating mass. This mass moves back and forth in a controlled manner, following the principles of simple harmonic motion. Because the direction of movement continuously changes, LRAs require an alternating current (AC) signal with a specific frequency that matches the resonant frequency of the actuator.

This distinction in operating principle allows LRAs to deliver more precise and efficient haptic feedback, making them well-suited for applications where responsiveness and control are critical. Despite their similar form factor to ERM and coin motors, LRAs represent a distinct class of vibration technology.

Figure 2 LRA vibration motor generates haptic feedback via resonant linear actuation. Source: Author

Keep note that there is also a growing category of brushless vibration motors, typically based on brushless DC (BLDC) technology. These motors offer improved durability and efficiency compared to traditional brushed ERM designs, thanks to the absence of mechanical brushes.

While they may share similar cylindrical or coin-like form factors, their internal construction and control requirements differ. Brushless vibration motors are especially useful in high-reliability applications where splendidly long mean time before failure (MTBF) and low maintenance are priorities.

Figure 3 BLDC motors often feature additional wires that enable functions like speed regulation and directional control. Source: Author

How to use actuators

Up next, we take a closer look at how to use these tiny actuators effectively in your designs.

To start with, ERM and coin vibration motors that run on DC can be powered directly from a suitable DC source. But when it comes to haptics—where you want the motor to respond to input—you will probably want to hook it up to a microcontroller. That way, you can control not just the on/off state but also tweak the amplitude and define vibration profiles.

For those seeking integrated driver solutions, ICs such as the NCP5426 offer a reliable and efficient alternative to using a simple BJT or MOSFET.

LRAs, on the other hand, operate on an AC signal and are tuned to a specific resonant frequency. Driving them properly usually means using a dedicated LRA driver to ensure optimal performance.

At this point, it’s worth noting that the DRV2605/DRV2605L from Texas Instruments is a popular motor driver designed for haptic feedback applications. Unlike basic motor drivers, it can generate nuanced vibration patterns, making it ideal for creating tactile feedback that feels responsive and intentional. Thus, it offloads waveform generation from the host processor, simplifying design and saving resources.

Quick note: After reviewing numerous datasheets, a few general trends emerge. Most ERM vibration motors are rated around 3 V, with a starting voltage near 2.5 V and a rated current close to 100 mA at full voltage.

In contrast, most LRAs tend to have a rated voltage of approximately 2 V RMS, a nominal operating current around 150 mA, and a resonant frequency of 150 Hz ±5Hz. That said, consider these figures as ballpark estimates rather than absolutes. Always double-check with the specific datasheet!

Other design considerations

When it comes to mounting vibration motors, they are typically placed within an enclosure or directly onto a PCB. For enclosure-based setups, custom 3D-printed housing can be a convenient way to fasten the motor. If you are mounting the motor to a PCB, many models offer through-hole pins for straightforward soldering. For coin and LRA types, the adhesive backing is usually sufficient for reliable attachment.

As a little extra, here is a handy blueprint for testing/driving a 6-wire vibration motor with integrated driver (Model NFP-BLV3650-FS, for example)

Figure 4 This handy little circuit tests and runs most vibration motors with internal drivers. Source: Author

Just to round things off, there are numerous ways to integrate haptic feedback into your devices, with vibration motors being one of the most accessible options. Whether you opt for a simple implementation or a more sophisticated approach, adding haptics can significantly elevate your device’s user experience and overall effectiveness.

The insights shared here are intended to serve as a springboard, hopefully helping you incorporate haptic feedback into your designs with confidence and creativity.

T. K. Hareendran is a self-taught electronics enthusiast with a strong passion for innovative circuit design and hands-on technology. He develops both experimental and practical electronic projects, documenting and sharing his work to support fellow tinkerers and learners. Beyond the workbench, he dedicates time to technical writing and hardware evaluations to contribute meaningfully to the maker community.

Related Content

• Baby, You Can Drive My BLDC
• Haptic or Vibration motors – A Quick Look
• Single-phase BLDC motor minimizes noise, vibration
• Vibration motor driver IC applies the Freewheel principle
• Motor-driver IC features Hall-element commutation for driving vibration motors

The post Vibration motors: The key to compact haptic solutions appeared first on EDN.

The iconic Etch-a-Sketch, a toy beloved by generations, always had one major limitation: a drawing mistake meant shaking the entire device and starting over from scratch. With the TekkaSketch project, this limitation is overcome thanks to a modern approach that integrates digital functions while preserving the classic aesthetic. The idea stems from observing the original […]

The post TekkaSketch: Reinventing the Etch-a-Sketch with E-Ink and ESP32 Innovation appeared first on Open-Electronics. The author is Boris Landoni

The Ministry of Commerce and Industry has clarified that no additional tariffs have been imposed on Indian exports to the United States in the pharmaceutical and electronics sectors. As per a written reply in the Lok Sabha, this announcement would bring relief to exporters in these sensitive sectors facing concerns about possible duty hikes.

In the meantime, the Ministry said that other goods have been subjected to a reciprocal tariff of 25% from August 7 and that this applies to around 55% in value of India merchandise exports to the US. Furthermore, on August 27, the ad valorem duty of 25% on certain goods will come into being.

The government undertakes consultations with stakeholders, including exporters, MSMEs, and the industry, for the assessment of these measures. It was emphasised that top priority will continue to be given to protecting the interest of farmers, workers, entrepreneurs, and all sections of the industry.

On the trade diplomacy front, India and the US are continuing negotiations on a Bilateral Trade Agreement (BTA) aimed at enhancing market access, reducing tariff and non-tariff barriers, and improving supply chain integration. Talks began in March 2025, with five rounds completed so far the latest held in Washington from July 14 to 18. The US delegation is set to arrive in India by the end of August for the sixth round of Bilateral Trade Agreement negotiation.

The Department of Commerce is closely monitoring the situation to evaluate the potential repercussions of the tariff changes and is working on strategies to mitigate any adverse effects. Measures such as export promotion and market diversification are being explored to support affected industries.

The post Govt Confirms Tariff Stability for Indian Pharma, Electronics appeared first on ELE Times.

In a move to boost India’s electronics manufacturing ecosystem, the Union Cabinet has approved the setup of 4 semiconductor fabrication units at Odisha, Punjab, and Andhra Pradesh.

Having a combined investment of around ₹4,600 crore, these projects will generate direct employment for about 2,034 people and provide a great fillip towards making the country self-reliant in the semiconductor field. This initiative comes under the India Semiconductor Mission (ISM), which is one of the flagship programmes created primarily to lessen the import dependence and create strong manufacturing capabilities within the country.

According to the India Semiconductor Mission, the Union Cabinet approved the setup of four semiconductor manufacturing projects-

Odisha will host two plants in Bhubaneswar’s Info Valley. SicSem Pvt Ltd, in collaboration with UK’s Clas-SiC Wafer Fab Ltd, will set up India’s first commercial compound semiconductor fab to produce 60,000 wafers and 96 million packaged units annually, for use in defence, EVs, railways, chargers, and renewable energy. The second unit, by 3D Glass Solutions Inc., will establish an advanced packaging and embedded glass substrate facility with annual capacity of 69,600 glass panels, 50 million assembled units, and 13,200 3DHI modules for defence, AI, photonics, and high-performance computing.

In Andhra Pradesh, ASIP and South Korea’s APACT Co. Ltd will set up a 96 million unit semiconductor plant for mobile, automotive, and consumer electronics.

In Punjab, CDIL will expand its Mohali facility to produce 158.38 million high-power discrete devices annually, including MOSFETs, IGBTs, and Schottky Bypass Diodes for automotive electronics, EV charging, and industrial use.

According to the Union Minister Ashwini Vaishnaw, these units will cater to both domestic needs and strategic needs, including electronics, telecommunications, defense, and space technologies. Spread across three states, the approved units represent a major infrastructure-building step for semiconductors in India, with a heavy emphasis on job creation, technology innovation, and attracting even more private investment.

Conclusion:

With the approvals, India is decisively charting a course that places it among the global semiconductor firms. Through a mix of value creation through strategic investments, job creation, and technology capacities, the government wants to strategically position itself to meet domestic demand as well as become a deserving assembly hub on the world scale. Industry analysts consider that these projects might be the very foundation that leads toward a self-sustaining semiconductor ecosystem, capable of lessening import dependence and setting India on the pathway of being a key player in future-ready technologies.

The post Union Cabinet Approves Strategic Semiconductor Projects to Strengthen India’s Chip Ecosystem appeared first on ELE Times.

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Kioxia says its UFS version 4.1 embedded flash memory device can improve performance and diagnostic capabilities in automotive and data center applications.

By strategically incorporating artificial intelligence throughout their networks, telecom companies can meet demand for better performance, streamlined operations, and improved customer experiences.

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Several Design Ideas (DIs) have employed the subject ICs to implement programmable current sources in an innovative manner [Editor’s note: DIs referenced in “Related Content” below]. Figure 1 shows the idea.

Figure 1 Two independent current sources, one for loads referenced to the more negative voltage, and the other for those to the more positive one. The Isub current sources control the magnitudes of the currents delivered to the loads.

Wow the engineering world with your unique design: Design Ideas Submission Guide

Each of the ICs works by enforcing Vref = 1.25 V (±50 mV over load current, supply voltage, and operating temperature) between the OUT and ADJ terminals. The Isubs are programmable current sources (PWM-implemented or otherwise) which produce voltage drops Vsubs across the Rsubs.

Given that there are ADJ terminal currents IADJ ( typically 50 µA and maxing out at 100 µA ), the load currents can be seen to be:

[Vref  + ( IADJ – Isub ) · Rsub] / Rsns

When Isub is 0, the load current is at its maximum, Imax, and its uncertainty is a mere ±50 mV / 1250 mV = ±4%. But when Isub rises to yield a desired current of Imax/10, the uncertainty rises to ±40%; the intended fraction of 1.25 V is subtracted, but the unknown portion of the ±50 mV remains. If Imax/25 is desired, the actual load current could be anywhere from 0 to twice that value. Things are actually slightly worse, since the uncertainty in IADJ is a not-insignificant portion of the typically few-milliamp maximum value of Isub.

Circumnavigating the accuracy limitations of reference voltages

Despite the modest accuracy of their reference voltages, these ICs have the advantage of built-in over-temperature limiting. So it’s desirable to find a way around their accuracy limitations. Figure 2 shows just such a method.

Figure 2 Two independent current regulators. The Isub magnitudes are programmable and are often implemented with PWMs. Diodes connected to the ADJ terminals protect the LM ICs during startup. The 0.1-µF supply decoupling capacitors for U1 and U3 are not shown.

The idea of the three-diode string was borrowed from the referenced DIs [Editor’s note: in “Related Content” below]. It ensures that even for the lowest load currents (the LM ICs’ minimum operating is spec’d at 10 mA max.), the ADJ terminal voltages needn’t be beyond the supply rails.

The OPA186 op-amp’s input operating range extends beyond both supply rails (a maximum of 24 V between them is recommended), and its outputs swing to within 120 mV of the rails for loads of less than 1 mA.

The maximum input offset voltage, including temperature drift and supply voltage variations, is less than ±20 µV. An input current of less than ±5 nA maximum means that for Rsubs of 1 kΩ or less, the total input offset voltage is 2000 times better than the LMs’ ±50 mV.

Placing the LM ICs in this op-amp’s feedback loop improves output current accuracy by a similar factor (but see addendum).

Adapting Jim Williams’ design for a current regulator

Jim Williams of analog design fame published an application note placing the LM317 in an LT1001-based feedback loop to produce a voltage regulator. Nothing prevents the adaptation of this idea to a current regulator. The LT1001’s typical gain-bandwidth (GBW) product is 800 kHz, almost exactly the 750 kHz of the OPA186, so no stability problems are expected. And there were none when the LM317 circuit was bench-tested with an LM358 op amp (GBW typically 700 kHz), which I had handy.

Just as you would with the Figure 1 designs, make sure the LM ICs are heatsinked for intended operation. Enclosing them in a feedback loop won’t help if their over-temperature circuitry kicks in. But under the temperature limit, this circuit increases not only load current accuracy, but also the IN-terminal impedances and the rejection of both the power supply and the LM’s references’ noises.

Note that some of the reduction in reference voltage error can be traded off to reduce power dissipation by making the Rsns resistors small. You can also convert the design to a precision voltage regulator by replacing the three-diode strings with a resistor and moving the load to between the OUT terminal and its Rsns resistor’s supply terminal.

Addendum

There’s a missing term in the equation given for load current. In Figure 2, the unknown and unaccounted-for amount of ADJ terminal current is added to the load current.

Considering that the LMs’ minimum specified operating current (see the LM317 3-Pin Adjustable Regulator datasheet and LMx37 3-Terminal Adjustable Regulators datasheet)—and therefore the minimum current through the load—is 10 mA at 25°C, the ADJ maximum of 100 µA is small potatoes. Still, there might be applications where it would be desirable to account for it. Figure 3 is a possible solution, although I’ve not bench-tested it.

Figure 3 Replacing the ADJ terminal-connected diodes with JFETs preserves startup protection for the LM ICs.

The ‘201 and ‘270 JFETS route the ADJ terminal current through the Rsns resistors where it can be recognized and accounted for as part of the current that passes through the load. Cheaper bipolar transistors (which would reroute almost all IADJ) could be used in place of the JFETS, but that would require an additional diode in series with the three-diode string.

Christopher Paul has worked in various engineering positions in the communications industry for over 40 years.

Related Content

• Cross connect complementary current sources to reduce self-heating error
• A negative current source with PWM input and LM337 output
• PWM-programmed LM317 constant current source

The post Improve the accuracy of programmable LM317 and LM337-based power sources appeared first on EDN.

Very on-budget setup. What do you think I should add next? (I've already saved some space for a fume extractor). submitted by /u/GamingVlogBox [link] [comments]

k-Space Associates Inc of Dexter, MI, USA — which produces thin-film metrology instrumentation and software — says that its new kSA RHEEDSim reflection high-energy electron diffraction (RHEED) simulation software is now available for both labs and classrooms...

ClassOne Technology of Kalispell, MT, USA (which manufactures electroplating and wet-chemical process systems for ≤200mm wafers) is providing its Solstice S8 single-wafer processing system to Applied Optoelectronics Inc (AOI) of Sugar Land, TX, USA, a designer and manufacturer of optical components, modules and equipment for fiber access networks in the Internet data-center, cable TV broadband, fiber-to-the-home (FTTH) and telecom markets. The system will further strengthen AOI’s capabilities for producing optoelectronic components that power high-speed data and communications infrastructure...