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An EDN Design Idea (DI) presented a discussion of how to increase the resolution of an ADC by adding a non-deterministic, zero-mean, Gaussian noise dither waveform to a signal to be converted; then, oversampling the sums, and low-pass filtering (thereby averaging) the ADC conversions. (As noted, a filter that optimally removes out-of-band high-frequency dither noise is generally more complex than a simple averager.)

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Conversions are executed at a rate of M times that are required to satisfy the Nyquist condition. Low-pass filtering them offers an increase in resolution of a factor of M and of B = log2(M) bits.

The signal at the filter output has negligible energy above the Nyquist frequency, and so only every Mth output of the filter needs to be sampled in a process known as decimation. Even though the resolution of the conversions has been increased by a factor of M, the signal-to-quantization noise ratio has not improved by the same amount. Because there is still non-deterministic noise present below the Nyquist frequency, it turns out that the signal-to-quantization noise ratio has improved only by a factor of sqrt(M) and by sqrt(B) bits.

But what if the signal were DC and the dither were known, deterministic, and repeated every M samples? The addition of dither-associated noise could be avoided if a judiciously selected dither waveform were added to the signal to be converted and its mean subtracted from the average of M conversions. A simple averager would suffice for the filter. (And if the dither were zero-mean, there would be nothing to subtract!) The advantage of this approach would be that the signal-to-quantization noise ratio would be improved by the same amount as the resolution.

So, what might constitute a “judiciously selected” dither waveform? I won’t keep you in suspense: a sawtooth whose peak-to-peak amplitude is an odd integral multiple of the size of the least significant bit (LSB) of the ADC fits the bill. Why only “odd”? Let’s see why the odds work and why the evens are not as good choices.

In examining the effects of dithering, it’s convenient to work with integer values. For example, let’s assign the smallest possible ADC conversion step size value not to 1 as is traditional, but to M, which is also the number of conversions to be averaged to produce an output. Consider the case of M equal to 64.

Accordingly, all ADC conversions are integral multiples of M: 0, 64, 128, etc., whereas the dither ramp takes on the values of d = 0, 1, 2… 63. Each dither value is added to an input value of (for example) 42, and each sum is converted.

There will be 42 conversions of value 64, and 22 conversions of value 0. The average is 42. We have our increase in resolution! This works for input signals of 0, 1, 2… and up to and well beyond 63.

It’s limited only by the input conversion range of the ADC. Notice that some very large input signals, which by themselves are within that conversion range, will, when added to portions of the dither waveform, be moved above that range. In such cases, the averaging process will yield incorrect results. These input values are in the “dither-disadvantaged” range.

For dither to be of value, it must be added to the signal prior to A-to-D conversion; that is, the dither is an analog signal. But analog or digital, a question arises as to its optimal peak-peak range. Should it take on exactly the values discussed above? Or should each of these values be multiplied by some number? An Excel program was written to answer this question by examining sets of signals plus dither of the form of Expression (1):

S + si + dk  · Aa  (1)

Table 1 describes each variable.

Table 1: The variables in Expression (1) that an Excel program was built around to examine sets of signals plus dither.

Expression (1) is evaluated for the full range of si for every given Aa. ADC conversions yielding multiples of 64 are determined for each value of dk.

These conversions are averaged, added to 31.5, and the sum converted to an integer. The number of errors ei,a (0, 1, 2…) in units of 1/64 of an LSB are determined by subtracting this result from S + si.

The errors are then graphed against si for each peak-peak dither amplitude Aa.

This eye chart appears in Figure 1. Confusing, impressive, or both, it’s difficult to get too much useful information out of it. But it’s clear that even though there are errors in most cases, their magnitudes are small compared to the resolution of a single ADC conversion; useful resolution enhancement has been achieved.

Figure 1 An eye chart with the errors of dithered input signals of amplitudes 0 to 63 for and ADC whose LSB is 64.

To derive more useful information so that the best values of Aa can be identified, some additional calculations are performed. For each Aa, the ei,a are squared, summed over all i, and the square root of the average of the sum is taken to produce the rms error erms. This provides a figure of merit for each scaled peak-peak range Aa of dither. erms is graphed against Aa in Figure 2.

Figure 2 The RMS errors of all input signals with dither added, providing a figure of merit for each scaled peak-peak range Aa of dither.

What is clear from this graph is that zero errors can be obtained if the peak-to-peak dither amplitude is an odd multiple of the ADC conversion LSB. To understand why this happens, consider multiplying dither elements -31.5, -30.5… 31.5 by an odd integer and taking the modulo M = 64 portion of the products.

Surprisingly, you’ll find every number in the basic dither sequence of 0, 1, 2… 63. This gives full coverage to every possible value of input S + si. But why aren’t even multiples error-free?

The modulo 64 of products with even integer multiplicands are even numbers only; the odd elements of the basic sequence are missing. And when Aa is not an integer, the rms errors are generally (although not always) even larger. It could be challenging to generate an analog signal whose range is an exact odd multiple. To minimize the error due to an inexact dither amplitude, we might skip the choice of Aa equal to 1 and choose a multiplier of 3 or 5.

A suitable circuit for generating and using a non-zero mean dither waveform is shown in Figure 3.

Figure 3 A suitable circuit for generating a non-zero mean dither waveform.

At the start of a string of conversions, d2 is set to 0 V to disable M1 while d1 is connected to a reference voltage Vref, such as the one used by the ADC. This allows C1 to begin to charge.

After the last conversion, d1 is left open or grounded, and d2 is set high to enable the MOSFET and quickly discharge the capacitor. Because the peak value of the dither voltage is such a small portion of Vref, what would normally be a signal involving a negative exponent of time is well-approximated as a linear ramp of:

Vref · t / T, where T = R1 · C1

Assuming that the M conversions are equally spaced in time and last for Tsam seconds, T is selected so that the desired Aa is equal to:

Aa = Vref · Tsam / T

The intended signal is obviously not zero-mean. And there is also a small amount of charge injection into C1 when the MOSFET shuts off due to that device’s parasitic capacitances. (A MOSFET with minimal capacitances and a fairly large C1 will work together to limit the size of the charge injection voltage offset.)

Fortunately, even a simple calibration scheme that converts known small and large signals and fashions a best-fit linear correction out of these renders the offsets inconsequential. Note that the dither waveform is subtracted from rather than added to the input signal. This means that the smallest rather than the largest input signals that alone would be within the ADC conversion range are now the ones in the dither-disadvantaged range. If this is of concern, The R resistor connected to ground in Figure 3 can be replaced with a resistor divider presenting the same resistance as R and driven by Vref. A small division ratio is chosen to ensure that all ADC inputs are positive. This returns the dither-disadvantaged range to the larger of all possible ADC conversions. 

The increase in resolution should not be confused with improvements in accuracy; no ADC is ideal. All have integral and differential non-linear errors.

A means has been presented of generating a dither waveform and employing a method using it to enhance the resolution and signal-to-quantization noise of ADC conversions by a factor M, where M is the number of conversions per sample of a DC input signal. A simple calibration technique is required involving the use of ADC conversions of known small and large signals to afford gain and offset error compensation. It should be noted that the application of dither to increase ADC resolution is still, to some extent, at the mercy of the ADC’s accuracy.

If we wish to consider AC input signals rather than only DC ones, it would be possible to digitally subtract the dither value associated with each conversion from that conversion. Perhaps an averager would still suffice as the filter, perhaps not. Perhaps overall performance improvement would not be as good as with a DC signal, or maybe it would. I’ll do some further analysis, but I also invite comments on the matter. 

With AC signals, we don’t have the luxury of waiting for the capacitor in the sawtooth generator to discharge; sampling should be at an uninterrupted, constant rate. Instead of a sawtooth, a triangle wave of the same peak-to-peak amplitude would work.

It could be created with a square wave driving an R1-C1 lowpass filter whose output is capacitively coupled to the unity gain op amp input of Figure 3 in place of the sawtooth generator.

This input would be referenced through a large resistor to ground or to a DAC voltage within the op-amp’s common-mode input range. Dither-disadvantaged ranges might now exist at both extremes of the ADC conversion range. Dealing with such ranges was discussed with sawtooth dither, and the same method can be employed with the triangular waveform. Successive sets of M conversions would occur on rising and on the falling ramps of the triangle wave. The triangular dither waveform would work with DC signals, too, and has the advantage of eliminating MOSFET charge injection.

But with or without a dither waveform, annoying artifacts can arise whenever there is correlation between the periods of the conversion rate and the AC input signal. It is expected that with the dither discussed, artifacts would be M times smaller than without dither.

A known solution to the artifacts problem is to add a small, random analog dither waveform. This will, of course, have a negative impact on signal-to-quantization noise, but the tradeoff may be worth it. I suspect that the magnitude of the new dither should be the size of the ADC’s LSB, but once again, I will investigate, and I do invite comments.

Acknowledgements

I’d like to acknowledge significant contributions to the development and readability of this DI by someone who wishes to remain anonymous.

 Christopher Paul has worked in various engineering positions in the communications industry for over 40 years.

 Related Content

• Increasing bit resolution with oversampling
• Frequency dithering enhances high-performance ADCs
• Dithering increases dynamic range in digital-radio system
• Analyzing ADC Noise Impacts on Wireless System Performance

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The automotive industry is continuing its transition from proprietary automotive serializer/deserializer (SerDes) solutions to an interoperable ecosystem established by the Automotive SerDes Alliance and its first open-standard ASA Motion Link (ASA-ML). ASA-ML is now being implemented by OEMs and Tier 1 suppliers because it provides an asymmetric high-speed communications standard that connects the increasing number of cameras, sensors and displays used in In-Vehicle Networking. Microchip Technology announced a significant milestone with AVIVA Links, an automotive company delivering advanced multi-Gigabit vehicle infrastructure for ADAS and IVI systems, demonstrating that ASA-ML chipsets from multiple vendors can interoperate seamlessly to deliver scalable, high-speed connectivity. This interoperability between major semiconductor suppliers underscores the viability of the ASA-ML ecosystem and its growing role in the automotive industry.

The Automotive SerDes Alliance has more than 175 members, including OEMs such as BMW, Ford, GM, Hyundai Kia Motor Company, Nio, Renault/Ampere, Stellantis, Volvo and Xiaopeng Motors. The multi-vendor ecosystem is actively collaborating to bring ASA-ML enabled systems to the market, addressing the rapid growth of Advanced Driver Assistance Systems (ADAS) and In-Vehicle Infotainment (IVI) applications.

“Microchip is a market leader in automotive networking and connectivity, and achieving robust ASA-ML interoperability with AVIVA Links—who has announced a pending acquisition by NXP—is a pivotal moment for the Automotive SerDes Alliance and a clear signal to the market,” said Kevin So, vice president of Microchip’s communications business unit. “This collaboration highlights the benefits of a multi-source, open standards approach and gives automotive OEMs and Tier 1 suppliers the confidence to design their next-generation ADAS architectures around ASA-ML, knowing they have a scalable, robust and secure connectivity standard backed by leading semiconductor suppliers.”

The ASA-ML standard supports asymmetric high-speed video, control and data transmission up to 16 Gbps, offering a scalable and forward-looking solution. To achieve ADAS L2 and L2+ autonomous-level applications, an increasing number of cameras and sensors must be added into vehicles. These applications require the ASA-ML standard’s scalability, architectural flexibility and interoperability benefits, further driven by the availability of multi-vendor, high-bandwidth connectivity solutions that reduce reliance on proprietary solutions.

“AVIVA Links is focused on delivering advanced connectivity and enabling standards-based, interoperable solutions for the next generation of automotive systems,” said Kamal Dalmia, CEO of AVIVA Links.  “Proving interoperability with Microchip’s ASA-ML SerDes chipset is an important milestone for the automotive industry, and together with our pending acquisition by NXP, will further drive confidence in ASA-ML adoption at OEMs and Tier 1s.”

The post Microchip and AVIVA Links Achieve ASA-ML Interoperability, Accelerating Open Standards for Automotive Connectivity appeared first on ELE Times.

STMicroelectronics and SP Group (SP) have commenced operations for Singapore’s largest industrial district cooling system at STMicroelectronics’ (ST) Ang Mo Kio TechnoPark. The event was inaugurated by Ms. Low Yen Ling, Senior Minister of State, Ministry of Trade and Industry and Ministry of Culture, Community and Youth.

The system is expected to reduce carbon emissions by up to 120,000 tonnes per year and enable 20 per cent savings on cooling-related electricity consumption. It will also repurpose over half a million cubic meters of water each year by using reject reverse osmosis water, previously used in ST Cooling Towers, to support the new district cooling operations.

This marks ST’s first use of district cooling at a manufacturing facility and will strengthen ST’s commitment to be carbon neutral by 2027.

“The deployment of Singapore’s largest industrial district cooling system at our Ang Mo Kio TechnoPark demonstrates our commitment to pioneering energy-efficient solutions that reduce carbon emissions and conserve resources. This achievement strengthens our partnership with Singapore in advancing its national sustainability goals,” said Rajita D’Souza, President of Human Resources and Corporate Social Responsibility at STMicroelectronics. “By integrating advanced technologies like the district cooling system, we are driving a smarter, more sustainable future — showcasing how industry leadership and environmental stewardship align to create lasting value for our business, communities, and the planet.”

“SP Group’s strategic partnership with STMicroelectronics marks a pivotal milestone in our nation’s transition towards a low-carbon future. This project showcases how collaborative innovation can transform urban infrastructure to deliver sustainable, energy-efficient solutions. District cooling will continue to play a vital role in Singapore’s net-zero ambitions, enabling carbon emissions reduction and enhancing energy resilience across industrial and urban developments,” said Stanley Huang, SP’s Group Chief Executive Officer.

Technical details of the district cooling system

Designed, built, owned, and operated by a joint venture between SP and Daikin Airconditioning (Singapore), the system has an installed capacity of up to 36,000 refrigeration tonnes (RT). It delivers continuous chilled water to cool both manufacturing and office spaces via a centralized closed-loop pipe network replacing individual chillers in each building. The total area served by the system is approximately 90,000 square metres.

Chillers in series counterflow configuration reduce the energy required to cool the water. This ensures an efficient and reliable 24/7 operation, with remote monitoring capabilities augmenting the operations team on site to come.

“This partnership with SP reflects Daikin’s commitment to delivering advanced, energy-efficient solutions that go beyond immediate operational needs. Our goal is to contribute to a more sustainable built environment, where technology plays a key role in enhancing resilience, reducing environmental impact, and supporting Singapore’s long-term climate ambitions,” said Chua Ban Hong, Managing Director at Daikin Airconditioning (Singapore).

Additionally, the new installations free up around 4,000 square meters of space at Ang Mo Kio TechnoPark, which will enable ST to install other equipment contributing to environmental impact mitigation. This includes perfluorocarbon (PFC) abatement equipment, with near-future plans for additional water reclamation systems and volatile organic compounds (VOC) abatement as part of its ongoing sustainability efforts.

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Bluetooth Low Energy, Thread, Matter and proprietary protocols come together in a secure, feature-rich platform for supporting evolving standards, interface needs and market demands

As connectivity standards and market needs evolve, upgradeability has become essential for extending device lifecycles, minimizing redesigns and enabling differentiated features. To solve this challenge, Microchip Technology has released the highly integrated PIC32-BZ6 MCU that serves as a common, single-chip platform to reduce development cost, complexity and time-to-market for multi-protocol products featuring advanced connectivity and scalability.

“The PIC32-BZ6 MCU stands out for its powerful blend of connectivity, integration and flexibility in a single-chip solution,” said Rishi Vasuki, vice president of Microchip’s wireless solutions business unit. “Few devices bring together this breadth of features in a single chip, and we’re already seeing strong tremendous early adopter activity. Customers are leveraging its multi-protocol wireless capabilities, advanced analog features and high I/O to develop smarter, more connected products with greater efficiency.”

RF design for smart devices has become increasingly complex, and wireless solutions typically require multiple chips to add new features or frequent redesigns to support evolving industry standards. The PIC32-BZ6 MCU replaces these multi-chip solutions and reduces the redesign burden with a single, highly integrated chip that removes the complexity of multi-protocol wired and wireless connectivity. The MCU also includes analog peripherals to simplify motor control development, along with touch and graphics capabilities for advanced user interfaces and enhanced memory to support complex applications, heavy workloads and Over the Air (OTA) firmware updates.

The PIC32-BZ6 MCU platform streamlines development of products in the smart home and for automotive connectivity, industrial automation and wireless motor control use cases. Key features include:

• High memory and scalable package choices to support demanding applications and OTA updates: The high-performance MCU includes 2 MB Flash memory and 512 KB RAM and is available in 132-pin ICs and modules with additional pin and package variants planned.
• Multi-protocol wireless networking: Qualified against Bluetooth Core Specification 6.0, the device also supports 802.15.4-based protocols such as Thread and Matter plus proprietary smart-home mesh networking protocols.
• Design flexibility that extends product options and scaling opportunities: Versatile and comprehensive selection of on-chip peripherals goes beyond wireless connectivity and OTA updates to support:

Wired connectivity: Multiple interfaces include two CAN-FD ports for automotive and industrial communication, a 10/100 Mbps Ethernet MAC for high-speed wired connectivity and a USB 2.0 full-speed transceiver for seamless data transfer and PC integration.

Touch and graphics: Incorporate peripherals that enable advanced user interfaces including Capacitive Voltage Divider (CVD)-based touch capabilities with up to 18 channels.

Motor control: Simplifies system development through advanced analog peripherals such as 12-bit ADCs, 7-bit DAC, analog comparators, PWMs and QEI for precise motor position and speed control.

• Security by design to protect applications and IP: Includes immutable secure boot in ROM and an advanced on-board hardware-based security engine supporting AES, SHA, ECC and TRNG encryption.
• Reliability in harsh environments: The device is qualified to AEC-Q100 Grade 1 (125 °C) specifications for automotive and industrial environments.

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Edge AI designs, starting to see a trickle-down effect from AI data centers, increasingly rely on toolchains to keep up with the breakneck speed of AI. So, to bolster the edge AI ecosystem, Infineon Technologies has expanded its edge AI toolchain with the DEEPCRAFT Suite, a set of software, tools, and solutions that help engineers seamlessly integrate AI into their designs.

DEEPCRAFT AI Suite includes an AI Hub with ready models and audio tuning tools. That simplifies the implementation of AI/ML capabilities in edge devices and allows design engineers to either develop their models from scratch or integrate off-the-shelf models.

Figure 1 DEEPCRAFT AI allows developers to bring their own model and convert it for the edge. Source: Infineon

“With the introduction of our DEEPCRAFT AI Suite, we are further expanding Infineon’s Edge AI software ecosystem for unlocking the full potential of edge AI,” said Steve Tateosian, senior VP and GM for IoT, consumer, and industrial MCUs at Infineon.

Take AI Hub, for instance, which Infineon calls a one-stop shop for its Edge AI software offerings. It offers access to more than 50 content resources, including open-source models, Infineon software, tools, and solutions, as well as case studies from industrial, consumer, and automotive applications.

Then there is DEEPCRAFT Studio, which provides support for audio, computer vision, radar, and other time-series data. It facilitates an end-to-end platform for developing robust AI and machine learning models for use at the edge.

Figure 2 DEEPCRAFT Studio includes training and deploying high-performance computer vision models for object detection using advanced YOLO models. Source: Infineon

Additionally, DEEPCRAFT Model Converter in the suite allows developers to optimize both proprietary and open-source models to run on Infineon hardware. It supports popular AI frameworks, including PyTorch, TFLite, and Keras.

Figure 3 This software tool converts, optimizes, and validates AI models to run on the edge. Source: Infineon

Voice and audio solutions in the DEEPCRAFT suite support the development of high-quality, voice-controlled products. These solutions feature always-on listening below 1 mW with very low-latency room conditions, avoiding repeated wake-word prompts and extending battery runtime. Moreover, detection rates exceed 98% in close-talking scenarios with a very low rate of false alarms.

More specifically, DEEPCRAFT Audio Enhancement improves speech intelligibility by removing unwanted noise. Furthermore, DEEPCRAFT Voice Assistant supports natural voice interfaces running locally on edge devices.

The DEEPCRAFT AI Suite is optimized for Infineon’s PSOC microcontrollers—built around Arm Cortex-M processor cores—to facilitate high-performance, low-power, and secure hardware with machine learning (ML) acceleration in edge applications.

PSOC microcontrollers also provide advanced security features, including Infineon Edge Protect Category 4 (EPC4) with PSA Certified L2 and L4 iSE, PCI pre-certification, and a secure enclave to protect designs from concept through manufacturing. Next, a dedicated 2.5D GPU enables responsive, high-quality graphical interfaces at the edge, offering realistic visuals at a fraction of the performance and energy cost of traditional 3D processors.

PSOC microcontrollers are fully supported by ModusToolbox, Zephyr, and DEEPCRAFT AI Suite. ModusToolbox features a number of software stacks—including Bluetooth, Wi-Fi, and USB—along with middleware and libraries that can be used to develop custom applications. Zephyr is a small, yet scalable OS with an architecture that allows developers to focus on applications requiring an RTOS.

At Infineon’s OctoberTech 2025 Silicon Valley event held at the Computer History Museum in Mountain View, California, the German chipmaker displayed the company’s PSOC-based edge AI capabilities in applications like advanced sensing. The booth also showcased the analog front-end for a single-chip ECG sensing solution as well as PSOC powering advanced graphics in an AI vision application.

Related Content

• How Edge AI Transforms IIoT and Enables Industry 5.0
• Google Open-Sources NPU IP, Synaptics Implements It
• An edge AI processor’s pivot to the open-source world
• Open-Source ML Tool Aims To Make Edge AI Accessible To All
• Edge AI: The Future of Artificial Intelligence in embedded systems

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Submissions are now open for the 2025 Product of the Year. Winners will be announced in January 2026 and featured in the January/February 2026 digital issue of Electronic Products Magazine, now presented by EDN.com.

Did your company announce or start shipping a product between November 1, 2024, and October 31, 2025, that represents a significant advancement in technology or its application, an innovation in design, or a gain in price/performance? If yes, tell us about it below.  You may submit separate entries for more than one new product, and there are no fees of any kind. The product description can be just a few lines of key information, plus you can upload datasheets and images. The Electronic Products editors will select 13 winners from these and other products introduced or announced during the year.

Entries must be received by 11:59 p.m. PDT on Monday, November 3, 2025. Contact us at editorial@aspencore.com or gina.roos@aspencore.com with any questions.

/* "function"==typeof InitializeEditor,callIfLoaded:function(o){return!(!gform.domLoaded||!gform.scriptsLoaded||!gform.themeScriptsLoaded&&!gform.isFormEditor()||(gform.isFormEditor()&&console.warn("The use of gform.initializeOnLoaded() is deprecated in the form editor context and will be removed in Gravity Forms 3.1."),o(),0))},initializeOnLoaded:function(o){gform.callIfLoaded(o)||(document.addEventListener("gform_main_scripts_loaded",()=>{gform.scriptsLoaded=!0,gform.callIfLoaded(o)}),document.addEventListener("gform/theme/scripts_loaded",()=>{gform.themeScriptsLoaded=!0,gform.callIfLoaded(o)}),window.addEventListener("DOMContentLoaded",()=>{gform.domLoaded=!0,gform.callIfLoaded(o)}))},hooks:{action:{},filter:{}},addAction:function(o,r,e,t){gform.addHook("action",o,r,e,t)},addFilter:function(o,r,e,t){gform.addHook("filter",o,r,e,t)},doAction:function(o){gform.doHook("action",o,arguments)},applyFilters:function(o){return gform.doHook("filter",o,arguments)},removeAction:function(o,r){gform.removeHook("action",o,r)},removeFilter:function(o,r,e){gform.removeHook("filter",o,r,e)},addHook:function(o,r,e,t,n){null==gform.hooks[o][r]&&(gform.hooks[o][r]=[]);var d=gform.hooks[o][r];null==n&&(n=r+"_"+d.length),gform.hooks[o][r].push({tag:n,callable:e,priority:t=null==t?10:t})},doHook:function(r,o,e){var t;if(e=Array.prototype.slice.call(e,1),null!=gform.hooks[r][o]&&((o=gform.hooks[r][o]).sort(function(o,r){return o.priority-r.priority}),o.forEach(function(o){"function"!=typeof(t=o.callable)&&(t=window[t]),"action"==r?t.apply(null,e):e[0]=t.apply(null,e)})),"filter"==r)return e[0]},removeHook:function(o,r,t,n){var e;null!=gform.hooks[o][r]&&(e=(e=gform.hooks[o][r]).filter(function(o,r,e){return!!(null!=n&&n!=o.tag||null!=t&&t!=o.priority)}),gform.hooks[o][r]=e)}}); /* ]]> */

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NXP Semiconductors unveils its i.MX 952 AI-enabled applications processor for automotive human-machine interfaces (HMIs), in-cabin sensing, and vision applications. This new applications processor leverages NXP’s sensor fusion, powered by the eIQ neutron neural processing unit (NPU), for applications such as driver monitoring, child presence detection, and industrial HMI systems.

The i.MX 952 applications processor uses AI to take inputs from different sensors to deliver more accurate and usable data for improved safety in interior cabin sensing applications and to meet regulatory requirements such as the Euro NCAP. These in-cabin sensing systems are used to determine driver attention levels, ensure proper airbag calibration, and detect a child left alone in a car.

“By combining the data from cameras, UWB, ultrasonic and other sensors, the i.MX 952 SoC enhances the intelligence each system provides to deliver a more intuitive interaction between the driver and car,” said Dan Loop, vice president and general manager, edge microprocessor, NXP, in a statement. “This allows OEMs and Tier 1s to offer additional value beyond safety, such as health monitoring, personalization and more, while scalability with the i.MX 95 family reduces hardware and software total cost of ownership and improves times to market.”

The i.MX 952 also can be used in industrial applications, such as AI-powered surveillance and environment sensing applications, as well as HMI systems. The applications processor leverages AI to provide real-time analysis and anomaly detection across the factory floor, and it supports low-power scale to multi-site monitoring and control from a central office.

The i.MX 952, part of NXP’s i.MX 9 series, is pin-to-pin compatible with the i.MX 95 family. This makes it easier for developers to scale their hardware and software design to meet  different price points with a single platform design, NXP said.

The i.MX 952 features an integrated eIQ Neutron NPU for use with multiple camera sensors and an image signal processor and supports RGB-IR sensors. It delivers low-power, real-time, and high-performance processing through a multi-core application domain with up to four Arm Cortex-A55 cores, and an independent safety domain with Arm Cortex-M7 and Arm Cortex-M33 CPUs. It enables ISO 26262 ASIL B compliant platforms and SIL2/SIL3 compliant platforms in industrial safety-critical environments.

NXP claims the i.MX 952 SoC is the industry’s first automotive and industrial processor with integrated support for local dimming, delivering lower power consumption and improved visibility.

With the iMX 952, in-cabin LCD panels and HUDs use less energy, deliver higher contrast, and enhance outdoor HMI panels by dynamically adjusting brightness for optimal visibility in harsh lighting conditions, NXP said, reducing power consumption and eliminating the need for additional components.

The new SoC also features advanced security. This includes EdgeLock Secure Enclave (Advanced Profile), a hardware root of trust that simplifies the implementation of security-critical functions such as secure boot, secure update, device attestation, and secure device access, based on both classic cryptography and post-quantum cryptography (PQC) to ensure security into the future. Together with NXP’s EdgeLock 2GO key management services, OEMs can securely provision i.MX 952 SoC-based products with credentials for secure remote management of devices deployed in the field, including secure over-the-air updates.

The i.MX 952 applications processor will start sampling in the first half of 2026.

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