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Lattice Semiconductor claims the industry’s first post-quantum cryptography (PQC)-ready FPGAs with the launch of its MachXO5-NX TDQ family. Touted as the industry’s first secure control FPGAs, the MachXO5-NX TDQ family features full CNSA 2.0-compliant PQC support.

Built on the Lattice Nexus platform, these FPGAs target applications such as computing, communications, industrial, and automotive applications, addressing the continued threat of quantum-enabled cyberattacks.

(Source: Lattice Semiconductor)

The MachXO5-NX TDQ FPGA family provides the only complete CNSA 2.0 and National Institute of Standards and Technology (NIST)-approved PQC algorithms (LMS, XMSS, ML-DSA, ML-KEM, AES256-GCM, SHA2, SHA3, and SHAKE) offering robust protection against quantum threats, according to Lattice. Its authenticated and/or encrypted bitstream ensures data integrity and protection against unauthorized access with ML-DSA, LMS, XMSS, and AES256. It features crypto-agility via in-field algorithm update capability and anti-rollback version protection for ongoing alignment with evolving standards, and secure bitstream key management with revokable root keys and sophisticated key hierarchy for PQC and classical keys.

Advanced cryptography features include advanced symmetric and classical asymmetric cryptographic algorithms (AES-CBC/GCM 256 bit, ECDSA-384/521, SHA-384/512, and RSA 3072/4096 bit) for bitstream and user data protection. A device identifier composition engine, security protocol and data model, and Lattice SupplyGuard support provide attestation and secure lifecycle/supply chain management for future-proof, end-to-end security.

The FPGAs also provide hardware root of trust (RoT), delivering a trusted single-chip boot with integrated flash, a unique device secret that ensures distinct device identity, and integrated non-volatile configuration memory and user flash memory with flexible partitioning and secure locking. They also feature comprehensive locking control of the programming interface (SPI, JTAG), side channel attack resiliency, and NIST Cryptographic Algorithm Validation Program (CAVP) compliant algorithms.

In addition, Lattice expanded its RoT-enabled Lattice MachXO5-NX device family with new MachXO5-NX TD devices, offering new density and package options. The new Lattice MachXO5-NX TDQ and MachXO5-NX TD FPGA devices are currently available and are supported by the latest release of Lattice Radiant design software.

The post Lattice sets new standard for secure control FPGAs appeared first on EDN.

Brief intro to vactrols

Vactrols, or both an LED and a light depending resistor (LDR) in a light-tight housing, are found in analog music electronics circuits like audio compressors, voltage-controlled amplifiers (VCAs), voltage-controlled filters (VCFs), and other applications.

Wow the engineering world with your unique design: Design Ideas Submission Guide

Nowadays, analog ICs are used for this purpose, so vactrols have become quite rare. One of their main advantages was and remains the low large signal distortion compared to transistor circuits.

On the other hand, they are slow and sluggish when driven by small control currents and have a nonlinear characteristic curve.

Fortunately, the characteristic curve of the conductance versus control current is more linear than that of the resistance. This is advantageous, for instance, for VCFs with a frequency response proportional to 1/RC. For music electronics applications, however, exponential control of the conductance is preferred since voltage-controlled circuits use the “volt/octave” characteristic, whereby with each volt of additional control voltage, the cutoff frequency of the VCF doubles.

Another advantage of exponential vactrol control is the fact that the LED current never becomes 0 [y= exp(x) > 0] and thus the LDR never reaches its full dark resistance, which has a positive effect on the response time of the LDR.

A vactrol circuit

Usually, a pair of transistors is used to convert a linear control voltage into an exponential current. In the case of a vactrol, however, the pair of transistors can be replaced by the LED itself, which is like any diode a voltage-controlled exponential current source.

For temperature compensation, two matched LEDs are required, similar to the transistor circuit.
Figure 1 shows the simulated circuit of the exponential vactrol control.

Figure 1 An exponential vactrol drive where a reference LED is used to convert a linear control voltage into an exponential current, and two matched LEDs are used for temperature compensation.

The LED2 is operated with Iref = -V/R4. At CV=0, the current in the vactrol LED2 is identical, and the resistance of the LDR is set to the middle of the desired resistance range via Iref, here about 30 µA.

As CV increases, the voltage at the cathode of LED2 decreases, but the voltage between the anode and cathode increases so that the LED current increases exponentially.

With a negative CV, the voltage across LED2 decreases accordingly, so that the LED current decreases exponentially. The range of the LDR resistance is determined by summing amplifier U1’s gain. In practical applications, a range of ~ 1 MΩ (CV = -5 V) to 1 kΩ (CV = +5 V), is used, so that a VCF can be tuned from 20 Hz to 20 kHz.

Thermistor R3 improves the temperature drift of the LED current. Still, the LDR’s temperature dependence remains at approximately 0.2%/K, which makes the vactrol circuit less suitable for high-end VCOs.

For other applications (VCF, VCA), the temperature drift is good enough, and in most cases, the thermistor can be omitted.

Figure 2 shows the simulated resistance curve and LED2 current at 20°C and 40°C.

Figure 2 The simulated resistance curve and LED2 current at 20°C and 40°C.

Practical notes

A small PCB was developed for the circuit. The SMD LEDs are standard white types in a 5730 case. Vactrol LED2 is on the PCB top side and illuminates two GL5537 LDRs, which are arranged at an angle of approximately 45 degrees above LED2.

By slightly bending the LDRs, they can be mechanically trimmed for matching resistance. A small black 3D-printed box and a PCB with black solder mask prevent external light from affecting the circuit. Circuits with two and four LDRs illuminated by one LED have been successfully tested to implement 2nd- and 4th-order VCFs.

Uwe Schüler is a retired electronics engineer. When he’s not busy with his grandchildren, he enjoys experimenting with DIY music electronics.

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• Electroschematics LDR circuits

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It's almost time for you to join us for the 4th day of the 2025 All About Circuits Summit Series. Check out our handy guide to learn about the amazing free content available from industry-leading companies and experts.

🎥 КПІшники — переможці хакатону VR Deminer's Lab kpi вт, 10/21/2025 - 12:52

The first demonstration of scandium aluminium nitride (ScAlN) thin films grown by plasma-enhanced atomic layer deposition PEALD expands application to complex 3D structures, according to a University of Michigan study published in Applied Physics Letters and funded partly by the Army Research Office (W911NF-24-2-0210)...

The device is Melexis’ first dual-input inductive ASSP sensor, purpose-built for demanding automotive applications like steer-by-wire and torque feedback.

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📢 Запрошуємо на Інженерний тиждень «KPISchool» kpi пн, 10/20/2025 - 20:12

Intel has pulled back the curtain on Panther Lake, the first client architecture built on its advanced 18A process node.

Life is rife with dichotomies. Good and evil. Black and white. Up and down. Left and right. And, apparently, Ultrahuman and Ringconn ;-). My previous post detailed my experiences, observations, and conclusions from a week or so evaluating the Ultrahuman’s Ring AIR smart ring, following up on last month’s smart ring introductory overview write-up. This one will cover its also-scheduled-for-shipment-cessation-on-October-21 competitor, RingConn’s Gen 2.

What do I mean by dichotomy in this regard? Well, several of the Ultrahuman weak points were, in contrast, RingConn’s strengths. What did I like the most about the Ultrahuman smart ring? It’s the same thing I liked least about RingConn’s alternative device.

Color shortcomings

Let’s dive into the details, starting with that last nitpick bit, since it matches the ordering cadence from last time. Here again are all three smart rings I initially tested, simultaneously located on my left index finger:

The RingConn Gen 2 is at the right, with the Ultrahuman Ring AIR in the middle and Oura’s Gen3 Horizon at left. Color options specifically selected for my evaluations are as follows:

• RingConn Gen 2: Future Silver
• Ultrahuman Ring AIR: Raw Titanium
• Oura Gen3 Horizon: Brushed Titanium

As mentioned last time, the Ultrahuman ring is the closest match to my wedding band on the left-hand ring finger. The Oura Gen3 Horizon is next in the similarity line, although, as you’ll see in near-future detailed coverage of it, the differentiation from my band is more obvious when it’s standalone on the index finger. And the sketchiest match, at least from the standpoint of the wedding band’s body color, is the RingConn Gen 2, although in exchange, it alternatively does a decent job of accentuating the wedding band’s bright edges:

The irony here is that the original RingConn Gen 1 did come in a duller Moonlit Silver color option, which likely would have been a closer match, but for some unknown reason, the company decided not to continue it into the next-generation offering:

Other folks are apparently displeased with the shinier evolutionary trend, too, and have dulled their Gen 2s using abrasive-side kitchen sponges, Dremels, files, and the like. I’m impressed with the results, although I’m admittedly not sure I’ve got the moxie to follow in their footsteps:

Battery life and other bonuses

From this point forward, pretty much everything else came up roses. I’d bought my ring, gently (and briefly) used, off Mercari (no, I never seemingly learn, but this time the outcome was positive) back in mid-June for ~$200 inclusive of tax, shipping, etc., representing a 33.3% (or more) discount off the normal sale price. Initially, the battery charge level only dropped ~5% per day, translating into a whopping nearly three weeks of estimated between-charges operating life (although I never let it completely drain to see if the discharge rate was truly linear or not). Even now, roughly three months later, the drain is still notably less than 10% per day. And it recharges very quickly.

To the best of my recollection, the ring (originally introduced in August 2024) has also received only one firmware update the entire time I’ve owned it, which installed successfully and drama-free. I really do like RingConn’s direct (vs inductive) charging scheme, which reliably mates the ring to the dock (courtesy of magnetic attraction between the two sets of contacts) and preserves existing dock investments if you change ring sizes:

And the high-end Gen 2 comes with an official (from-RingConn versus third-party) battery case, convenient for use when traveling (for long durations, mind you, given the ring’s inherent lengthy between-charges operating life):

Standard charging docks, factory-bundled with the lower-priced Gen 2 Air (which I’ll cover next), can also be purchased separately for both Gen 2 smart ring models.

The lower-priced, apnea-less alternative

The mainstream Gen 2 smart ring I tested normally sell for $299 or more (minus occasional promotional discounts) on Amazon and elsewhere, and comes in three color scheme options:

• (aforementioned) Future Silver
• Matte Black
• Royal Gold

For $100 more ($399 total), there’s also a (fourth) Rose Gold color option.

RingConn also sells a $199 “Air” version of the Gen 2 smart ring. There are, as far as I know, only two differences between it and the more expensive alternative:

• Only two color options this time: Galaxy Silver and Dune Gold, and
• No sleep apnea measurement and analysis capabilities (which may reflect a reduced sensor or other functional allotment, or may just be a software feature lock-out)

The latter point is one for which I have personal interest, so I’ve spent a fair bit of time assessing it. For one thing, the RingConn Gen 2 is the only smart ring I’m aware of on the market that offers this feature. I tested it a bit; here’s the report I got on September 5, for example:

which closely correlated with the data that came directly from my Resmed CPAP machine:

That said, the comparative results for the next night weren’t quite as synonymous, although they were still “in the ballpark”:

What you’re looking for when comparing results, at least at first, is the AHI (Apnea-Hypopnea Index) number, which Resmed’s software alternately refers to as “Events/hr” in its summary screen. Here’s an overview description, from the Sleep Foundation website:

The Apnea-Hypopnea Index (AHI) quantifies the severity of sleep apnea by counting the number of apneas and hypopneas during sleep. Apneas are periods when a person stops breathing and hypopneas are instances where airflow is blocked, causing shallow breathing. Normal AHI is less than 5 events per hour, while severe AHI is more than 30 events per hour. The AHI guides healthcare professionals in their diagnosis and in determining effective treatment.

A key point to note here: I was using my CPAP machine both nights, which is why the AHI was so low in the first place. To that point, a sleep apnea-assessing smart ring is IMHO of limited-to-nonexistent value once you’ve been diagnosed and treatment is in process, since further apnea is suppressed (assuming your treatment regimen is effective, that is). Anyway, the treatment equipment is likely already reporting the data you need to assess effectiveness. Save the $100 in this case. Conversely, though, as an early-warning indication of potential apnea, which you don’t yet realize you’re suffering from? Given the large number of people who are reportedly sleep apnea-afflicted but don’t yet realize it, from study results I’ve seen, as well as how significantly apnea can health-compromise a person, I’m gung-ho on RingConn’s smart ring for that scenario.

Oh, and before going on, here’s the report that RingConn’s app generates after it’s gotten at least three nights’ worth of sleep data point sets to comparatively assess:

Other observations

Much of what follows echoes what I said about the Ultrahuman smart ring in my previous post and/or in last month’s initial overview piece. Nevertheless, for completeness’ sake:

• It (like others) misinterpreted keyboard presses and other finger-and-hand movements as steps, leading to over-measurement results, especially on my dominant right hand.
• While the Bluetooth LE connectivity extends battery life versus a “vanilla” Bluetooth alternative, it also notably reduces the ring-to-phone connection range. Practically speaking, this isn’t a huge deal since the data is viewed on the phone. Picking up the phone (assuming your ring is also on your body) will prompt a speedy close-proximity preparatory sync.
• Unlike Oura (and like Ultrahuman), RingConn provides membership-free full data capture and analysis capabilities. The company also sells optional extended warranties.
• And the app will also automatically sync with other health services, such as Google Fit and, more recently, its Android Health Connect successor. That said, I wonder (but haven’t yet tested to confirm or deny) what happens if, for example, I’m wearing both the ring and my Health Connect-cognizant (either directly or via the Health Sync intermediary) smartwatches from Garmin or Withings. Will the service endpoint be intelligent enough to recognize that it’s receiving concurrent data from two different sources and either discard one data set or reconcile them, rather than just adding them together?

And with that, a few hundred words shorter than its Ultrahuman predecessor (which in this case definitely isn’t a bad thing from a RingConn standpoint), I’m going to wrap up this write-up.

It turns out I’ve got two different Oura posts coming up; I ended up picking up a gently used Ring 4 to supplement its Gen3 Horizon precursor. Plus, two different smart ring teardowns, as well. So, stay tuned for those. And until then, please share your thoughts in the comments!

—Brian Dipert is the Editor-in-Chief of the Edge AI and Vision Alliance, and a Senior Analyst at BDTI and Editor-in-Chief of InsideDSP, the company’s online newsletter.

Related Content

• The Smart Ring: Passing fad, or the next big health-monitoring thing?
• Can a smart ring make me an Ultrahuman being?
• The 2025 CES: Safety, Longevity and Interoperability Remain a Mess
• Smart ring allows wearer to “air-write” messages with a fingertip

The post RingConn: Smart, svelte, and econ(omical) appeared first on EDN.

Infineon Technologies AG of Munich, Germany has launched the CoolSiC MOSFETs 1400V G2 in the TO-247PLUS-4 Reflow package, supporting higher DC-link voltages and enabling improved thermal performance, reduced system size and enhanced reliability...

Простір спільноти в осередку мудрості: круглий стіл у НТБ імені Г.І. Денисенка Інформація КП пн, 10/20/2025 - 13:07

🕔 Дайджест актуальних подій та конкурсів від Відділу академічної мобільності kpi пн, 10/20/2025 - 10:59

Japan-based power semiconductor firm ROHM has released a new white paper detailing power solutions for AI data centers based on the 800VDC architecture of NVIDIA of Santa Clara, CA, USA...

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Edge AI, mired by fragmentation and a lack of broad availability of toolchains, is inching toward open architectures and open-source hardware and software. This shift was apparent at Synaptics Tech Day on 15 October 2025, held at the company’s headquarters in San Jose, California.

In other words, some edge AI processors are moving away from proprietary, closed AI software and tooling toward open software and ecosystems to deliver AI applications at scale. Google’s collaboration with Synaptics embodies this open-source approach to edge processors, aiming to deliver AI intelligence at very low power levels.

Figure 1 Astra SL2610 processors provide multimodal AI compute for smart appliances, home and factory automation equipment, charging infrastructure, retail PoS terminals and scanners, and more. Source: Synaptics

Google, which built a mini-TPU ASIC for edge AI under the Coral brand back in 2017, subsequently built the Coral NPU as a four-way superscalar 32-bit RISC-V CPU. Google is hoping that edge AI silicon suppliers will start using this small, lightweight CPU as a consistent front-end to other execution units on an edge AI processor.

As part of this initiative, Google has open-sourced a compiler and software stack to port models from any ML framework onto the CPU. That allows silicon vendors like Synaptics to create an open-standards-based pipeline from the ML frameworks all the way down to the NPU front-end.

But the question is why RISC-V, especially when Synaptics’ SL2610 processor is built around Arm Cortex-A55, Cortex-M52 with Helium, and Mali GPU technologies. Synaptics managers say that the move to RISC-V is intended to reduce fragmentation in software stacks serving edge AI designs.

When asked about this, John Weil, head of processing at Synaptics, told EDN that many semiconductor suppliers are employing RISC-V cores, generally as assisting cores, and most people don’t know that they are even there. “In this case, it’s a much more performance-oriented RISC-V core to perform neural processing.”

Synaptics tie-up with Google

In January 2025, Synaptics announced it would integrate Google’s ML core with its Astra open-source software to accelerate the development of context-aware devices. The collaboration aimed to combine AI-native hardware with open-source software to accelerate the development of context-aware devices.

Next, Synaptics introduced the Torq edge AI platform, which combines NPU architectures with open-source compilers to set a new standard in edge AI application development. Torq, leveraging an open-source IREE/MLIR compiler and runtime, has been critical in facilitating the deployment of Google’s RISC-V-based Coral open NPU in the edge AI processor Astra SL2610.

Figure 2 Torq, a combination of AI hardware and software, includes Google’s Coral NPU and Synaptics’ home-grown AI accelerator. Source: Synaptics

At Synaptics Tech Day, the company showcased the Astra SL2610 processor powering several edge AI applications. That included e-bikes, EV charging infrastructure, industrial-grade AI glasses, command-based speech recognition, and smart home automation.

Vikram Gupta, chief products officer at Synaptics, told EDN that when the company wanted to go broad, it decided that this processor would be AI native. “When we met with Google, it instantly resonated with us because they were working on Coral NPU, an open ML accelerator,” he said. “We also wanted to go open source as part of our AI-native processor story.”

Regarding Google’s interest in this collaboration, Gupta said that Google benefits because it has a silicon partner. “Google gets mindshare in the AI race while it’s prominent in the cloud as well as the edge AI.” Moreover, Google could bring multimodal capabilities to this tie-up to enable more context-aware user experiences, said Nina Turner, research director for enabling technologies and semiconductors at IDC.

Another critical goal of this silicon partnership is to confront fragmentation in the edge AI world. “Our take is that the only way to keep up with AI innovation at the edge is to be open,” said Weil of Synaptics. “While some edge AI suppliers want everything in their ecosystem, we are focused on how we knock down walled gardens.”

Regarding collaboration with Google, Weil added, “As an edge AI guy, I need to be working with guys working in the cloud, focused on the next big AI idea.” He further summed up by saying that for Synaptics, the challenge was how to make hardware that keeps up with the speed of AI, open architecture, and open source. “So, we took Google technology and matched it with ours.”

Open and collaborative

At a time when innovations in AI software and algorithms are far outpacing silicon advancements, an AI-native approach to edge IoT processing could be critical in adopting contextual LLMs for audio, voice, text, and video applications at the edge.

The launch of the Astra SL2610 processor, an AI-enabled system-on-chip (SoC) encompassing application processor-level as well as microcontroller-level parts, marks an important step in the availability of scalable, open systems for deploying real-world edge AI. These AI-native chips are expected to help create an ecosystem that will simplify development and unlock powerful new applications in the edge AI realm.

“We believe that the only way to keep up with AI innovation at the edge is to be open and collaborative,” Weil concluded.

Related Content

• It’s All About Edge AI, But Where’s the Revenue?
• How Edge AI Transforms IIoT and Enables Industry 5.0
• Hybrid system resolves edge AI’s on-chip memory conundrum
• Infineon Expands Edge AI Capabilities with Launch of DEEPCRAFT AI Suite
• The Future of the Edge: The Rising Tide for Better AI Performance, Scalability, and Security

The post An edge AI processor’s pivot to the open-source world appeared first on EDN.

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Learn how the Foster-Seeley discriminator, a classic analog circuit for FM demodulation, achieves its superior linearity.

This is probably pretty common since there are 8 (EIGHT!!!) of these inside a cheap Samsung monitor, still, found it really impressive that this is (1) possible & (2) economically viable. submitted by /u/Bug_Next [link] [comments]

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