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Broadcom Inc. claims the industry’s first Wi-Fi 8 silicon solutions for the broadband wireless edge, including residential gateways, enterprise access points, and smart mobile clients. The company also announced the availability of its Wi-Fi 8 IP for license in IoT, automotive, and mobile device applications.

Designed for AI-era edge networks, the new Wi-Fi 8 chips include the BCM6718 for residential and operator access applications, the BCM43840 and BCM43820 for enterprise access applications, and the BCM43109 for edge wireless clients such as smartphones, laptops, tablets and automotive. These new chips also include a hardware-accelerated telemetry engine, targeting AI-driven network optimization. This engine collects real-time data on network performance, device behavior, and environmental conditions.

(Source: Broadcom Inc.)

The engine is a critical input for AI models and can be used by customers to train and run inference on the edge or in the cloud for use cases such as measuring and optimizing quality of experience (QoE), strengthening Wi-Fi network security and anomaly detection, and lowering the total cost of ownership through predictive maintenance and automated optimization, Broadcom said.

Wi-Fi 8 silicon chips

The BCM6718 residential Wi-Fi access point chip features advanced eco modes for up to 30% greater energy efficiency and third-generation digital pre-distortion, which reduces peak power by 25%. Other features include a four-stream Wi-Fi 8 radio, receiver sensitivity enhancements enabling faster uploads, BroadStream wireless telemetry engine for AI training/inference, and BroadStream intelligent packet scheduler to maximize QoE. It also provides full compliance to IEEE 802.11bn and WFA Wi-Fi 8 specifications.

The BCM43840 (four-stream Wi-Fi 8 radio) and BCM43820 (two-stream scanning and analytics Wi-Fi 8 radio) enterprise Wi-Fi access point chips also feature advanced eco modes and third-generation digital pre-distortion, a BroadStream wireless telemetry engine for AI training/inference, and full compliance to IEEE 802.11bn and WFA Wi-Fi 8 specifications. They also provide an advanced location tracking capability.

The highly-integrated BCM43109 dual-core Wi-Fi 8, high-bandwidth Bluetooth, and 802.15.4 combo chip is optimized for mobile handset applications. The combo chip offers non-primary channel access for latency reduction and improved low-density parity check coding to extend gigabit coverage. It also provides full compliance to IEEE 802.11bn and WFA Wi-Fi 8 specifications, along with 802.15.4 support including Thread V1.4 and Zigbee Pro, and Bluetooth 6.0 high data throughput and higher-bands support. Other key features include a two-stream Wi-Fi 8 radio with 320-MHz channel support, enhanced long range Wi-Fi, and sensing and secure ranging.

The Wi-Fi 8 silicon is currently sampling to select partners. The Wi-Fi IP is currently available for licensing, manufacture, and use in edge client devices.

The post Broadcom delivers Wi-Fi 8 chips for AI appeared first on EDN.

Microchip Technology Inc. expands its Switchtec PCIe family with its next-generation Switchtec Gen 6 PCIe fanout switches, supporting up to 160 lanes for high-density AI systems. Claiming the industry’s first PCIe Gen 6 switches manufactured using a 3-nm process, the Switchtec Gen 6 family features lower power consumption and advanced security features, including a hardware root of trust and secure boot with post-quantum-safe cryptography compliant with the Commercial National Security Algorithm Suite (CNSA) 2.0.

The PCIe 6.0 standard doubles the bandwidth of PCIe 5.0 to 64 GT/s per lane, making it suited for AI workloads and high-performance computing applications that need faster data transmission and lower latency. It also adds flow control unit (FLIT) mode, a lightweight forward-error-correction (FEC) system, and dynamic resource allocation, enabling more efficient and reliable data transfer, particularly for small packets in AI workloads.

As a high-performance interconnect, the Switchtec Gen 6 PCIe switches, Microchip’s third-generation PCIe switch, enable high-speed connectivity between CPUs, GPUs, SoCs, AI accelerators, and storage devices, reducing signal loss and maintaining the low latency required by AI fabrics, Microchip said.

Though there are no production CPUs with PCIe Gen 6 support on the market, Microchip wanted to make sure that they had all of the infrastructure components in advance of PCIe Gen 6 servers.

“This breakthrough is monumental for Microchip, establishing us once again as a leader in data center connectivity and broad infrastructure solutions,” said Brian McCarson, corporate vice president of Microchip’s data center solutions business unit.

Offering full PCIe Gen 6 compliance, which includes FLIT, FET, 64-Gbits/s PAM4 signaling, deferrable memory, and 14-bit tag, the Switchtec Gen 6 PCIe switches feature 160 lanes, 20 ports, and 10 stacks with each port featuring hot- and surprise-plug controllers. Also available are 144-lane variants. These switches support non-transparent bridging to connect and isolate multiple host domains and multicast for one-to-many data distribution within a single domain. They are suited for high-performance compute, cloud computing, and hyperscale data centers.

(Source: Microchip Technology Inc.)

Multicast support is a key feature of the next-generation switch. Not all switch providers have multicast capability, McCarson said.

“Without multicast, if a CPU needs to communicate to two drives because you want to have backup storage, it has to cast to one drive and then cast to the second drive,” McCarson said. “With multicast, you can send a signal once and have it cast to multiple drives.

“Or if the GPU and CPU have to communicate but you need to have all of your GPUs networked together, the CPU can communicate to an entire bank of GPUs or vice versa if you’re operating through a switch with multicast capability,” he added. “Think about the power savings from not having a GPU or CPU do the same thing multiple times day in, day out.”

McCarson said customers are interested in PCIe Gen 6 because they can double the data rate, but when they look at the benefits of multicast, it could be even bigger than doubling the data rates in terms of efficient utilization of their CPU and GPU assets.

Other features include advanced error containment and comprehensive diagnostics and debug capabilities, several I/O interfaces, and an integrated MIPS processor with bifurcation options at x8 and x16. Input and output reference clocks are based on PCIe stacks with four input clocks per stack.

Higher performance

The Switchtec Gen 6 product delivers on performance in signal integrity, advanced security, and power consumption.

PCIe 6.0 uses PAM4 signaling, which enables the doubling of the data rate, but it can also reduce the signal-to-noise ratio, causing signal integrity issues. “Signal integrity is one of the key factors when you’re running this higher data rate,” said Tam Do, technical engineer, product marketing for Microchip’s Data Center Solutions business unit

Signal loss, or insertion loss, set by the PCIe 6 spec is 32 dB. The new switch meets the spec thanks in part to its SerDes design and Microchip’s recommended layout of the pinout and package, according to Do.

In addition, Microchip added post-quantum cryptography to the new chip, which is not part of the PCIe standard, to meet customer requirements for a higher level of security, Do said.

The PCIe switch also offers lower power consumption, thanks to the 3-nm process, than competing PCIe Gen 6 devices built on older technology nodes.

Development tools include Microchip’s ChipLink diagnostic tools, which provide debug, diagnostics, configuration, and analysis through an intuitive graphical user interface. ChipLink connects via in-band PCIe or sideband signals such as UART, TWI, and EJTAG. Also available is the PM61160-KIT Switchtec Gen 6 PCIe switch evaluation kit with multiple interfaces.

Switchtec Gen 6 PCIe switches (x8 and x16 bifurcation) and an evaluation kit are available for sampling to qualified customers. A low-lane-count version with 64 and 48 lanes with x2, x4, x8, x16 bifurcation for storage and general enterprise use cases will also be available in the second quarter of 2026.

The post Microchip launches PCIe Gen 6 switches appeared first on EDN.

Віктор Лазаренко. Пів століття разом із КПІ Інформація КП вт, 10/14/2025 - 21:38

IV семінар серії «Аспекти національної безпеки та оборони» kpi вт, 10/14/2025 - 21:27

Пам'яті Шумара Андрія Георгійовича kpi вт, 10/14/2025 - 21:24

Power Integrations Inc of San Jose, CA, USA (which provides high-voltage integrated circuits for energy-efficient power conversion) has outlined the benefits of its PowiGaN gallium nitride technology for next-generation AI data centers. The capabilities of 1250V and 1700V PowiGaN technology for 800VDC power architectures are explained in a new white paper from Power Integrations, published at the 2025 OCP Global Summit in San Jose, where NVIDIA provided an update on the 800VDC architecture. Power Integrations is collaborating with NVIDIA to accelerate the transition to 800VDC power and megawatt-scale racks...

Renesas Electronics Corp of Tokyo, Japan says that it is supporting efficient power conversion and distribution for the 800V direct current power architecture announced by NVIDIA of Santa Clara, CA, USA, helping to fuel the next wave of smarter, faster AI infrastructure...

Qualcomm has spent years trying to get traction in edge computing. Now it has a direct channel to developers building those systems at the prototype stage.

Analog topologies abound for converting current to voltage, voltage to current, voltage to frequency, and frequency to voltage, among other conversions.

Figure 1 joins the flock while singing a somewhat different tune. This current, voltage, and power (IVW) DC power converter multiplies current by voltage to sense wattage. Here’s how it gets off the ground.

Figure 1 The “I*V = W” converter comprises voltage-to-frequency conversion (U1ab & A1a) with frequency (F) of 2000 * Vload, followed by frequency-to-voltage conversion (U1c & A1b) with Vw = Iload * F / 20000 = (Iload * Vload) / 10 = Watts / 10 where Vload < 33 V and Iload < 1.5 A.

Wow the engineering world with your unique design: Design Ideas Submission Guide

The basic topology of the IVW converter comprises a voltage-to-frequency converter  (VFC) cascaded with a frequency-to-voltage converter (FVC). U1ab and A1a, combined with the surrounding discretes (Q1, Q2, Q3, etc.), make a VFC similar to the one described in this previous Design Idea, “Voltage inverter design idea transmogrifies into a 1MHz VFC”

The U1ab, A1a, C2, etc., VFC forms an inverting charge pump feedback loop that actively balances the 1 µA/V current through R2. Each cycle of the VFC deposits a charge of 5v * C2, or 500 picocoulombs (pC), onto integrator capacitor C3 to produce an F of 2 kHz * Vload (= 1 µA / 500 pC) for the control signal input of the FVC switch U1c. 

The other input to the U1c FVC is the -100 mV/A current-sense signal from R1. This combo forces U1c to pump F * -0.1 V/amp * 500 pF = -2 kHz * Vload * 50 pC * Iload into the input of the A1b inverting integrator.

 The melodious result is:

Vw = R1 * Iload * 2000 * Vload * R6 * C6

or, 

Vw = Iload * Vload * 0.1 * 2000 * 1 MΩ * 500 pF = 100 mV/W.

The R6C5 = 100-ms integrator time constant provides >60-dB of ripple attenuation for Vload > 1-V and a low noise 0- to 5-V output suitable for consumption by a typical 8- to 10-bit resolution ADC input. Diode D1 provides fire insurance for U1 in case Vload gets shorted to ground.

Stephen Woodward’s relationship with EDN’s DI column goes back quite a long way. Over 100 submissions have been accepted since his first contribution back in 1974.

Related Content

• Voltage inverter design idea transmogrifies into a 1MHz VFC
• A simulated 100-MHz VFC
• A simple, accurate, and efficient charge pump voltage inverter for $1 (in singles)
• 100-MHz VFC with TBH current pump

The post Amps x Volts = Watts appeared first on EDN.

Join us for the third All About Circuits Summit Day of 2025 or catch up on everything you missed with this helpful guide to the keynotes, live sessions, microsites, and prizes.

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Texas Instruments (TI) debuted new design resources and power-management chips to help companies meet growing artificial intelligence (AI) computing demands and scale power-management architectures from 12V to 48V to 800 VDC. The new solutions will be on display at Open Compute Summit (OCP) Oct. 13-16 in San Jose, and include:

• “Power delivery trade-offs when preparing for the next wave of AI computing growth”: TI is collaborating with NVIDIA to develop power-management devices to support 800 VDC power architecture, as IT rack power is expected to eclipse 1MW in the next two to three years. This white paper reexamines the power delivery architecture within the IT rack, and addresses design challenges and opportunities for high efficiency and high power-density energy conversion at a system level.
• Reference design: 30kW AI server power-supply unit: To support stringent AI workloads, TI’s dual-stage power-supply reference design features a three-phase, three-level flying capacitor power factor correction converter paired with dual delta-delta three-phase inductor-inductor-capacitor converters. The power supply is configurable as a single 800V output or separate output supplies.
• Dual-phase smart power stage:The highest peak power density power stage on the market, TI’s CSD965203B offers 100A of peak current per phase and combines two power phases in a single 5mm-by-5mm quad flat no-lead package. The device enables designers to increase phase count and power delivery across a small printed circuit board area, improving efficiency and performance.
• Dual-phase smart power module for lateral power delivery: The CSDM65295 module delivers up to 180A of peak output current in a compact 9mm-by-10mm-by-5mm package, helping engineers increase data center power density without compromising thermal management. The module integrates two power stages and two inductors with trans-inductor voltage regulation (TLVR) options, while maintaining high efficiency and reliable operation.
• Gallium-nitride intermediate bus converter: Capable of delivering up to 1.6kW of output power in a quarter-brick (58.4-mm-by-36.8mm) form factor, TI’s LMM104RM0 converter module offers over 97.5% input-to-output power-conversion efficiency and high light-load efficiency to enable active current sharing between multiple modules.

AI data centers require architectures designed with multiple foundational semiconductors for efficient power management, sensing and data conversion. With new design resources and a broad power-management portfolio, TI is working alongside data center designers to implement a comprehensive approach that drives efficient, safe power management – from power generation at the grid to the fundamental logic gates of graphics processing units.

“With the growth of AI, data centers are evolving from simple server rooms to highly sophisticated power infrastructure hubs,” said Chris Suchoski, sector general manager, Data Centers at TI. “Scalable power infrastructure and increased power efficiency are essential to meet these demands and drive future innovation. With devices from TI, designers can build innovative, next-generation solutions that are enabling the transition to 800 VDC.”

The post TI’s new power-management solutions enable scalable AI infrastructures appeared first on ELE Times.

КПІ ім. Ігоря Сікорського на відкритті Huawei Student Tech Challenge 2025 kpi вт, 10/14/2025 - 12:13

The event brought together institutional and industrial partners, ESA Member State representatives, and leading figures in satellite navigation. The celebration revisited pivotal milestones in Europe’s satellite navigation history and looked ahead to future innovations. A highlight of the evening was the award ceremony led by European Space Agency (ESA) Director of Navigation Javier Benedicto, who, alongside past directors, presented accolades to organizations and partners instrumental in this success story.

Rohde & Schwarz’s recognition underscores their role in advancing European satellite navigation technology. Their contributions have been vital in the development and operational success of Galileo and EGNOS, systems that have revolutionized positioning, navigation, and timing services across Europe and beyond.

The event not only celebrated past achievements but also set the stage for the future of European satellite navigation, with discussions around upcoming initiatives and advancements. For Rohde & Schwarz and other honourees, the evening served as both a celebration of past achievements and a call to continue building a connected, resilient, and sustainable future in space.

Rob Short, Director Business Development at Rohde & Schwarz comments: “Thirty years of satellite navigation is a testament to shared vision, determination to push technology boundaries, and intense, long-term collaboration. We are honoured to have contributed to this remarkable achievement. Congratulations to everyone who made this milestone possible.”

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STMicroelectronics, a global semiconductor leader serving customers across the spectrum of electronics applications, announced that Rias Al-Kadi, General Manager of the Company’s Range and Connectivity Division, joined the board of directors of the FiRa Consortium, the industry body dedicated to advancing secured fine ranging and positioning ultra-wideband (UWB) technology.

ST is actively driving the development of the IEEE 802.15.4ab amendment, building upon previous UWB enhancements to further improve system performance and expand UWB’s application scope. The ongoing evolution of UWB standards promises significant improvements, including centimetre-level accuracy, enhanced security, and reduced power consumption. These improvements are critical for enabling a wide range of applications, from automotive access and digital keys to smart home automation and IoT innovations. Integrating IEEE 802.15.4ab into the CCC Digital Key ecosystem would represent a major step forward in addressing implementation challenges and accelerate broader adoption of UWB technology in both consumer and automotive markets.

“STMicroelectronics has long been a valued member of the FiRa Consortium, and we are thrilled to welcome them at the Sponsor level. This upgrade is a reflection of ST’s deepening commitment to the future of Ultra-Wideband technology and to FiRa’s mission. We are especially pleased to have Rias Al-Kadi, General Manager of ST’s Ranging and Connectivity Division, join our Board of Directors. His experience and leadership will be instrumental as we continue to expand UWB’s global impact and shape the future of secure, interoperable solutions,” states SK Yong, FiRa Consortium Board Chairman.

“Joining the FiRa board underlines our commitment to advancing the CCC Digital Key and other UWB-based applications,” said Rias Al-Kadi, General Manager, Ranging and Connectivity Division, STMicroelectronics. “By deeply engaging in standardization and certification across all major UWB groups, we are helping to shape the future of UWB technology to deliver maximum value for consumers and industries alike.”

Rias Al-Kadi’s appointment further strengthens ST’s active participation in key UWB standards bodies and consortia, including the IEEE, Connected Car Consortium (CCC), Connectivity Standards Alliance (CSA), and UWB Alliance. Through strategic participation in these groups, ST supports the continuous evolution of UWB technology aimed at enhancing user experiences and lowering system costs, particularly in consumer and automotive access applications. This aligns with ST’s vision to foster a robust UWB ecosystem that enables seamless, secure, and cost-effective solutions for the growing UWB market.

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🎬 Показ та обговорення фільму «Після ери мовчання» kpi вт, 10/14/2025 - 10:26

The STARLight project is bringing together a consortium of leading industrial and academic partners to position Europe as a technology leader in 300mm silicon photonics (SiPho) technology by establishing a high-volume manufacturing line, developing leading-edge optical modules, and fostering a complete value chain.  From now until 2028, STARLight aims to develop application-driven solutions focusing on key industry sectors such as datacentres, AI clusters, telecommunications, and automotive markets.

Led by STMicroelectronics, a global semiconductor leader serving customers across the spectrum of electronics applications, the STARLight consortium has been selected by the European Commission under the EU CHIPS Joint Undertaking initiative.

“Silicon Photonics technology is critical to put Europe at the crossroads to the AI factory of the future and the STARLight project represents a significant step for the entire value chain in Europe, driving innovation and collaboration among leading technology companies. By focusing on application-based results, the project aims to deliver cutting-edge solutions for datacentres, AI clusters, telecommunications, and automotive markets. With well-recognized pan-European partners, the STARLight consortium is set to lead the next generation of silicon photonics technologies and applications,” said Remi El-Ouazzane, President, Microcontrollers, Digital ICs and RF products Group at STMicroelectronics.

Silicon photonics is a preferred technology to support datacentres and AI clusters optical interconnects for scale-out and scale-up growth, as well as for other technologies such as LIDAR, space applications, and AI photonic processors that require better energy-efficiency and power efficient data transfer. It combines the high-yield manufacturing capabilities of CMOS silicon, commonly used in electronic circuits, with the benefits of photonics, which transmits data using light.

Addressing key challenges
The development of advanced Photonic Integrated Circuits (PICs) will tackle several challenges:

• High-speed modulation: creating highly efficient modulators capable of operating at speeds exceeding 200 Gbps per lane is a key focus
• Laser integration: developing efficient and reliable on-chip lasers is critical for integrated systems
• New materials: various advanced materials will be explored with actors like SOITEC, CEA-LETI, imec, UNIVERSITE PARIS-SACLAY, III-V LAB, LUMIPHASE, and integrated on a single innovative silicon photonics platform, such as Silicon-on-Insulator (SOI), Lithium Niobate (LNOI), and Barium Titanate (BTO)
• Packaging and integration: optimizing the packaging and integration of PICs with electronic circuits is essential to optimize signal integrity and minimize power consumption.

Applications-based innovations
Datacentres / Datacom
The STARLight project has an initial focus to build datacom demonstrators for datacentres, based on PIC100 technology, capable of handling up to 200Gb/s with key actors including ST, SICOYA and THALES. It will also develop prototypes for free-space optical transmission systems, designed for both space and terrestrial communication.

Additionally, the project will leverage the multidisciplinary experience of major contributors to shape the research effort towards a 400Gbps per lane optical demonstrator using new materials, targeting the next generation of pluggable optics.

Artificial Intelligence (AI)
The STARLight project aims to develop a cutting-edge photonic processor optimized for tensor operations, such as matrix vector multiplication and multiply-accumulate, with superior characteristics in terms of size, data processing speed, and energy consumption compared to existing technologies. Since neural networks – the core algorithms behind AI – rely heavily on tensor operations, enhancing their efficiency is critical for AI processing performance.

Telecommunication
The STARLight project plans to develop and showcase innovative silicon photonic devices specifically designed for the telecommunications industry. Ericsson will focus on two concepts to improve mobile network efficiency. The first involves the development of an integrated switch to enable optical offload within Radio Access Networks, allowing for more efficient handling of data traffic. The second concept explores Radio over Fiber technology to relocate power-intensive processing ASICs away from antenna units, thus providing enhanced capacity and savings in embodied CO2. Additionally, MBRYONICS will develop a free space to fiber interface at the reception of Free Space Optical (FSO) communication, which is a key element in the design of an optical communication system.

Automotive/ Sensing
The STARLight project will also demonstrate how it performs in sensing applications, and the close relationships of STEERLIGHT, a LiDAR sensors maker, with leading car manufacturers will help make this an industrial reality.

“STEERLIGHT is developing a new generation of 3D vision sensors—non-mechanical FMCW LiDARs—powered by groundbreaking silicon photonics technology that enables the entire system to be integrated onto a microchip. In the coming years, the light-vehicle components market will undergo a significant transformation driven by the rise of advanced driver-assistance systems (ADAS), which require compact, cost-effective, and high-performance LiDAR solutions. Securing sovereign sources of microelectronic components is a strategic priority for STEERLIGHT to enable large-scale production of this next generation of LiDAR systems. This is essential for European players to maintain a leading position in the global value chain and to ensure technological sovereignty in a highly competitive and rapidly evolving sector. The STARLight project will support this goal with ST’s proprietary advanced silicon photonics platform, bringing the capability to industrial maturity.” – François Simoens, CEO and co-founder of SteerLight.

Within the project, THALES will develop sensors that accurately generate, distribute, detect, and process signals with intricate waveforms to demonstrate key functionalities. More broadly, the outcomes of this project are also intended to benefit the wider ecosystem of indoor and outdoor autonomous robot manufacturers.

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KYOCERA AVX released the new KGP Series commercial-grade stacked capacitors for high-frequency applications in the industrial and downhole oil and gas industries.

The new commercial-grade KGP Series stacked multilayer ceramic capacitors (MLCCs) deliver higher capacitance values in the same mounting area as traditional capacitors to support the enduring miniaturization megatrend and are manufactured without lead or cadmium to support the thriving sustainability megatrend and ease standards compliance. They also exhibit low equivalent series resistance (ESR) and inductance (ESL) to minimize noise and optimize performance and feature metal lead frames that reliably suppress both thermal and mechanical stress to ensure stability and durability.

KGP Series stacked MLCCs are currently available in five EIA case sizes (1210, 1812, 1825, 2220, and 2225) with two stack sizes, maximum thicknesses spanning 3.40mm to 6.95mm, and “J” or “L” leads. They are also available in three dielectrics (C0G, X7R, and X7T). The series is rated for operating voltages spanning 50V to 1,500V, capacitance values ranging from 10nF to 47µF ±10% or 20% capacitance tolerance, and operating temperatures extending from -55°C to +125°C.

Ideal applications for the series extend throughout the industrial, alternative energy, and downhole oil and gas industries and include power supplies, DC/DC converters, control circuits, high voltage coupling, and DC blocking.

“The new KGP Series stacked MLCCs further expand our proven portfolio of capacitor solutions optimized for growing markets with challenging performance requirements, including the power supply and downhole drilling markets,” said Zack Kozawa, Director of MLCC Product Marketing at KYOCERA AVX. “They also support the miniaturization and sustainability megatrends affecting these and other market segments.”

KGP Series stacked MLCCs with C0G and X7R dielectrics are available in all five EIA case sizes with the full range of rated voltage values and capacitance values up to 220nF and 47µF, respectively. Those with X7T dielectrics are available in three EIA case sizes (1210, 1812, and 2220) with three rated voltages (250V, 450V, and 630V) and capacitance values up to 4.7μF.

All parts are thoroughly tested for visual characteristics, capacitance values, dissipation factor, temperature coefficient, insulation resistance, dielectric strength, temperature cycling, steady state and load humidity, high temperature load, termination strength, bending, vibration resistance, and soldering heat resistance to ensure peak performance in a wide range of challenging high-frequency applications. They are also RoHS compliant and packaged on tape and reel in quantities of 500–1,500 for automated placement.

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Switchtec Gen 6 PCIe Fanout Switches deliver extra bandwidth, low latency and advanced security for high-performance compute, cloud computing and hyperscale data centers

As artificial intelligence (AI) workloads and high-performance computing (HPC) applications continue to drive unprecedented demand for faster data movement and lower latency, Microchip Technology has introduced its next generation of Switchtec Gen 6 PCle Switches. The industry’s first PCIe Gen 6 switches manufactured using a 3 nm process, the Switchtec Gen 6 family is designed to deliver lower power consumption and support up to 160 lanes for high-density AI system connectivity. Advanced security features include a hardware root of trust and secure boot, utilizing post-quantum safe cryptography compliant with the Commercial National Security Algorithm Suite (CNSA) 2.0.

Previous PCIe generations created bandwidth bottlenecks as data transferred between CPUs, GPUs, memory and storage, leading to underutilization and wasted compute cycles. PCIe 6.0 doubles the bandwidth of PCIe 5.0 to 64 GT/s (giga transfers per second) per lane, providing the necessary data pipeline to keep the most powerful AI accelerators consistently supplied. Switchtec Gen 6 PCIe switches enable high-speed connectivity between CPUs, GPUs, SoCs, AI accelerators and storage devices, and are designed to help data center architects scale to the potential of next generation AI and cloud infrastructure.

“Rapid innovation in the AI era is prompting data center architectures to move away from traditional designs and shift to a model where components are organized as a pool of shared resources,” said Brian McCarson, corporate vice president of Microchip’s data center solutions business unit. “By expanding our proven Switchtec product line to PCIe 6.0, we’re enabling this transformation with technology that facilitates direct communication between critical compute resources and delivers the most powerful and energy efficient switch we’ve ever produced.”

By acting as a high-performance interconnect, the switches allow for simpler, more direct interfaces between GPUs in a server rack, which is crucial for reducing signal loss and maintaining the low latency required by AI fabrics. The PCIe 6.0 standard also introduces Flow Control Unit (FLIT) mode, a lightweight Forward Error Correction (FEC) system and dynamic resource allocation. These changes make data transfer more efficient and reliable, especially for small packets which are common in AI workloads. These updates lead to higher overall throughput and lower effective latency.

Switchtec Gen 6 PCIe switches feature 20 ports and 10 stacks with each port featuring hot- and surprise-plug controllers. Switchtec also supports NTB (Non-Transparent Bridging) to connect and isolate multiple host domains and multicast for one-to-many data distribution within a single domain. The switches are designed with advanced error containment and comprehensive diagnostics and debug capabilities, a wide breadth of I/O interfaces and an integrated MIPS processor with bifurcation options at x8 and x16. Input and output reference clocks are based on PCIe stacks with four input clocks per stack.

The post Microchip Unveils First 3 nm PCIe Gen 6 Switch to Power Modern AI Infrastructure appeared first on ELE Times.

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