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The circuit in Figure 1 combines a VBE-referenced current source with a current mirror to implement a simple two-terminal, fully floating LED current sink or source. This approach is well-suited for applications in which tight current accuracy is not required, such as driving LED strings where a 5–10% current tolerance is acceptable.

Figure 1 A simple, fully floating LED current driver based on a VBE-referenced current source and a BJT current mirror. The circuit operates as either a current sink or source and supports output currents up to 100 mA. Note: R2=R3. All resistors are ¼ W and 5%. 

Wow the engineering world with your unique design: Design Ideas Submission Guide

The LED driver can drive an arbitrary number of series-connected LEDs, provided the available supply voltage is at least 2.3 V. The topology supports both high-side and low-side operation, as shown in Figure 2. Output current ranges from a few milliamps up to 100 mA, with no requirement for heat sinks.

Figure 2 High-side and low-side operating configurations enabled by the fully floating nature of the LED driver.

The current source formed by BJTs Q1 and Q2 is set by resistor R1. A current mirror implemented with BJTs Q3 and Q4, using equal emitter resistors (R2 = R3), forces nearly equal currents in branches I1 and I2, as long as the voltage drop across the emitter resistors is at least 0.5 V. This requirement helps compensate for VBE mismatch between the transistors. The total LED current is therefore doubled, while power dissipation is evenly shared among the devices.

Experimental data (Table 1) confirm the expected behavior: output current scales with R1, and the minimum supply voltage increases from 2.3 V at 9.3 mA to 2.8 V at 97 mA, consistent with the headroom required by the VBE-referenced source and mirror.

R1	R2=R3	Iout	Vsupplymin
150Ω	100 Ω	9.3mA	2.3V
82 Ω	56 Ω	18.2mA	2.4V
33 Ω	22 Ω	44mA	2.5V
15 Ω	10 Ω	97mA	2.8V

Table 1 Experimental data showing R1, R2/R3, and corresponding Iout and Vsupplymin.

With a minimum operating voltage of approximately 2.8V, the circuit dissipates about 280 mW at a maximum output current of 100 mA. Higher supply voltages reduce efficiency due to increased power dissipation in the driver.

Because the LED current is VBE-dependent, it exhibits temperature sensitivity, with a temperature coefficient of approximately -0.3 %/°C. Using a resistor with a negative temperature coefficient for R1 can partially compensate for this effect.

—Luca Bruno has a Master’s Degree in Electronic Engineering from the Politecnico of Milan. He has written 16 EDN Design Ideas.

Related Content

• LED strings driven by current source/mirror
• Current mirror drives multiple LEDs from a low supply voltage
• A current mirror reduces Early effect
• A two-way mirror — current mirror that is

The post A fully floating BJT-based LED current driver appeared first on EDN.

The AI industry has converged on a deceptively simple metric: cost per token. It’s easy to understand, easy to compare, and easy to market. Every new system promises to drive it lower. Charts show steady declines, sometimes dramatic ones, reinforcing the impression that AI inference is rapidly becoming cheaper and more efficient.

But simplicity, in this case, is misleading.

A token is not a fundamental unit of cost in isolation. It is the visible output of a deeply complex system that spans model architecture, hardware design, system scaling, memory behavior, power consumption, and operational efficiency. Reducing that complexity to a single number creates a dangerous illusion: improvements in cost per token necessarily reflect improvements in the underlying system.

They often do not.

To understand what is really happening, we need to step back and look at the full system—specifically, the total cost of ownership (TCO) of an AI inference deployment.

From benchmark numbers to real systems

Most comparisons in the industry start from benchmark results. Inference benchmarks such as MLPerf provide a useful baseline because they fix key variables—model, latency constraints, and workload characteristics—allowing different systems to be evaluated under the same conditions.

Take a large-scale model such as Llama 3.1 405B. On a modern GPU system like Nvidia’s GB200 NVL72, MLPerf reports an aggregate throughput that translates to roughly 138 tokens per second per accelerator. An alternative inference-focused architecture might deliver a lower figure—say, 111 tokens per second per accelerator.

At first glance, the conclusion seems obvious: the GPU is faster.

But this is precisely where the problem begins. That number describes the performance of a single accelerator under specific benchmark conditions. It says very little about how the system behaves when deployed at scale.

And in real-world data centers, scale is everything.

The illusion of linear scaling

In theory, performance should scale linearly with the number of accelerators. Double the hardware, double the throughput. In practice, this never happens. Communication overhead, synchronization, memory contention, and architectural inefficiencies all conspire to reduce effective performance as systems grow.

This effect is captured by what is often called scaling efficiency. It’s one of the most important and most overlooked parameters in AI infrastructure.

A system that achieves 97% scaling efficiency will behave differently from one that achieves 85%, even if their per-chip performance appears comparable. Over dozens or hundreds of accelerators, that difference compounds rapidly.

This is where inference-specific architectures begin to separate themselves.

Unlike training, inference does not require backpropagation. The execution flow is more predictable, the data movement patterns are more structured, and the opportunity for optimization is significantly greater. Architectures that are purpose-built for inference can exploit this determinism to sustain high utilization across large systems.

One architecture is a case in point. By moving away from the traditional GPU execution model and adopting a deeply pipelined, dataflow-oriented design, it minimizes the coordination overhead that typically erodes scaling efficiency. The result is not just higher peak utilization, but more important, consistently high utilization at scale.

When the system flips the narrative

Once performance is evaluated at the level that actually matters—servers, racks, and data centers—the comparison often changes.

Throughput per server depends not only on per-accelerator performance, but also on how many accelerators are packed into a system and how efficiently they work together. Throughput per rack adds another layer, incorporating system density and infrastructure constraints. When power is introduced into the equation, the relevant metric becomes throughput per kilowatt.

It is at this level that architectural differences become impossible to ignore.

GPU-based systems are optimized for flexibility. They can handle a wide range of workloads, but that generality introduces inefficiencies when running highly structured inference tasks. Data must move between memory hierarchies, threads must be synchronized, and execution units often sit idle waiting for dependencies to resolve.

The architecture mentioned above takes a different approach. By eliminating the traditional memory hierarchy bottlenecks and replacing them with a large, flat register file combined with a dataflow execution model, it effectively removes the “memory wall” that limits sustained performance in GPU systems. Data is kept close to compute, and execution proceeds in a continuous pipeline rather than in discrete, synchronized steps.

The consequence is subtle but powerful: even if peak per-chip performance appears lower, the effective throughput at the system level can be significantly higher. More importantly, that performance is achieved with far greater energy efficiency.

Power: The constraint that doesn’t go away

Energy consumption is not just a cost factor; it’s the constraint that ultimately defines the scalability of AI infrastructure.

Electricity prices, power usage effectiveness (PUE), and utilization rates are not theoretical constructs. They are operational realities that directly impact the economics of every deployment. A system that consumes less energy per token has an intrinsic advantage that compounds over time.

This is where inference-native architectures again demonstrate their value.

Because the architecture’s design minimizes unnecessary data movement and maximizes pipeline utilization, it delivers more tokens per unit of energy. The metric that matters is not peak FLOPS, but tokens per kilowatt—and on that axis, architectural efficiency becomes the dominant factor.

In large-scale deployments, this translates directly into lower operating costs and improved total cost of ownership.

The hidden influence of workload assumptions

Benchmarking does not eliminate bias—it simply moves it.

Parameters such as context length, output token size, and concurrency have a profound impact on system behavior. A model running at 128K context imposes different demands than one operating at 8K. Latency, memory pressure, and throughput all shift accordingly.

Architectures that rely on heavy memory movement are particularly sensitive to these changes. As context length grows, the cost of moving data becomes increasingly dominant.

By contrast, architectures that localize data and streamline execution are more resilient to these shifts. This is another area where the architecture’s register-centric, dataflow design provides an advantage: it reduces dependence on external memory bandwidth and maintains more consistent performance across varying workloads.

From metrics to economics

When performance, power, and infrastructure are combined, the discussion moves from engineering to economics.

Total cost of ownership captures the full picture: capital expenditure, operating costs, energy consumption, and system utilization over time. It reflects not just how fast a system can run, but how efficiently it can deliver value in a real deployment.

This is where many cost-per-token claims fall apart.

A lower cost per token can be achieved in multiple ways—by improving efficiency, by adjusting assumptions, or by accepting lower margins. Without a system-level view, it’s impossible to distinguish between these scenarios.

What matters is not the headline number, but the underlying drivers.

The risk of optimizing the wrong thing

The industry’s focus on cost per token has created a subtle distortion. Instead of optimizing systems, we risk optimizing metrics. This is not unique to AI. Every technology cycle has its preferred metrics, and every metric can be gamed if taken out of context.

A truly efficient system is one that aligns performance, energy consumption, and scalability. It delivers consistent throughput, minimizes waste, and operates effectively under real-world constraints. This is precisely the direction that inference-specific architectures are taking.

The aforementioned architectural approach illustrates this shift. Rather than attempting to adapt a general-purpose architecture to an increasingly specialized workload, it starts from the workload itself and builds upward. The result is a system that is not only efficient in theory, but also in practice—at scale, under load, and within the constraints of real data centers.

Toward a more honest conversation

None of this diminishes the achievements of GPU-based systems. They have been instrumental in the rise of modern AI and remain incredibly powerful platforms. But the workloads are changing. Large language model inference is not the same as training, and it’s not the same as graphics. As the industry shifts toward deployment at scale, the limitations of general-purpose architectures become more apparent.

At the same time, new architectures, as described above, are emerging that are designed specifically for these workloads. They may not always win on peak performance metrics, but they are optimized for the realities of inference: predictable execution, high utilization, and energy efficiency.

If we want to compare these systems fairly, we need to move beyond simplified metrics and toward system-level evaluation.

The bottom line

Cost per token is not wrong—but it is incomplete.

The real question is not how cheaply a token can be produced in isolation, but how efficiently a system can deliver tokens over time, at scale, within the constraints of power, infrastructure, and workload demands.

When viewed through that lens, the path forward becomes clearer.

The next generation of AI infrastructure will not be defined by the highest peak performance or the most aggressive benchmark result. It will be defined by architectures that align performance with efficiency, and efficiency with economics.

And in that context, the industry may find that the most important innovation is not faster hardware—but better architecture.

Lauro Rizzatti is a business development executive at VSORA, a pioneering technology company offering silicon semiconductor solutions that redefine performance. He is a noted chip design verification consultant and industry expert on hardware emulation.

Related Content

• Chiplets Are The New Baseline for AI Inference Chips
• Custom AI Inference Has Platform Vendor Living on the Edge
• The next AI frontier: AI inference for less than $0.002 per query
• Revolutionizing AI Inference: Unveiling the Future of Neural Processing
• Purpose-built AI inference architecture: Reengineering compute design

The post The truth about AI inference costs: Why cost-per-token isn’t what it seems appeared first on EDN.

Applied Optoelectronics Inc (AOI) of Sugar Land, TX, USA (a designer and manufacturer of optical and hybrid fibre-coaxial networking products for AI data centers, cable TV and broadband fiber access networks) has received a new volume order from one of its major hyperscale customers for 800G single-mode data-center transceivers to help expand its network capacity for AI-driven workloads...

ROHM has added the new CMOS Operational Amplifier (op amp) series “TLRx728” and “BD728x” to its lineup. These are suitable for a wide range of applications, including automotive, industrial, and consumer systems. A broad lineup also makes product selection easier.

In recent years, demand for high-accuracy op amps has been rapidly increasing as automotive and industrial systems become more sophisticated, demanding faster speed, better precision, and higher efficiency. In applications requiring amplification of sensor outputs, minimising signal error and delay is essential. To meet these requirements, a well-balanced set of key characteristics is needed, including Input Offset Voltage, Noise, and Slew Rate.

These new products are high-performance op amps that offer a low input offset voltage, low noise, and high slew rate. TLRx728 features an input offset voltage of 150 μV (typ.), while the BD728x offers 1.6 mV (typ.).  Both series have a noise voltage density of 12 nV/√Hz at 1kHz and a slew rate of 10 V/μs. They are therefore suitable for a wide range of precision applications, including sensor signal processing, current detection circuits, motor driver control, and power supply monitoring systems. Both series are designed to balance versatility and high performance rather than being limited to specific applications.

Application Examples

Automotive equipment, industrial equipment, and consumer electronics.

Example use case: Sensor signal processing, current detection circuits, motor driver control, and power supply monitoring systems.

The post ROHM has added New Lineup of 17 High-Performance Op Amps Enhancing Design Flexibility appeared first on ELE Times.

Поїздка Шевченковими місцями із Профкомом kpi вт, 03/31/2026 - 12:56

КПІшники — серед лідерів з настільного тенісу на XXI Універсіаді kpi вт, 03/31/2026 - 12:51

In a major move to solidify India’s standing as a global high-tech hardware hub, the Union Government has announced a strategic investment of ₹257.77 crore (approximately $31 million) into 128 technology startups.

The announcement, shared by Minister of State for Electronics and IT, Jitin Prasada, in a written reply to the Rajya Sabha on Friday, March 27, 2026, highlights a shift toward “risk capital” for sectors critical to national security and economic self-reliance.

The “Fund of Funds” Mechanism

The investment was executed through the Electronics Development Fund (EDF), which operates under a “Fund of Funds” model. Instead of direct equity, the EDF acts as an anchor investor in eight professionally managed “Daughter Funds” (early-stage venture and angel funds).

These Daughter Funds have leveraged the government’s initial contribution to mobilise a total of ₹1,335.77 crore in follow-on investments for startups specialising in:

• Semiconductor Design & Nano-electronics

• Cybersecurity & AI/ML

• Robotics & IoT

• Medical Electronics (HealthTech)

Impact by the Numbers

As of late February 2026, the ripple effect of this capital injection has already yielded significant socio-economic returns:

• Job Creation: Over 22,700 high-skilled jobs have been generated within the supported startups.

• Intellectual Property: The companies have successfully filed or acquired more than 300 IPs, reinforcing India’s domestic design capabilities.

• Profitable Exits: The government has already realised ₹173.88 crore from 37 successful exits, proving that DeepTech ventures are becoming increasingly viable for investors.

Geographic Distribution: Bangalore Leads the Charge

While the government aims for pan-India growth, the current investment data shows a strong concentration in existing tech corridors. Bangalore remains the undisputed leader, housing 88 of the 128 funded startups.

A Strategic Pivot Toward Self-Reliance

This news comes on the heels of the Ministry of Electronics and IT (MeitY) approving 29 additional projects under the Electronics Component Manufacturing Scheme, involving a cumulative investment of ₹7,104 crore.

By focusing on the “Daughter Fund” model, the government ensures that capital is managed by industry experts while maintaining a minority stake—a move designed to encourage private venture capital to take more “brave” bets on hardware and indigenous R&D rather than just consumer-facing software apps.

“The goal is to build a self-sustaining electronics ecosystem,” stated the Ministry. “We aren’t just looking for the next ‘unicorn’; we are looking for the next breakthrough in Indian-owned IP.”

By: Shreya Bansal, Sub-Editor

The post Govt Infuses ₹258 Crore Into 128 Startups to Drive DeepTech and IP Creation appeared first on ELE Times.

КПІ ім. Ігоря Сікорського зберігає сильні позиції в рейтингу QS World University Rankings by Subject 2026 kpi вт, 03/31/2026 - 11:42

Голос "Академіка Вернадського" чуємо завдяки випускникові КПІ Інформація КП вт, 03/31/2026 - 11:29

As the global transition toward industrial automation and smart living accelerates, the security and processing efficiency of microcontrollers (MCUs) have become decisive factors for enterprises’ success in the business-to-business market. Nuvoton Technology has announced the launch of its new NuMicro M3331 series 32-bit microcontroller. Powered by the Arm Cortex-M33 core, the M3331 series delivers exceptional performance at operating frequencies of up to 180 MHz and integrates TrustZone technology, providing a robust hardware foundation for industrial control, smart factories, smart buildings, and renewable energy.

The M3331 series is more than just a hardware platform; it is an integrated solution designed to address the challenges customers face when processing complex control algorithms and protecting intellectual property (IP). Featuring the Cortex-M33 core with built-in DSP instruction set and a single-precision floating point unit (FPU), it runs up to 180 MHz. The M3331 series is built with comprehensive security mechanisms. Through hardware-level Secure Boot, it ensures that the system executes only certified and authorised firmware from startup, establishing an immutable root of trust. To protect core IP assets, it features eXecute-Only-Memory (XOM) to safeguard core algorithms and eliminate the risk of code leakage. Additionally, the TrustZone technology partitions a secure execution environment to effectively defend against malicious attacks.

Designed for reliability, the M3331 series supports a wide operating temperature range from -40°C to +105°C and exhibits superior interference resistance (ESD HBM 4 kV / EFT 4.4 kV), significantly reducing the risk of downtime caused by environmental factors. To further enhance system reliability, the 512 KB Flash memory supports Error Correction Code (ECC) for detecting and repairing bit-flip errors. Furthermore, within the 320 KB SRAM, a hardware parity check is provided for the 64 KB core area, achieving true industrial-grade system resilience.

To meet the diverse communication demands of the IoT era, the M3331 series introduces an I3C interface and two CAN FD controllers, greatly increasing data throughput between sensors and control nodes. For high-speed peripherals and mass storage, it includes a built-in USB 2.0 High-Speed OTG controller (with on-chip PHY) and an SDH (Secure Digital Host Controller) interface, delivering exceptional performance for both gaming products requiring low-latency transmission and smart consumer devices needing high-bandwidth storage.

Moreover, the M3331 series features a 12-bit ADC with a sampling rate of up to 4.2 Msps, accurately capturing subtle changes in analogue signals. With up to 48 PWM outputs, it provides precise control solutions for professional photography lighting and stage lighting. Specifically, the series is equipped with ELLSI (Enhanced LED Light Strip Interface) and up to 10 LLSI (LED Light Strip Interface) interfaces, supporting next-generation gaming ARGB LED control protocols. This offloads the CPU and reduces development difficulty, enabling brilliant and fluid dynamic LED effects. The M3331 series offers a variety of package options, from the compact QFN 33 (4×4 mm) to the high-pin-count LQFP 128 (14×14 mm), helping customers optimise their PCB layouts.

To accelerate time-to-market, Nuvoton provides NuMaker-M3333KI and NuMaker-M3334KI evaluation boards, along with full support for mainstream RTOS (FreeRTOS, Zephyr, RT-Thread) and GUI libraries (emWin, LVGL). This ecosystem empowers customers to build stable system solutions rapidly.

The M3331 series consists of two subseries: the M3333 series (without USB 2.0 support) and the M3334 series (with USB 2.0 support).

The post Nuvoton Launches Upgraded Driving Smart Device, NuMicro M3331 Series MCU appeared first on ELE Times.

Toshiba Corp of Kawasaki, Japan has signed a memorandum of understanding (MoU) to start discussions regarding a business integration of the semiconductor business of its subsidiary Toshiba Electronic Devices & Storage Corp (TDSC), the semiconductor business of ROHM Co Ltd, and the power device business of Mitsubishi Electric Corp. The MoU was signed with Japan Industrial Partners Inc (JIP), TBJ Holdings Corp (TBJH), ROHM, and Mitsubishi Electric...

I have a brass annealer project and thought that it will be easy to make with protoboard. it was not, at least not for me. The welder tip was too large and there are bad joints everywhere. well, if it works🤷 submitted by /u/rcplaner [link] [comments]

How easy is it to analyze and optimize how much power the device connected to a smart plug is drawing? The answer depends in part on which hardware and firmware version you’re running.

Next up in my ongoing TP-Link smart home device ecosystem series of hands-on evaluations and teardowns:

• Tapo or Kasa: Which TP-Link ecosystem best suits ya?
• TP-Link’s Kasa HS103: A smart plug with solid network connectivity
• TP-Link’s Kasa EP10: If at first it doesn’t connect, buy, buy again

is the EP25 smart plug, which builds on the EP10 foundation with two feature set additions: Apple HomeKit (and Siri, for that matter) support, along with energy monitoring capabilities.

I bought a two-pack (with an associated “P2” product name suffix) from Amazon’s Resale (formerly Warehouse) sub-site for $13.29 plus tax during a 30%-off promotion last November. They also come in an “EP25P4” four-pack version. I’ll start with some stock photos:

An uncertain lineage

Although I’ve identified the EP25 as the enhanced sibling of the EP10, particularly referencing the naming-format commonality, those of you who’ve already analyzed the above graphic with device dimensions (not to mention the side switch location) might understandably be confused. Doesn’t it look more like the earlier, beefier, HS103? Indeed, it does. Here it is below the EP10:

And now underneath the HS103:

Perhaps the larger chassis was necessary to fit the additional feature-implementing circuitry? There’s one way to find out for sure; take it apart. So, let’s start, as usual with some box shots, as usual accompanied by a 0.75″ (19.1 mm) diameter U.S. penny for size comparison purposes:

This isn’t what the box backside originally looked like, actually:

When it arrived, there was a barcode-inclusive sticker stuck to it, as is typical with products that cycle back through the Amazon Resale sub-site after initial sale-then-customer return:

But stuck to it was something I’d not experienced before: another sticker, with a smaller black rectangle near its center:

I had a sneaking suspicion that I’d find a RFID or other tracking tag on the other side. I was right:

Continuing around the outer package sides:

Packaging assault

Judging from the already-severed clear tape on the bottom of the box, in contrast to the still-intact tape holding the top flap in place, I assumed the original owner got inside through the bottom-end pathway:

Yup. I don’t know what surprises me more (and I’ve also seen it plenty of times before): how brutishly some folks mangle the various packaging piece(s) to get to the device(s) inside, or that they still have the impudence to return the goods for refund afterwards. Now to cut the top’s transparent tape and try out the alternative entry path:

At least the original owner was thoughtful enough to put the sliver of quick-install literature back in the box prior to returning. Although, on second thought, he or she probably never even got to it before sending everything back. There was also this, reflective of its Apple protocol-friendliness:

You also may have already noticed in the earlier bottom-view open-box shot that one of the devices inside was still encased by a protective translucent sleeve, while that of the other device was missing. I went with the latter as my teardown victim, operating under the theory that its still-plastic-covered sibling was unused and therefore most likely to still be functional for future hands-on evaluation coverage purposes. Here’s our patient:

Monitoring implementation variability

This last shot of the underside of the device:

Specifically, this closeup of the specs, including the all-important FCC ID (2AXJ4KP125M):

is as good a time as any to explain the background to my “The answer depends in part on which hardware and firmware version you’re running” comment in this post’s subtitle. Note the following lines of prose on the product support pages for the EP25P2 and EP25P4:

Vx.0=Vx.6/Vx.8 (eg:V1.0=V1.6/V1.8)
Vx.x0=Vx.x6/Vx.x8 (eg:V1.20=V1.26/V1.28)
Vx.30=Vx.32 (eg:V3.30=V3.32)

I’d mentioned in the prior teardown in this series that TP-Link tends to cycle through numerous hardware revisions throughout a product’s life, with each hardware iteration accompanied by multiple firmware versions, and the cadence combination resulting in inconsistent functionality (said another way: bugs). The EP25 is no exception to this general rule. That said, “inconsistent functionality” seemingly is particularly notable in this product case (grammatical tweaks by yours truly):

On Amazon, I bought a 2-unit box set of the EP25P2 (“Hardware 2.6” in the Kasa app), and a 4-unit box of the EP25P4 (“Hardware 1.0” in the Kasa app). They market them as the exact same product, but the EP25P2 has much better energy and power consumption data and graphs, and a cost tool. The other just has a crude power read out. It seems like something they should’ve been clear about, and like something they could fix in the app software. I’m annoyed they did this and will return the EP25P4.

FWIW, looking back both at the device bottom closeup and the earlier bottom box shot, I’m guessing “US/2.6” references hardware v2.6. Again: . Curiously, the four-pack (EP25P4) support page lists three hardware versions (V1.60, V1.80 and V2.60), albeit not the V1.0 h/w mentioned in the earlier Reddit post…and the two-pack (EP25P2) page mentions only V2.60.

Unto the breach, dear friends

Time to delve inside. The case-disassembly methodology was unsurprisingly identical to that for the earlier HS103, so in the interest of brevity I’ll spare you another iteration of the full image suite of steps. See the earlier teardown for ‘em; here’s today’s teardown subset. One upside this second time around: no blood loss by yours truly!

As before, I ‘spect this is the assembly subset that you’re all most interested in:

once again based on (among other things) a Hongfa HF32FV-16 relay (the tan rectangular “box” at far right). Multiple products, along with multiple hardware versions for each, may evolve in a general sense, but some things stay the same…

Detailing the “smarts”

And specifically, here’s the “action” end:

From this side, the embedded antenna is visible; the PCB is otherwise bare:

You can see the antenna from the other side, too, plus a more broadly interesting presentation:

The PCB “lay of the land” is reminiscent of that inside February’s HS103, including the respective switch and LED locations:

This time, however, the prior design’s Realtek RTL8710 has been upgraded to the dual-core RTL8720 (PDF), whose beefier processing “chops” are presumably helpful for implementing the added energy monitoring and HomeKit protocol capabilities, as well as with expanded internal RAM and (optional integrated) flash memory. In this particular design, however, the flash memory is external, taking the form of an Eon Silicon Solution EN25Q32B 32 Mbit SPI serial device. It’s in the upper right corner of the PCB, next to the LED and occupying one of the IC sites you might have already noticed was unpopulated in the HS103 implementation. The other previously unpopulated IC site, below the EN25QH32B, now houses a Shanghei Belling BL0937 (PDF) single-phase energy monitoring IC. Eureka!

Tying up loose ends

As with its TP-Link (but not more amenable Amazon) smart plug predecessors, I was unable to wedge the EP25’s PCB away from the rear half of its enclosure, so there’ll be no circuit board backside photos for you…from me, at least. Alternatively, you can always check out the ones published by the FCC. If you do, you may walk away amazed (as I was) by the total area dominance by multiple large globs of solder.

In closing, I thought I’d share a somewhat related video I found while doing my research. It’s a review of the HS110, the energy monitoring variant of TP-Link’s original HS100 smart plug that I tore down nine years back:

As those Virginia Slims commercials used to say, “You’ve come a long way.” And with that, I’ll turn it over to you for your thoughts in the comments!

—Brian Dipert is the Principal at Sierra Media and a former technical editor at EDN Magazine, where he still regularly contributes as a freelancer.

Related Content

• Tapo or Kasa: Which TP-Link ecosystem best suits ya?
• TP-Link’s Kasa HS103: A smart plug with solid network connectivity
• TP-Link’s Kasa EP10: If at first it doesn’t connect, buy, buy again

The post TP-Link’s Kasa EP25: Energy monitoring for a hoped-for utility bill nose-dive appeared first on EDN.

NXP’s TEF8388 RF CMOS automotive radar transceiver supports Level 2+ and Level 3 ADAS, with a roadmap toward higher levels of automation. Operating in the 76- to 81-GHz FMCW radar band, it provides 8 transmitters and 8 receivers (8T8R), scalable to 32T32R configurations for both entry-level and high-performance systems. Paired with NXP radar processors, it forms an imaging radar platform that addresses diverse performance, cost, and regulatory requirements across global markets.

The TEF8388 delivers strong RF performance—14 dBm Pout and 12 dB NF—while keeping power consumption comparable to less integrated 3T4R devices. An on-chip M7 core provides flexible chirp programming, calibration, and functional safety management.

Occupying a 16×16-mm footprint, the TEF8388 uses an optimized pin layout and strategic launcher placement to enhance channel isolation and signal quality. It meets AEC-Q100 and ISO 26262 SEooC ASIL B requirements and operates over a junction temperature range of –40 °C to +150 °C.

Development support for lead customers is available now. Mass-market support will follow later in 2026. 

TEF8388 product page 

NXP Semiconductors 

The post Radar transceiver scales for automated driving appeared first on EDN.

A half-wave LLC (HWLLC) platform from Renesas includes four controller ICs rated for up to 500 W for high-speed chargers. The HWLLC AC/DC converter topology scales from 100 W to 500 W, enabling chargers for power tools, e-bikes, and other appliances without the size, heat, and efficiency penalties of legacy topologies.

Combined in a 240-W USB EPR power adapter design, the HWLLC approach achieves a power density of 3 W/cm³ and 96.5% peak efficiency—described as the industry’s highest power density. The 500-W envelope broadens application range, while USB-C EPR capability enables a move beyond 100-W charging.

At the heart of the lineup is the RRW11011, an AC/DC primary-side digital controller with interleaved PFC and HWLLC operation. It delivers a wide 5-V to 48-V output for USB 3.1/3.2 EPR and other variable-load charging systems. The boost PFC stage minimizes ripple, total harmonic distortion, and EMI, while digital two-stage control enhances efficiency and reduces audible noise.

The platform also includes the RRW30120 USB PD 3.2 EPR controller with secondary-side regulation, the RRW40120 600-V half-bridge gate driver optimized for SuperGaN FETs and MOSFETs, and the RRW43110 synchronous rectifier controller.

The RRW11011, RRW30120, RRW40120, and RRW43110 are now in production, and samples are available for evaluation.

Renesas Electronics 

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QSiC Dual3 1200-V half-bridge MOSFET modules from SemiQ address the efficiency and thermal demands of liquid-cooled AI data centers. Two of the series’ six devices offer an RDS(on) of just 1 mΩ and achieve a power density of 240 W/in.3 in a 62×152-mm package. The modules are available with or without a parallel Schottky barrier diode to further reduce switching losses in high-temperature environments.

QSiC Dual3 is designed to replace silicon IGBT modules with minimal redesign, reducing both size and weight while maintaining efficiency. All SiC MOSFET die are screened using wafer-level gate-oxide burn-in tests exceeding 1350 V. The modules also feature low junction-to-case thermal resistance, enabling the use of smaller, lighter heatsinks.

The Dual3 lineup includes the following part numbers:

Rated for junction temperatures from −40°C to +175°C, the QSiC modules are also suited for grid converters in energy storage systems, industrial motor drives, uninterruptible power supplies, and EV applications.

Learn more about the QSiC Dual3 modules here.

SemiQ

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The SAM9X75D5M from Microchip is a hybrid SiP for automotive HMI applications, integrating an 800‑MHz ARM926EJ‑S 32‑bit processor with 512 Mbits of DDR2 SDRAM. The package also includes a 24‑bit LCD controller supporting displays up to 10 in. with XGA resolution (1024×768), simplifying high-performance graphical interfaces.

This hybrid SiP combines MPU-class processing with high-density memory in a single package, reducing PCB complexity while maintaining MCU-style development workflows. For automotive and e-mobility HMIs, it offers real-time OS support and flexible display and camera interfaces, including MIPI DSI, LVDS, RGB, MIPI CSI, and 12-bit parallel I/F.

AEC-Q100 Grade 2 qualified, the SAM9X75D5M provides CAN FD, USB, and Gigabit Ethernet connectivity with Time-Sensitive Networking (TSN) capability. It also integrates 2D graphics, audio, and advanced security functions.

The device comes in a 243‑ball BGA package (part number SAM9X75D5M‑V/4TBVAO) and is priced at $9.12 each in 5000‑unit quantities. Variants with 1 Gbit and 2 Gbits of memory are now sampling.

SAM9X75D5M product page 

Microchip Technology 

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Semtech’s TDS5311P circuit protection device delivers near-constant clamping voltage for 48-V USB PD EPR applications. A member of the SurgeSwitch family, it protects a single voltage bus or data line operating at up to 53 V in devices and systems requiring industrial-grade reliability.

Unlike conventional TVS diodes, the TDS5311P uses a surge-rated FET as the main electrical overstress (EOS) protection element. It maintains a nearly constant clamping voltage from the first microsecond of a surge event through the maximum rated current across the full −40°C to +125°C industrial temperature range.

The TDS5311P is rated for transient current up to 24 A (8/20 µs) and peak pulse power of 1512 W (8/20 µs). It meets the IEC 61000-4-5 industrial surge standard of ±1 kV (RS = 42 Ω, CS = 0.5 µF), as well as IEC 61000-4-2 ESD withstand levels of ±20 kV (contact) and ±25 kV (air). Typical clamping voltage is 60 V at 24 A (8/20 µs).

Housed in a 2.0×2.0-mm, 6-pin DFN package, the TDS5311P conserves PCB area compared with SMAJ and SMAB packages. Supplied on tape and reel in 3000-unit quantities, the device costs $0.38256 each ($1147.68 per reel).

TDS5311P product page 

Semtech

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Deepak Shankar, founder of Mirabilis Design and developer of VisualSim Architect platform for chip and system designs, has created this cartoon for electronics design engineers.

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