Збирач потоків

Risks come in more than one form. There are risks that arise from science and technology, and there are risks that arise from human motivations, which are not always of an obvious sort. This is about the latter.

I had a client company that was owned by a husband and wife for whom I had once solved a power supply thermal runaway problem. I had measured temperature rise versus time and temperature fall versus time, and of course, the two were not exactly the same. Their difference was quite pronounced when I first looked at the issue, but they were almost identical to each other after I had solved their problem. If you’re curious about that, please see the How2Power article here. 

A couple of years went by, and I got a call from that same company about a different power supply that also seemed to have a thermal runaway problem. By then, sadly, the husband had passed away, and only the wife remained to run the business.

During the first time frame, the wife had displayed a hair-trigger temper. Any moment of uncertainty as events unfolded would result in a raging torrent from her, to which her husband would make great efforts to calm her down. I would hear lines like “It’s okay. It’s oh-kay! Please relax. Things are going well.” to which she would then go silent, but now she didn’t have anyone to give her any assurance when it was needed.

An employee who had been promoted to Chief Engineer was my new point of contact. I explained to him that I would examine the thermal rise and thermal fall traits of this new power supply to see if indeed the same situation pertained as it did in the first case or not.

“There’s no need for that. I’ve already made those measurements.” He handed me a sheet of paper with columns of numbers, purportedly the data I had planned to acquire. That night, I examined those numbers and discovered that if you plotted the thermal rise and inverted a plot of the thermal fall, the two curves precisely lined up and were EXACTLY the same!! There was absolutely zero difference. They were totally spot on, no ifs, ands, buts, hows, whys, or wherefores, exactly the same, which meant that the rising and falling curves given to me were not the results of actual testing. They were false.

Confronted with a Chief Engineer whom I then knew to be dishonest and confronted with the woman whom I knew to be extremely volatile and prone to bursts of rage, I assessed the risk of dealing with it all to be unacceptable.

I made up some excuse (I don’t remember what it was) and declined to offer my services.

John Dunn is an electronics consultant and a graduate of The Polytechnic Institute of Brooklyn (BSEE) and of New York University (MSEE).

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As AI workloads extend across nearly every technology sector, systems must move more data, use memory more efficiently, and respond more predictably than traditional design methodologies allow. These pressures are exposing limitations in conventional system-on-chip (SoC) architectures as compute becomes increasingly heterogeneous and traffic patterns become more complex.

Modern SoCs integrate CPUs, GPUs, NPUs, and specialized accelerators that must operate concurrently, placing unprecedented strain on memory hierarchies and interconnects. To Keep processing units fully utilized requires high-bandwidth, low-latency access to data, making the memory hierarchy as critical to overall system effectiveness as raw performance.

On-chip interconnects move data quickly and predictably, but once requests reach external memory, latency increases, and timing becomes less consistent. As more data accesses go off chip, the gap between compute throughput and data availability widens. In these conditions, processing engines stall while waiting for memory transactions to complete, creating data starvation.

The role of last-level cache

To mitigate this imbalance, SoC designers are increasingly turning to last-level cache (LLC). Positioned between external memory and internal subsystems, LLC stores frequently accessed data close to compute resources, allowing requests to be served with significantly lower latency.

Unlike static buffers, an LLC dynamically fetches and evicts cache lines based on runtime behavior without direct CPU intervention. When deployed effectively, this architectural layer delivers measurable benefits, including substantial reductions in external memory traffic and power consumption.

Simply including an LLC does not guarantee improved performance. Configuring the cache correctly is a complex task that must account for workload characteristics, compute-unit behavior, and real-time constraints. Poorly chosen parameters can waste area without meaningful gains, while under-provisioned configurations may fail to alleviate memory bottlenecks.

Architects must carefully determine cache capacity, the number of cache instances, and internal banking structures to support sufficient parallelism. Partitioning strategies must also be defined to ensure that individual IP blocks receive the bandwidth and predictability they require. While some settings can be adjusted later through software, foundational decisions on cache size, banking, and associativity must be finalized early in the development cycle.

The role of last-level cache is shown in successful designs. Source: Arteris

Factors influencing cache behavior

Banking configuration illustrates this trade-off clearly. Increasing the number of cache banks improves internal parallelism and throughput, but it also increases silicon area. Workloads with largely sequential access patterns may see limited benefit from aggressive banking.

In contrast, highly parallel workloads, especially those driven by AI accelerators or GPUs, require substantial internal concurrency to maintain utilization. Because these characteristics vary by application, banking decisions must be informed by realistic workload analysis during the architectural phase.

Cache capacity is just as important. A cache that is too small struggles to achieve acceptable hit rates, pushing excessive traffic to external memory. Conversely, oversizing the cache often yields diminishing returns relative to the additional area consumed. The optimal balance depends on actual runtime behavior rather than theoretical assumptions.

In practice, acceptable hit rates vary widely. Some systems can tolerate moderate miss rates if latency and power reductions outweigh the cost, while real-time applications demand consistently high hit rates to maintain deterministic behavior.

This variability underscores why no single LLC configuration is universally optimal. Mobile devices may require only a few megabytes of cache to balance power efficiency and responsiveness. At the same time, servers and HPC platforms often deploy tens or hundreds of megabytes to reduce DRAM pressure. Despite these differences, successful designs rely on a common principle in which cache parameters are derived from the workloads the system will actually execute.

Managing shared caches

Diversity in system demands further complicates how an LLC must be structured. Automotive chips built around concurrent vision processing and strict timing requirements operate under very different constraints than data-center platforms optimized for accelerator-heavy inference at scale. Even within a single chip, CPUs, accelerators, and I/O subsystems generate distinct access patterns with different latency sensitivities.

The LLC must accommodate all of them without allowing one workload to interfere with another’s real-time guarantees. This makes early understanding of system-level access behavior essential, since cache configuration otherwise becomes speculative at best.

Partitioning provides a powerful mechanism for preserving determinism in such environments. By allocating portions of cache capacity to specific clients, architects can prevent high-bandwidth workloads from starving latency-sensitive subsystems. This capability is particularly critical in environments that must meet strict timing guarantees. Partition sizes must be tuned carefully, as oversizing wastes area while undersizing risks violating latency requirements.

Configuring a last-level cache is ultimately a multidimensional challenge shaped by workload demands, compute topology, latency requirements, and silicon constraints. Achieving the right balance between performance, determinism, power, and area depends on understanding how an SoC behaves under real operating conditions.

To address this, SoC teams increasingly rely on system-level simulation using realistic data flow profiles generated by multiple on-chip request sources. This approach allows teams to evaluate cache behavior before key architectural decisions are finalized. It helps identify bottlenecks, validate cache sizing, and determine when isolation mechanisms such as partitioning are required to preserve real-time guarantees.

Arteris developed its CodaCache IP, which operates as a configurable last-level cache between on-chip initiators and different types of external memories such as DDR-DRAM, HBM and even NVM for execution in place (EIP) use cases. With CodaCache, architects can equip their SoC fabric with the optimal configuration to address intelligent, scalable, and automated data management in a wide range of applications.

Andre Bonnardot is product marketing manager at Arteris.

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Texas Instruments announced accelerating the safe deployment of humanoid robots into the real world with NVIDIA. By combining TI’s real-time motor control, sensing, radar and power technologies with NVIDIA’s advanced robotics compute, Ethernet-based sensing and simulation technologies, robotics developers can validate perception, actuation and safety earlier and more accurately. TI connects NVIDIA physical AI compute to real-world applications with deterministic control, sensing, power, and safety at every joint and subsystem. This partnership will help developers move faster from virtual development to production-ready, scalable and safety-compliant systems.

As part of this collaboration, TI designed a sensor fusion solution by integrating its mmWave radar technology with NVIDIA Jetson Thor using NVIDIA Holoscan Sensor Bridge to enable low-latency, 3D perception and safety awareness for humanoid robots. TI will showcase the solution at NVIDIA GTC, March 16–19, 2026, in San Jose, California.

“The next generation of physical AI requires more than just advanced compute – it demands seamless integration between sensing, control, power and safety systems,” said Giovanni Campanella, general manager of industrial automation and robotics at TI. “TI’s comprehensive portfolio bridges the gap between NVIDIA’s powerful AI compute and real-world applications, enabling developers to validate complete humanoid systems earlier in development. This integrated approach will help accelerate the evolution from prototypes to commercially viable humanoid robots operating safely alongside humans.”

“The safe operation of humanoid robots in unpredictable environments requires a massive leap in processing power to synchronise complex AI models with real-time sensor data and motor controls,” said Deepu Talla, vice president of robotics and edge AI at NVIDIA. “The integration of Texas Instruments’ sensing and power management technologies with the NVIDIA Jetson Thor platform provides developers with a functional safety-capable foundation to accelerate the deployment of next-generation physical AI.”

Enabling safer humanoid robots with real-time sensor fusion technology

TI’s mmWave radar sensor, IWR6243, connected via Ethernet to NVIDIA Jetson Thor, enables scalable low-latency, 3D perception and safety awareness for physical AI applications. By fusing camera and radar data, the solution improves object detection, localisation, and tracking while reducing false positives for confident, real-time decision-making in humanoid robots.

This solution enables human-like perception that works reliably in challenging conditions – from low light and bright glare to fog and dust indoors and outdoors – and addresses a critical safety gap that has limited real-world deployment of humanoid robots. For example, while cameras may not reliably detect glass doors or reflective surfaces, radar provides consistent detection of these transparent obstacles, enabling smooth navigation in places like office buildings, hospitals and retail environments.

TI at NVIDIA GTC 

TI will present its technologies at NVIDIA GTC in booth 169 at the San Jose McEnery Convention Centre. TI and D3 Embedded’s live demonstration, “Real-time sensor fusion for reliable robotic perception with Holoscan,” showcases how TI’s mmWave radar technology integrates with NVIDIA’s Jetson Thor and Holoscan ecosystem using an end-to-end software processing chain and visualisation from D3 Embedded.

On Wednesday, March 18, from 3:00-3:40 p.m. PT, TI’s Giovanni Campanella will participate in a lightning talk, “The Edge of the Edge: Redefining GPU-Enabled AI Sensor Processing.” Campanella will discuss how the tight integration of sensing, networking and GPUs is enabling real-time physical AI at the edge of industrial systems.

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Everspin Technologies, the world’s leading developer and manufacturer of magnetoresistive random access memory (MRAM) persistent memory solutions, announced continued progress across its high-reliability (HR) PERSYST xSPI STT-MRAM portfolio, including the completion of full production qualification for its 64Mb MRAM and the expansion of the family to a new 256Mb density.

The HR 64Mb xSPI STT-MRAM has now completed full production qualification for the AEC-Q100 Grade 1 specification. It is currently available for customer orders and supports high-volume production programs, with inventory available through Everspin’s authorised distributors worldwide.

The 128Mb xSPI STT-MRAM is expected to complete production qualification in May 2026, and a new 256Mb option is scheduled to complete full production qualification in July 2026, with volume availability expected in the second half of 2026.

“Advancing our high-reliability product family through production qualification and expanding density options reflects steady progress against our technology roadmap,” said Sanjeev Aggarwal, president and CEO of Everspin Technologies. “Customers designing long-lifecycle systems require validated memory solutions with predictable performance, and we are extending the PERSYST platform to meet those needs across a wider range of densities.”

The addition of the 256Mb density enables higher-capacity persistent memory designs within the same xSPI-based architecture. Together with the 64Mb and 128Mb xSPI STT-MRAM products, the expanded Hi-Rel portfolio provides scalable options for applications operating across extended temperature ranges and demanding reliability environments.

“Production qualification provides the level of confidence required for space and satellite programs moving into long-term deployment,” said Billy Wahng, Chief Technology Officer at Astro Digital. “Everspin’s focus on endurance, data integrity and radiation tolerance addresses the challenges of operating in unpredictable environments.”

These milestones represent continued execution of Everspin’s roadmap to broaden its HR MRAM portfolio for aerospace, defence, automotive, industrial and other mission-critical applications.

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Qualcomm Technologies has used the CMP180 radio communication tester from Rohde & Schwarz to validate advanced multi-antenna capabilities that are designed into its next-generation Wi-Fi 8 platforms, including support for 5×5 MIMO in the 2.4, 5, and 6 GHz bands. Advanced 5×5 MIMO architectures help Wi‑Fi 8 platforms deliver higher capacity and more reliable connectivity across a wider range of real‑world deployment scenarios.

The industry‑leading CMP180 delivers full bandwidth and seamless scalability for testing leading Wi‑Fi 8 chipsets across the entire device lifecycle — from development to production. As a result of this collaboration, Rohde & Schwarz now offers pre‑built test routines and early access to key resources, enabling device manufacturers to accelerate the time‑to‑market of their products.

Wi-Fi 8, based on the IEEE 802.11bn specification, builds on the foundation of Wi-Fi 7 to deliver next-level reliability, efficiency, and seamless mobility. New PHY and MAC layer technologies work together to extend range, improve spectrum utilization, reduce latency, and enable coordinated access across dense environments, setting the stage for ultra-high reliability (UHR) performance. Advanced antenna architectures such as 5×5 MIMO help enhance spatial efficiency and link robustness and provide a more consistent performance in real-world environments.

This new feature set of Wi-Fi 8 will accelerate the wireless LAN performance at home, in offices, venues, and factories, and enable applications like extended reality (XR), AI-assisted applications, real-time cloud gaming, and ultra-high-definition content streaming. To realize these benefits, test equipment must support all bands, full channel bandwidths, multi-antenna operation (MIMO), and deliver best-in-class measurement accuracy at benchmarking test efficiency. Rohde & Schwarz has designed the CMP180 radio communication tester with these capabilities in mind.

The CMP180 enables Qualcomm Technologies to validate essential features of its latest Wi-Fi innovation, including:

• 5×5 MIMO performance to further improve maximum data throughput per link
• Advanced modulation and coding schemes that enable fine‑grained adaptation to real‑time radio conditions.
• Distributed-tone resource units to improve uplink performance under regulatory limits.

Goce Talaganov, Vice President Mobile Radio Testers at Rohde & Schwarz, said: “We are excited to strengthen our long-time collaboration with Qualcomm Technologies to provide a unique testing solution for the next area of Wi-Fi innovations. The CMP180’s advanced features and our close collaboration will empower device manufacturers to bring innovative Wi-Fi 8 products to market quickly and confidently.”

Ganesh Swaminathan, Vice President and General Manager, Wireless Infrastructure and Networking, Qualcomm Technologies, Inc., said: “Qualcomm Technologies’ Wi-Fi 8 portfolio is engineered to deliver next-level performance, reliability, and scalability across a broad range of networking use cases. As part of this portfolio approach, we are advancing innovations such as higher-order MIMO to help increase performance in real-world environments. Our collaboration with Rohde & Schwarz highlights the progress of these capabilities as the Wi-Fi 8 ecosystem builds momentum.”

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Rohde & Schwarz acquired Software Radio Systems (SRS), a specialist in 5G software-defined radio systems. This acquisition further strengthens the position of Rohde & Schwarz in the cellular and wireless communications software market and accelerates development in AI-based test solutions for satellite and next-generation 6G wireless technologies. SRS will continue to operate under its own name as a Rohde & Schwarz group company, maintaining its product roadmap, leadership team and strategic focus. 

The management team at Software Radio Systems, Paul Sutton, Ismael Gomez and Andre Puschmann, will remain. Together with their team at SRS and their new colleagues at Rohde & Schwarz, they will drive innovation in software-defined mobile communications and contribute to the long-term success of the group.

With the acquisition of Software Radio Systems (SRS), Rohde & Schwarz is expanding its software-defined radio (SDR) technology portfolio, strengthening its position in the market for mobile and radiocommunications software, especially in the emerging fields of non-terrestrial networks (NTN) and 6G. The acquisition became effective as of March 5, 2026. Founded in 2012 and headquartered in Ireland, with branches in Barcelona and the USA, SRS has grown from a startup into a globally recognised innovator in mobile and radiocommunications software. The company has established itself as a key player in a highly competitive market through deep technical expertise, product innovation and a strong commitment to open and interoperable network architectures.

By integrating SRS, Rohde & Schwarz decisively expands its capabilities in software-defined radio technology to better serve existing market segments and tap new business opportunities. At the same time, SRS enters a new phase of accelerated growth. With access to deep technical resources from Rohde & Schwarz, global reach and long-term strategic stability, SRS is ideally positioned to scale its technology, expand internationally and execute its long-term mission. The combination of Rohde & Schwarz leadership in test and measurement and RAN expertise from SRS creates powerful synergies that will further advance software-defined mobile network solutions.

Goce Talaganov, Vice President Mobile Radio Testers at Rohde & Schwarz, explains: “I am very pleased that Software Radio Systems is becoming part of the Rohde & Schwarz group. SRS combines extensive telecommunications and wireless expertise with agile software development, making it the ideal complement to our mobile radio testing portfolio, which will benefit the customers of both companies. What SRS and its employees have built up over the past few years is a real success story that you don’t often see. From now on, we will work together to push the boundaries of the technically possible even further, to leverage new synergies and to make an impact on the market.”

Paul Sutton, Chief Executive Officer and co-founder of Software Radio Systems, is ready for the future. “Joining the Rohde & Schwarz group is a proud moment for everyone at SRS. We will continue to operate as SRS with our existing leadership team and a clear commitment to our strategic priorities. What changes is our ability to scale with speed and accelerate the execution of our roadmap, including key initiatives such as the OCUDU project. With Rohde & Schwarz, we gain the strength of a global technology leader whose deep technical expertise, worldwide presence and long-term perspective enable us to grow faster and think bigger. Together, we will expand the impact of our software-defined solutions and deliver innovation that truly makes a difference for our customers.”

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Courtesy: Synopsys

Advances in memory standards are driving faster and more power-efficient mobile and connected devices, from smartphones and tablets to ultra-thin laptops and wearables.

One such standard is Low Power Double Data Rate (LPDDR), which plays a crucial role in balancing high performance with energy efficiency. The latest iteration of the standard, LPDDR6, represents a big step forward in memory management. Comparing LPDDR6 to its predecessors, LPDDR5 and LPDDR5X, reveals just how quickly mobile memory technology is evolving — and what these advances mean for next-generation devices.

The role of LPDDR memory

LPDDR acts as the main system memory inside electronic devices. Working hand-in-hand with device processors and other components to store and access frequently used data, it helps keep applications, media, and multitasking features running smoothly. LPDDR is optimised for low power usage, compact footprint, and fast data transfer, making it ideal for portable, battery-powered devices.

LPDDR can integrate with Inline Memory Encryption (IME) modules to ensure data confidentiality — both in-use and when stored in off-chip memory. This is achieved through standards-compliant independent cryptographic support for read and write operations, providing robust protection against unauthorised access.

LPDDR memory is also available as automotive-grade Synchronous Dynamic Random-Access Memory (SDRAM), making it the preferred DRAM solution for automotive applications that require strict compliance with automotive standards.

LPDDR5 and LPDDR5X: the previous benchmarks

LPDDR5 marked a big step up in mobile memory when it was introduced in 2019. It delivered data rates up to 6.4 Gbps with improved energy efficiency (through features such as Dynamic Voltage Scaling) and smarter data handling. These upgrades led to longer battery life and better support for demanding applications like 5G connectivity, high-resolution media, and the initial wave of artificial intelligence (AI).

LPDDR5 also added new reliability features and smarter error handling, helping stabilise performance under complex workloads. As a result, devices using LPDDR5 delivered noticeable gains in both speed and overall user experience compared to devices using previous generations of LPDDR SDRAMs.

Introduced in 2021, LPDDR5X offered increased performance (up to 10.67 Gbps) and minor enhancements to LPDDR5’s features. LPDDR5X SDRAMs represent the vast majority of LPDDR SDRAMs shipping today.

LPDDR6: the next generation

Published in July 2025, the new LPDDR6 specification and compliant SDRAMs deliver even more performance, efficiency, and features — all designed to meet the growing demands of next-generation mobile and connected devices. LPDDR6 offers:

• Faster data rates. LPDDR6 is expected to reach up to 14.4 Gbps, a significant increase from LPDDR5X. This extra speed is essential for power-hungry applications like augmented reality, ultra-high-definition video streaming, advanced AI, and automotive electronics, all of which depend on rapid data processing.
• Wider bandwidth. Using 24-bit channels (up to 96 bits per package with 4 channels total), LPDDR6 effectively doubles LPDDR5X’s bandwidth per package. In addition, two 12-bit sub-channels in each channel help improve latency and access.
• Enhanced power management. LPDDR6 introduces more precise control over voltage and power states. This upgrade helps devices run more efficiently and extends their battery life as a result.
• Improved reliability and error correction. As the speed and footprint of LPDDR rise, so too does the risk of data errors — especially in data centres. LPDDR6 addresses this challenge with enhanced RAS (Reliability, Availability, and Serviceability) capabilities, providing robust error correction via Metadata, Advanced ECC, and Link ECC features. These improvements help minimise system glitches and stabilise device performance.

While LPDDR6 builds on LPDDR5 and LPDDR5X’s foundations, some legacy mechanisms were streamlined or replaced to support higher speeds and tighter power control. For example, earlier voltage scaling and command encoding schemes have been reworked to enable more granular power states and improved signal integrity. These changes mean LPDDR6 prioritises advanced efficiency and reliability features over older approaches that were optimised for lower data rates.

The implications for memory design and mobile devices

The improved performance, efficiency, and features of LPDDR6 will have wide-ranging impacts. From a technical perspective, LPDDR6 introduces a variety of upgrades to memory architecture:

• Signal integrity and bank management. Smarter signalling and improved memory bank management reduce latency and maximise data throughput.
• Ultra-low power modes. New power-saving states allow devices to conserve energy when idle, a big advantage for wearables and Internet of Things (IoT) products that run on small batteries.
• The new specification is engineered for seamless integration with the latest processors and chipsets, making it easier for manufacturers to integrate LPDDR6 into their next-generation devices.

These upgrades will enable the creation of mobile devices that offer:

• Faster, smoother performance. Higher data rates mean apps open quicker, multitasking is more efficient, and device operation is smoother.
• Better battery life. Improved power management reduces energy consumption, allowing devices to run longer between charges.
• Greater system stability. Stronger error correction improves reliability and reduces the risk of crashes and data loss.
• Future-proofing. LPDDR6 enables devices to support future advances in mobile computing, connectivity, and multimedia.

The Impact of LPDDR6 on smartphones, laptops, and wearables

LPDDR6 represents a significant step forward in mobile memory technology, delivering faster speeds, increased capacity, improved reliability, and better energy efficiency.

Leveraging silicon-proven interface IP and verification IP solutions — which have also been successfully validated at 10.667 Gb/s for SDRAM — device manufacturers are already upgrading their flagship smartphones, high-end laptops, and innovative wearables with LPDDR6-based memory.

But the transition from LPDDR5X/5 to LPDDR6 is more than just a technical upgrade — it enables new possibilities in mobile computing. As manufacturers adopt the new standard, users can expect devices that are faster, more reliable, and ready to support the next wave of on-device and cloud-connected experiences.

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