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### 1. Original Behavior and Diagnosis * **Symptom:** The device charged and operated normally when connected to the charger, even allowing it to be unplugged and continue working. However, the failure occurred when turning it off; it wouldn't turn back on independently unless the charger was reconnected. * **Diagnosis Process:** Exhaustive tests were performed, ruling out various components like the power button, battery, and motherboard capacitors, ultimately finding a damaged P-type MOSFET in the power section. ### 2. Tools and Materials Needed * Precision multimeter * Soldering station * Flux and isopropyl alcohol * Precision screwdrivers ### 3. Module Disassembly * Carefully remove the screws to open the module. * Separate the pressure tabs. * Carefully lift the back cover where the battery is attached, being mindful of the wiring connected to the main board. ### 4. Repair Procedure * Locate the power circuit section where the P-type MOSFET identified in the diagnosis operates. * Apply flux and use the soldering station to extract the defective component. * Once the P-type MOSFET causing the power-on failure is removed, clean the area with isopropyl alcohol and proceed as needed to restore the power line. ### 5. Subsequent Tests and Reassembly * Test the receiver's autonomous power-on without connecting an external charger. * Correctly align the circuit board inside the casing, securing the buttons and pins. * Close the cover, tighten the screws, and perform the final operational test. submitted by /u/Aarombts [link] [comments]

Discrete device designer and manufacturer Nexperia B.V. of Nijmegen, the Netherlands (which operates wafer fabs in Hamburg, Germany, and Hazel Grove Manchester, UK) says it will explore a strategic collaboration on advanced power semiconductor solutions for automotive applications with Aurobay Technologies, a division of Horse Powertrain Ltd (a joint venture between Renault Group and Geely)...

A compact LED traffic light module for Arduino and other platforms: how it works, how to wire it, and how to test it with simple sequences.

Finland-based Vexlum — which was spun off from Tampere University of Technology’s Optoelectronics Research Centre in 2017 and develops and manufactures high-power semiconductor vertical-external-cavity surface-emitting laser (VECSEL) technology systems — has appointed Erik McKee as president of the Americas. Based in Denver, Colorado, he will oversee operations and growth across North and South America, supporting accelerating demand for the company’s laser technology in quantum, semiconductor, space, medical and other advanced industrial and scientific applications...

⭐ Оголошується набір у творчі колективи Центру культури та мистецтв КПІ kpi вт, 09/01/2026 - 17:00

🏓 Спортивні секції для студентів kpi вт, 09/01/2026 - 16:00

The use of hardware assisted verification (HAV) technologies was once a luxury, “nice to have” technology for IC design. Because of the costs associated with HAV, especially for the “big box” logic emulators, it was mainly leveraged by the larger companies for their largest SoC projects.

Today with even medium complexity SoCs, modern HAV technologies have become far more accessible and affordable at a time when the use of HAV has become an imperative for helping design teams get massive SoC-powered products to market on time.

In today’s SoC design world, the issue isn’t strictly getting silicon to function properly. The main issue is ensuring that the SoC and the application software that runs on the SoC work together properly and with the highest efficiency.

Let’s examine a common methodology employed with verifying hardware and software together and where the traditional methodology breaks down. We’ll then look at how EDA vendors are offering modern FPGA-based prototyping systems in their HAV suites that bypass the shortcomings of the older methods.

The HW/SW, “chicken and egg” dilemma

On SoC projects, software development and testing can’t wait until silicon is available; on the other hand, embedded software development would need silicon to run on. As a result, design teams have come up with many techniques to make parallel development work. However, born out of necessity, one in particular has emerged over the years as the preferred methodology.

In this methodology, design teams attempt to separate the software stack into hardware-independent and hardware-dependent portions, separated by an operating-system layer and communicating through well-characterized APIs.

Typically, the larger hardware-independent code can be developed in a server environment with standard debugging techniques, using stubs to stand in for the APIs. Then the designers develop the hardware-dependent portion of the code, while the RTL design takes shape, using a hardware emulation system or perhaps even logic simulation as an execution environment.

But this methodology has its flaws. The first, and most obvious, is that it’s not always easy, or even possible, to determine which portions of the code are really hardware independent.

Dependencies accidentally created deep into the application code could go unnoticed, especially when intensive I/O and high computing loads must meet hard timing deadlines. And software developers often have to make some assumptions about execution speeds, cache sizes, and memory latencies—assumptions that may later prove false.

The second flaw of this older methodology is simply the combination of speed and capacity. In the older methodology, the integration and testing of the software with the RTL model of the chip is generally going to execute too slowly, even on an emulation system, to allow extensive exploration of the entire software stack. This leaves two options.

The first is waiting until first silicon is back and hope and pray all the bugs were caught; but hope is not a strategy and a software workaround or shut down part of the chip may not be feasible or acceptable. The second option is to move to a modern, success-oriented methodology that deals with shortcomings of the traditional hardware/software co-verification methodology.

This methodology is centered around hardware-assisted verification (HAV) solutions in general and FPGA-based prototyping in particular. Modern HAV technologies offer a much better methodology and higher likelihood of success that requires less stress and praying to a deity.

Addressing HW/SW co-verification bottlenecks

The end goal when deploying an HAV methodology is to ensure that not only is the SoC hardware functionally correct but that the software running on the SoC is optimized so the entire product meets spec and is optimized for best functionality, performance, and power. Ideally, the full software stack and the complete RTL design should be tested together as soon as both are sufficiently complete and stable to allow meaningful execution runs.

This gives the development team the opportunity to identify bugs and hardware/software interactions early, and before committing to silicon. And good version control ensures that the software team is working with the current RTL model and that the hardware team knows at once if they have just broken the software.

Speed of the HAV technology is the key. To test the full software stack on the SoC model realistically requires the use of an HAV technology, the FPGA-based prototype system. The model of the SoC under development is programmed onto the FPGAs of the prototyping system, allowing software developers to create software and run the software stack to ensure it works with the system.

An FPGA-based prototyping system will be able to run the full software stack on a realistic model of the SoC logic and memory, fast enough for intensive software and system validation. But what about the model’s interaction with the outside world? Verification requires seeing how the design behaves in continuous operation with real-world data.

In the past, many designs have attempted to circumvent the challenge of verifying their designs in continuous operations by trying to identify patterns of input data that will be most challenging to the system. They would synthesize those patterns as scripts and feed them into the prototyping system to observe its response. Unfortunately, this is ultimately a low-probability approach.

As years of development have illustrated, sometimes a bit too graphically, it’s just not possible to anticipate, for example, what streams of video from HD cameras are going to cause an AI system to miscategorize a traffic situation. And, as any communications engineer can attest, it’s equally impossible to predict the patterns of data that will appear on a real-world Gigabit Ethernet link or PCIe bus. As both ADAS and networking engineers have learned, a-priori analysis is no substitute for massive amounts of real-world data.

Ideally, verification engineers could connect the high-speed FPGA-based prototype directly to the cameras, sensors, actuators, and displays of the real system, and subject the system design to real-world data, in all its randomness, unpredictability, and at its natural speed. That could mean running the FPGA-based prototype system in a moving car, on a live network switch, or in a storage controller in a data center.

However, this raises another question: how to get at-speed or near-speed signals from the real world into the FPGA-based prototype. Design teams have tried several approaches, but once again, one solution is emerging.

Intuitively, it might seem reasonable to just implement the critical interfaces in the FPGA-based prototype. After all, the finished SoC will include those interfaces, so they are a real part of the design. And external networks, buses, and control signals could be connected directly into the prototyping system.

But there are serious issues with this approach. The first is that it will divert important design and verification resources away from the main design project. Yes, these interfaces will be present in the finished SoC, but they will almost certainly be implemented as third-party IP. Assuming that the third-party vendors have already been selected, they may or may not provide FPGA models of their IP for a particular FPGA family.

The models may or may not be accurate reproductions of the ASIC interface blocks’ functionality and will certainly differ in timing. Implementing these interface blocks in the FPGA and verifying them potentially becomes a significant FPGA design project in its own right, drawing on critical interface and FPGA skills that are needed elsewhere in the design.

An alternative is to design external interface adapter cards to connect the real-world signals into the prototype system. Such an adapter can run at full real-world speed on the real-world side, and at the speed required by the FPGA-based prototype on the prototype side. But again, there are significant challenges.

To begin with, no high-speed interface adapter is a trivial design, including power considerations, clocking, board design, connector or cable signal integrity, and so on. Then there is the matter of getting the signals back and forth between the adapter card and the prototype system.

Running cables to the system backplane will introduce timing and signal-integrity questions and will require precise understanding of the FPGA-based prototyping system’s internal design. Designing daughter cards to attach directly to expansion connectors or to the FPGA cards themselves within the prototyping system will require an even more detailed understanding of the system’s electrical, mechanical, and thermal requirements.

A modern solution

Take the case of a family of off-the-shelf extension boards for the Veloce proFPGA CS system. It includes I/O adapters for a range of interfaces, including Gigabit and slower Ethernet, PCIe GEN4, USB, DDR4, various Flash memory interfaces, and a range of connector configurations for bringing the FPGA I/O signals out of the box. Such an I/O board, for example, combines Ethernet on an RJ45 connector, a USB connector with UART, a MIPI 60 connector, and a GPIO header, along with user-definable LEDs.

Figure 1 The Veloce proFPGA CS platform is an entry-level solution in which the UNO desktop system delivers FPGA-based prototyping. Source: Siemens EDA

The extender cards plug directly onto connectors on the Veloce proFPGA CS FPGA boards, minimizing latency and signal-integrity issues. This also saves the user from having to provide external clock and power sources for the boards. Supporting software seamlessly integrates the extension boards into the Veloce proFPGA CS development environment.

Figure 2 The Veloce proFPGA CS boards can be adapted and expanded with the latest FPGA generations and extensions cards equipped with interconnections, interfaces or memories. Source: Siemens EDA

The result is that users can quickly connect an SoC prototype on the Veloce proFPGA CS into the actual environment in which the finished SoC will operate, with the interfaces operating at or near full speed. Software developers can instrument and observe the full software stack executing in the real world, not within the confines of synthetic tests. Hardware engineers can observe hardware/software interactions with live, real-world data at high speeds.

Juergen Jaeger is director of prototyping product strategy at Siemens EDA.

Related Content

• The Growing Use of Hardware-Assisted Verification
• The Case for Hardware-Assisted Verification in Complex SoCs
• Can Hardware-Assisted Verification Save SoC Realization Time?
• Hardware-Assisted Verification: The Real Story Behind Capacity
• Hardware-Assisted Verification: Ideal Foundation for RISC-V Adoption

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Fakery methods, and their impacts on those who are particularly easily fooled, have advanced dramatically in recent times.

My wife and I recently saw the movie Disclosure Day, in which an extra-terrestrial being comes to earth and after much ruckus and travail, is introduced to the world’s population with the advice to “listen”. Frankly, I didn’t much care for the movie, but a lot of people seemed to have enjoyed themselves watching it.

However, a disquieting moment came about just as we were leaving the theater. I heard one woman say to the other that this movie was “proof” that the depiction of an extra-terrestrial alien was real and further “proof” that “the government” is secretly concealing truth from the general public. The fact that the scroll of credits at the end of the movie listed the puppetry experts had made no impression on this lady whatsoever.

If this lady were a close relative of mine, I would be very concerned that she would be a prime target for all kinds of fraudsters seeking to rip her off using pretty much any of the widely publicized scams we see written up in the news lately. What she could seemingly be led to believe was alarming.

Fakery methods have been very much advanced in recent times. Look at this screen shot taken from a Neil deGrasse Tyson video, in which he appears to be in conversation with an alien from “Andromeda”.

I think in looking at this image that Mr. Tyson’s forehead is shown slightly higher than reality, but that isn’t all that obvious.

As to the alien, nothing more need be said.

John Dunn is an electronics consultant and a graduate of The Polytechnic Institute of Brooklyn (BSEE) and of New York University (MSEE).

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Cree LED Inc of Durham, NC, USA (a Penguin Solutions brand) and US-based Promier Products Inc (trading as LitezAll) have reached a mutually beneficial settlement resolving a patent infringement dispute involving Cree LED’s patents related to LED components used in portable lighting products. As part of the settlement, Cree LED has granted Promier Products a limited license to certain Cree LED patents covering LED components...

Build a compact digital clock using an Arduino Nano ESP32 and a MAX7219-driven 8x32 LED matrix, with WiFi time synchronization, BLE setup, and automatic brightness control.

🎥 Випуск перед вступом. Урочистий випуск слухачів підготовчих курсів КПІ 2026 Інформація КП вт, 09/01/2026 - 14:00

​The Indian Navy received its first indigenous multi-purpose vessel, Samarthak, from Larsen & Toubro at its Kattupalli shipbuilding yard. An indigenous content of 75% indigenous content, marking the next step in India’s initiative to build naval warships indigenously. It was built with features to fulfil various requirements, such as surveillance, maritime patrol, and participation in Humanitarian Assistance and Disaster Relief (HADR) activities. Furthermore, the vessel can successfully carry out launching and recovering of naval targets, use automated systems, and evaluate naval weapons, sensors, etc.

This inherent flexibility should provide the capability for the Navy to employ the ship in an operational role in addition to its testing and evaluation capacity. These vessels are critical because new underwater systems and other unmanned vehicles and new radars and weapons need to be rigorously tested in the natural sea environment before they are widely deployed into operations. The ship was built under a contract for two Multi-Purpose Vessels and demonstrates enhanced cooperation between the Indian Navy and private shipbuilding. Its induction proves the increasing capabilities of Indian companies in designing and building advanced, technically complex naval platforms​.

The post Indian Navy Takes Delivery of Indigenous Multi-Purpose Vessel Samarthak appeared first on ELE Times.

​The 4Th Tri-Services Future Warfare Course has concluded at the Manekshaw Centre, New Delhi, concluding the four weeks allotted for professional military education and strategy discussions. Sponsored by HQ IDS, the course was executed by the Centre for Joint Warfare Studies and offered a platform for interaction between the Army, Navy, and Air Force. Members of the government sector, academia, industrial sector, and strategic think tanks community were also invited.

The curriculum explored topics such as artificial intelligence, autonomous systems, quantum technology, cyberspace warfare, information operations, and cognitive warfare. The training also delved into grey zone conflict and coordinated military operations in the land, sea, air, space, and cyber fields. Participants will take part in lectures, scenario construction, cognitive warfare simulations, field trips, and lectures by military commanders, defence policymakers, researchers, engineers, and other experts.

The purpose of this training is to enable officers, who will participate in planning and making battlefield decisions, to understand how their operational planning and field decisions are being impacted by novel and developing technologies. It is another reflection of the Armed Forces’ greater commitment to joint and tech-focused operations, and it is its 5th edition this year, set to start 16 November to 11 December 2026.

The post Armed Forces Conclude Fourth Future Warfare Course appeared first on ELE Times.

​TATA Advanced Systems Limited has signed a Memorandum of Agreement (MoA) with Javelin Joint Venture, a partnership between Raytheon and Lockheed Martin, on the potential indigenous production of the Javelin anti-tank missile. Under the envisaged agreement, TATA Advanced Systems would become the lead industrial partner for developing final assembly, integration, and component manufacturing in India.

The scope of cooperation between the companies would include the Javelin All-Up Round, which is a complete missile sealed within its launch container and ready for use. Raytheon will provide the guidance electronics and Lockheed Martin will supply sub-assembly kits that India can use to assemble and integrate the weapon locally. Depending on India’s interests in further local content and technology transfer to its manufacturers, the project has the potential to foster a local missile supply chain.

Javelin is an American man-portable, fire-a​nd-forget, anti-tank and multi-purpose guided missile manufactured by Lockheed Martin and is capable of hitting armoured vehicles, fortified positions and other tactical targets. Its seekers can lock and track the target, and once launched, the operator can seek cover from hostile fire. The deal comes amid the Indian Army’s acquisition of a Rs 292 Crore batch of Javelin Systems, and may help reduce weapon availability time while simultaneously promoting deeper domestic engagement in complex weapon production.

The post TATA Teams Up with Javelin JV on Missile Production appeared first on ELE Times.

INS Nipun, the Navy’s second indigenously built Nistar-class diving support vessel, has been commissioned in the Naval Dockyard at Mumbai. The specialised vessel is expected to bolster the Navy’s capabilities in deep-sea diving, submarine rescue, salvage and underwater intervention. Built by Hindustan Shipyard Limited (HSL), INS Nipun is intended to support naval divers during difficult deep-sea dives and also to act as a mother ship for a Deep Submergence Rescue Vehicle (DSRV) or remotely operated vehicles deployed for locating and rescuing a disabled submarine’s crew.

It is the sister ship of the first vessel of the class, INS Nistar, which is already functioning in the Eastern Naval Command. By inducting a ship each on either the Indian Ocean seaboard and the Bay of Bengal, it will enable the Indian Navy to respond with a faster specialised underwater-support capacity across both sectors, and it is a major landmark development for the indigenous shipbuilding sector, as only a small number of navies in the world possess the deep-sea diving and submarine rescue capability available in these platforms. By inducting a ship for the Indian Navy, the capability for assisting partners during any underwater disaster or maritime calamity becomes higher.

The post INS Nipun Commissioned into Indian Navy for Ocean Warfare appeared first on ELE Times.

In what it claims is a breakthrough in micro-LED optical communications, Ennostar Corp of Hsinchu, Taiwan (a provider of integrated optoelectronic solutions, specializing in R&D and manufacturing III–V materials) says that its R&D team has increased the single-channel –3dB modulation bandwidth of its blue micro-LED to 2.1GHz at a current density of 2kA/cm2. The sample further demonstrated a modulation bandwidth of up to 3.3GHz at a current density of 5kA/cm2. These results approach the commercial specifications required for short-reach optical transmission using micro-LEDs, it adds...

The Ministry of Defence has streamlined India’s Defence Export Standard Operating Procedure (SOP) and Open General Export Licence (OGEL) to speed up the process and help the Indian manufacturing sector reach global markets. Except for a few items of non-lethal arms, no stakeholder concurrence will be needed for the shipment of these articles. Similarly, this requirement will not be necessary for exporting goods intended for international tendering or exhibitions. However, protection for high-security zones/sensitive equipment will continue to exist.

The three individual Open General Export Licence procedures are now integrated into a single one. The licence validity period has extended from two years to three years, and the range of eligible countries has widened further; countries covered by United Nations sanctions regimes, arms embargoes, and other security restraints are not eligible. Eligible exporters can use the licence to send multiple batches of specified goods instead of seeking permission for each batch individually.

The reform is to make way for Indian manufacturers entering long-term contracts with foreign original equipment manufacturers. It is felt that the MSMEs in the country will benefit particularly through this, as their consignments of defence products comprising components, protective devices, etc could be exported in a routine manner.

The post Indian Government Softens Defence Exports to Stimulate Domestic Sector appeared first on ELE Times.

NASH Energy, India’s first mass-scale LFP cell manufacturer, will showcase its latest energy storage and energy management solutions at the 50th edition of Middle East Energy 2026, being held from September 1–3 at the Dubai World Trade Centre.

At Booth Z3.E10, NASH Energy will present its capabilities spanning LFP cells, battery packs, battery management systems and energy storage solutions, addressing a range of applications across automotive, electric mobility, industrial and energy sectors.

The company will highlight solutions ranging from battery packs to large-scale energy storage systems, demonstrating its capabilities across the energy technology value chain. With in-house engineering, R&D and manufacturing capabilities, NASH Energy is developing customised energy solutions designed to address the evolving requirements of global customers.

Building Energy Solutions from Cell to System

NASH Energy has an R&D centre in Japan and operates an LFP cell and battery pack manufacturing line in Bengaluru, India. The company has invested significantly in strengthening its R&D and manufacturing capabilities, with the aim of developing and manufacturing advanced energy solutions in India for global markets.

The company’s portfolio includes LFP cells and battery packs designed for applications across electric mobility, industrial systems and energy storage. Its capabilities extend from cell technology and battery-pack development to the integration of battery management and monitoring technologies.

NASH Energy’s energy technology portfolio is complemented by firmware and battery management capabilities developed by NASH Industries, including Battmonx, Battery Management Systems (BMS) and EVolt. These technologies enable battery monitoring, management and automation, supporting the development of connected and intelligent energy applications.

Commenting on the company’s participation, Mr. Sanjay Wadhwa, Chairman & Managing Director, NASH Group, said, “The energy ecosystem is undergoing significant transformation, with growing requirements for reliable energy storage, intelligent battery management and connected technologies. At NASH Energy, we are building capabilities across the energy value chain, from LFP cells and battery packs to integrated energy-storage solutions. Our investments in R&D and manufacturing are focused on developing scalable, application-specific energy solutions from India for global markets. Middle East Energy provides an excellent platform to engage with customers and partners in the region, understand their evolving requirements and demonstrate how our technologies can support the next generation of energy applications.”

NASH Energy’s solutions cater to applications across automotive and electric mobility, renewable energy, industrial equipment, energy storage and other emerging energy applications. The company’s integrated approach combines battery technology, engineering and manufacturing capabilities to support customers from product development through to scalable production.

The Middle East is emerging as an important market for energy storage and intelligent energy solutions as industries and infrastructure increasingly seek reliable, efficient and scalable energy technologies. Through its participation at Middle East Energy 2026, NASH Energy aims to engage with customers, technology partners and industry stakeholders and explore opportunities to develop application-specific solutions for the region.

The post NASH Energy to Showcase Advanced Cell and Energy Solutions at Middle East Energy 2026 in Dubai appeared first on ELE Times.

Історія Київської політехніки в університетській бібліотеці Інформація КП вт, 09/01/2026 - 12:00