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Component organization
![]() | Just thought I’d share a little organization hack I made on the cheap. Dollar store wire dish rack and dollar store hardware boxes. Less than $10 total and makes organizing components a breeze. [link] [comments] |
An FM Generator Circuit Using the Capacitance of a Collector-Base Junction
I built my first DIY synthesizer!
![]() | Hi electronics friends! I’ve been working on this project for a few months, and the 1.0 version of my DIY synthesizer is finally here! I documented the whole process on YouTube: 👉 https://youtu.be/B1KDbnlMJYE[link] [comments] |
adapting an IC the hard way
![]() | For anyone wondering what it is: It's an old Xilinx Spartan II FPGA that was cut from an old custom PCI board. It has been adapted to an prototype board. It's an 8 bit ISA prototype board, however I'm not going to make an ISA card from it. I just ran out of typical prototype boards. I am planning to use this old FPGA to help me make another homebrew computer (glue logic). I am planning this time to make homebrew on a dedicated PCB, so I want to have a playground with that FPGA with all pins reachable to experiment with it before. I could got an adapter, but I couldn't find one locally to get it quickly. This thing took me three days of work in my free time. So, yeah. It works! On last photo teh FPGA is programmed to blink the LED! The RPi Pico acts as JTAG programming cable [link] [comments] |
Accessible breakout boards I built because a visually impaired student of mine couldn't wire circuits with standard components
![]() | submitted by /u/hey_hey_you_you [link] [comments] |
Weekly discussion, complaint, and rant thread
Open to anything, including discussions, complaints, and rants.
Sub rules do not apply, so don't bother reporting incivility, off-topic, or spam.
Reddit-wide rules do apply.
To see the newest posts, sort the comments by "new" (instead of "best" or "top").
[link] [comments]
A resistor-like capacitor and a capacitor-like resistor
![]() | submitted by /u/NEET_FACT0RY [link] [comments] |
Size comparison between GMI-2B and GMI-90
![]() | Recent addition to my collection [link] [comments] |
EEVblog 1704 - WTF? The ANENG 626 Multimeter REVIEW
A Trio of SMARC Compute Modules Meet HMI and Edge AI Needs
Lumentum’s June-quarter revenue and EPS exceed raised guidance
An e-mail delivery problem

For many years, I have been using my IEEE alias e-mail address in the “From” line of outgoing messages and receiving replies back addressed to that alias. Recently, that doesn’t seem to work anymore. If I put ambertec@ieee.org into the “From” line, messages often do not get delivered, as in these three examples below.
Figure 1 Screenshots of several rejected emails when ambertec@ieee.org is used in the “From” field.
The techno-babble of these rejections is different in each case, but the end result is the same: My message was refused for delivery.
I can only reliably send messages now using jdunn4@optimum.net as the “From” entry because, in the interest of “security,” the “From” entry must now match the actual sending address. When I made them match in these three cases, all of the messages were successfully sent to their intended recipients.
This difficulty was first noticed a few months ago for one recipient of my messages, but this issue has spread like some kind of disease to other recipients as well. The utility of the IEEE alias itself has therefore been very much diminished.
John Dunn is an electronics consultant and a graduate of The Polytechnic Institute of Brooklyn (BSEE) and of New York University (MSEE).
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The post An e-mail delivery problem appeared first on EDN.
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India Surges Ahead of China in Smartphone Exports to US
India is now the biggest supplier of smartphones to the US, overtaking China, marking a momentous change in global manufacturing. According to research firm Canalys, cited by the PIB, the share of Indian smartphone imports into the US had abruptly shot up to 44% during April-June 2025, whereas it was meager 13% in the same quarter of the previous year. On the other hand, China saw its share plummeting to just around 25% from 61% in 2024.
Such an extraordinary development has been largely attributed to government interventions like Make in India and the PLI scheme, transforming India’s electronics sector into what it is today.
The Ministry of Electronics & IT recently spoke about the growth journey of India, pointing out its tremendous rise both in production and exports between 2014-15 and 2024-25. From ₹18,000 crore, mobile phone production soared to ₹5.45 lakh crore, while exports surged from just ₹1,500 crore to ₹2 lakh crore a 127-fold increase in exports.
Overall electronics production grew from ₹1.9 lakh crore to ₹11.3 lakh crore, a sixfold increase.
There were only two production units in 2014–15, and by 2024–25, the number had grown to 300 units a massive expansion.
The increase in smartphone exports from India to the United States, which now accounts for 44% of US smartphone imports, is a key factor driving this shift in global manufacturing.This rapid scaling of production, reduction in imports, and emergence as an alternate tech supply chain to China have been largely driven by Make in India and PLI initiatives.
The rise of India as the top exporter of smartphones to the US represents a significant change in the dynamics of global manufacturing. This change has altered the electronics landscape of the nation and is being fueled by strategic initiatives such as the Production Linked Incentive scheme and Make in India.
The post India Surges Ahead of China in Smartphone Exports to US appeared first on ELE Times.
До Дня Державного Прапора та Дня Незалежності України
У КПІ ім. Ігоря Сікорського відбулася урочиста церемонія підняття синьо-жовтого стяга та покладання квітів з нагоди Дня Державного Прапора та Дня Незалежності України
Nuvoton Introduces Automotive-grade, Filter-Free 3W Class-D Audio Amplifier NAU83U25YG
The New High-Efficiency Audio Solution Ideal for Dashboard, eCall, and T-Box Applications
Nuvoton announced NAU83U25YG, a new automotive-grade Class-D audio amplifier. The NAU83U25YG Class-D amplifier features high-efficiency stereo, digital input, and delivers up to 3W (4 Ω load) or 1.7W (8 Ω load) output power. Featuring a two-wire gain adjustment interface, it is the ideal choice for automotive electronics applications such as dashboards, eCall, and T-Box systems.
As automotive electronics enter the era of the “smart cockpit,” vehicle intelligence has become a key industry focus. This trend is driving increasing functional requirements for audio solution providers in automotive applications. Nuvoton Technology strictly adheres to automotive industry standards, offering AEC-Q100 qualified products for automotive applications. To simplify system design, our solutions support digital I2S audio signal input from the vehicle’s main controller, reducing the need for external components and minimizing PCB size. Additionally, our digital amplifiers help prevent circuit interference and effectively solve EMI issues.
The NAU83U25YG stereo Class-D audio amplifier has advanced features like 80 dB PSRR, 90% efficiency, ultra-low quiescent current (i.e. 2.1 mA at 3.7V for 2 channels) and superior EMI performance. It offers lower distortion, reduced background noise, and a wider dynamic range. Additionally, this new amplifier supports comprehensive device protection.
NAU83U25YG Key Features
- Gain Setting via I²C interface, 22 dB to -62 dB
- Powerful Stereo Class-D Amplifier, 2ch x 3.0W (4Ω @ 5V, 10% THD+N)
- Low Output Noise: 18 μVrms @ 0 dB gain
- Comprehensive Device Protection:
- Overcurrent Protection (OCP)
- Undervoltage Lockout (UVLO)
- Overtemperature Protection (OTP)
- Clock Termination Protection (CTP)
- Click-and-Pop Suppression
- Package: QFN-20
- Operating Temperature Range: -40℃ ~ +105℃
- Automotive Grade: AEC-Q100 qualification & TS16949 compliant
Superior EMI Performance, Filter-Free
The NAU83U25YG amplifier stands out by eliminating the need for an external output filter, thanks to its spread-spectrum-oscillator technology and slew-rate control, effectively reducing electromagnetic interference (EMI). Moreover, it offers enhanced immunity and power supply rejection ratio (PSRR) of > 80 dB at 217 Hz. Making the NAU83U25YG an excellent fit for Class-D audio amplifiers in wireless and AM (Amplitude Modulation) frequency band applications.
Leap Forward in Efficiency, Power
The Class-D topology represents a significant leap forward in both power efficiency and noise minimization in audio devices. By generating a binary square wave, Class-D amplifiers efficiently amplify the signal through power device switching. Compared to Class-AB devices, Class-D amplifiers offer power efficiencies that are two-thirds better.
The NAU83U25YG Class-D audio amplifier excels in driving a 4 Ω load with an impressive output power of up to 3W and fast start-up time of just 14 msec.
NAU83U25YG Target Applications
The new Class-D audio amplifier is designed for automotive electronics applications including dashboards, eCall, ADAS (Advanced Driver Assist Systems) and T-Box.
The post Nuvoton Introduces Automotive-grade, Filter-Free 3W Class-D Audio Amplifier NAU83U25YG appeared first on ELE Times.
Cadence Accelerates Development of Billion-Gate AI Designs with Innovative Power Analysis Technology Built on NVIDIA
New Cadence Palladium Dynamic Power Analysis App enables designers of AI/ML chips and systems to create more energy-efficient designs and accelerate time to market
Cadence announced a significant leap forward in the power analysis of pre-silicon designs through its close collaboration with NVIDIA. Leveraging the advanced capabilities of the Cadence Palladium Z3 Enterprise Emulation Platform, utilizing the new Cadence Dynamic Power Analysis (DPA) App, Cadence and NVIDIA have achieved what was previously considered impossible: hardware accelerated dynamic power analysis of billion-gate AI designs, spanning billions of cycles within a few hours with up to 97 percent accuracy. This milestone enables semiconductor and systems developers targeting AI, machine learning (ML) and GPU-accelerated applications to design more energy-efficient systems and accelerate their time to market.
The massive complexity and computational requirements of today’s most advanced semiconductors and systems present a challenge for designers, who have until now been unable to accurately predict their power consumption under realistic conditions. Conventional power analysis tools cannot scale beyond a few hundred thousand cycles without requiring impractical timelines. In close collaboration with NVIDIA, Cadence has overcome these challenges through hardware-assisted power acceleration and parallel processing innovations, enabling previously unattainable precision across billions of cycles in early-stage designs.
“Cadence and NVIDIA are building on our long history of introducing transformative technologies developed through deep collaboration,” said Dhiraj Goswami, corporate vice president and general manager at Cadence. “This project redefined boundaries, processing billions of cycles in as few as two to three hours. This empowers customers to confidently meet aggressive performance and power targets and accelerate their time to silicon.”
“As the era of agentic AI and next-generation AI infrastructure rapidly evolves, engineers need sophisticated tools to design more energy-efficient solutions,” said Narendra Konda, vice president, Hardware Engineering at NVIDIA. “By combining NVIDIA’s accelerated computing expertise with Cadence’s EDA leadership, we’re advancing hardware-accelerated power profiling to enable more precise efficiency in accelerated computing platforms.”
The Palladium Z3 Platform uses the DPA App to accurately estimate power consumption under real-world workloads, allowing functionality, power usage and performance to be verified before tapeout, when the design can still be optimized. Especially useful in AI, ML and GPU-accelerated applications, early power modeling increases energy efficiency while avoiding delays from over- or under-designed semiconductors. Palladium DPA is integrated into the Cadence analysis and implementation solution to allow designers to address power estimation, reduction and signoff throughout the entire design process, resulting in the most efficient silicon and system designs possible.
The post Cadence Accelerates Development of Billion-Gate AI Designs with Innovative Power Analysis Technology Built on NVIDIA appeared first on ELE Times.
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Ranovus’ $100m investment to develop and scale optical semiconductor manufacturing in Ontario
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