Feed aggregator

Upfront in late November 2023’s most recent edition of the “Holiday Shopping Guide for Engineers” series was my recommendation to pick up a recently-introduced Raspberry Pi 5. But here we are, two months later as I write these words, and the Raspberry Pi 5 is still essentially sold out (echoing, ironically, my commentary introducing that shopping guide section, wherein I documented the longstanding supply constraints of its Raspberry Pi 4 precursor). I know. In my defense, however weak, I’ll note that I did write those words 1.5 months earlier, in mid-October (that excuse didn’t work, did it?). That said, the Raspberry Pi Foundation swears that production will ramp dramatically very soon, with supply improving shortly thereafter. Will it? I don’t know.

I bet at least some of you think that I get “special treatment” with the tech companies in constrained-supply situations like these, don’t you? Ha! Just two weeks ago, I finally gave up waiting on retailer supply and purchased a brand-new 8 GB Raspberry Pi 5 board plus an official case from a guy on eBay. He said he’d accidentally bought two of each and didn’t need the spare combo. Whatever. I didn’t get reseller-marked-up too badly, compared to most of the ridiculous pricing I’m seeing on eBay and elsewhere right now. The 8 GB board MSRP is $80, while that of the case is $10. I paid $123.39 plus tax for the combo, which probably left him with a little (but only a little) profit after covering his hardware costs plus the tax and shipping (or gas) he paid.

Don’t get me started on the Active Cooler shown in the first photo, which, if I wasn’t such a trusting fellow, I might think it doesn’t actually exist. Regardless, I still needed a power supply. A 5 V/3 A supply with a USB-C output such as the Raspberry Pi 15W USB-C Power Supply (standard “kit” for the Raspberry Pi 4, for example) might also work for the Raspberry Pi 5, especially if you only boot off a SD card and don’t have a lot of hooked-up, power-sucking peripherals:

That said, the Raspberry Pi 5’s bootup code will still grumble at you via displayed messages indicating that “current draw to peripherals will be restricted to 600mA.” And if you want to boot off a USB flash stick instead, you’ll need to tweak the config.txt prose first. Don’t even think about trying to boot off the m.2 NVMe SSD HAT (speaking of suspect vaporware) with only a 15 W PSU. And in general, you and I both know that the very first things I’ll likely do when I fire up my board are to run lengthy benchmarks on it, constrain its ventilation flow and see when clock throttling kicks in, try overclocking it, and otherwise abuse it. So yeah…27 W (or more).

The Raspberry Pi 27 W USB-C Power Supply shown above, in its white color option (black is also available) and UK plug option (among several others also available), in all cases matching the variants available with its 15 W sibling, was one obvious candidate. But…I know this is going to surprise you…it’s also near-impossible to track down right now. No problem, I thought. I have a bunch of 30 W USB-C wall warts lying around; I’ll just use one of them. Which, more than 500 words in, is where today’s story really begins.

Problem #1 centers on the term “wall wart”. More accurately, as the Wirecutter points out, I should probably be calling them “chargers” because fundamentally that’s all they are: power sources for recharging the batteries integrated within various otherwise-untethered devices (laptops, smartphones, tablets, smartwatches, etc.). Can you not only recharge a widget’s integrated battery but also simultaneously power that widget from the same charger? Sure, if the output power is high enough to handle this simultaneous-energy multitasking.

But trying to run a non-battery-powered device from a charger can be a recipe for disaster, specifically when that charger’s output power is close to what the device demands (such as my suggested 30 W charger for a Raspberry Pi 5 that wants to suck 27 W). Why? Chargers aren’t exactly known for being predictable in output as the power demands of whatever’s on the other end of the USB-C (which I’m using as an example here, although the concept’s equally relevant to USB-A and other standards) cable increase. As you near supposed “30 W”, for example, the output voltage might sag or, at minimum, exhibit notable ripple. The output current might also droop. Not a huge deal if all you’re doing is recharging a battery; it’ll just take a little longer than it might otherwise. But try to directly power a Raspberry Pi 5 with one? Iceberg dead ahead!

About that “30 W” (Problem #2)…if the wall wart has only one output, you can safely surmise that you’ll get a reasonable facsimile of that power metric out of it. But what if there are two outputs? Or more? And what if you only tap into one of the outputs? Will you get the full spec’d power, or not? The answer is “it depends”, and unfortunately the vendors don’t make it easy to get more precise than that. Here’s an example: remember the 30 W single-port USB-C GaN charger that I dissected around a year ago? Well, VOLTME also makes a two-output 35 W model:

Kudos to the company, as this graphic shows:

When either output is used standalone, it delivers the full 35 W. Use both outputs at the same time, on the other hand, and each is capable of 18 W max. Intuitive, yes? Unfortunately, as far as I can tell, VOLTME’s the exception here, not the norm. Take, for example, the two-output 70 W Spigen GaN charger that I take with me on trips:

It’s smaller and lighter than the single-output conventional-circuitry charger that came with my MacBook Pro. It’s also got enough “umph” (and outputs) to juice up both my laptop and my iPad Pro. Plus, its AC prongs are collapsable; love ‘em when jamming the adapter in my bag. All good so far. But one of the outputs is only 60 W max when used standalone and only 50 W max when used in tandem with the other (20 W max). The more powerful output is the bottom of the two in the above photo. And it’s not marked as such on the front panel for differentiation purposes. Inevitably, in the absence of visual cues to the contrary, I end up plugging my laptop into the upper, weaker output port instead.

Problem #3, particularly for 5 V devices on the other end of the cable, involves inconsistent output power at various output voltages. Let’s look back at that 30 W VOLTME teardown again:

I’ve written (more accurately, I suppose, ranted) before about USB-PD (Power Delivery), which supports upfront negotiation between the “source” and “sink” on their respective voltage and current capabilities-and-requirements, leading to the potential for higher output power. Programmable power supply (PPS), an enhancement to USB PD 3.0, supports periodic renegotiation as, for example, a battery nears full charge. Quoting from a Belkin white paper on the topic:

Programmable Power Supply (PPS) is a standard that refers to the advanced charging technology for USB-C devices. It can modify in real time the voltage and current by feeding maximum power based on a device’s charging status. The USB Implementers Forum (USB-IF), a nonprofit group that supports the marketing and promotion of the Universal Serial Bus (USB), added PPS Fast Charging to the USB PD 3.0 standard in 2017. This allows data to be exchanged every 10 seconds, making a dynamic adjustment to the output voltage and current based on the condition of the receiving device’s specifications. PPS’ main advantage over other standards is its capability to lower conversion loss during charging. This means that less heat is generated, which lengthens the device battery’s lifespan.

I mention this because the above photo indicates that this charger support PPS. But let’s backtrack and focus on its supported USB-PD options. It’s a 30 W charger, right? Well:

• 20 V x 1.5 A = 30 W
• 15 V x 2 A = 30 W
• 12 V x 2.5 A = 30 W

The next one isn’t exactly 30 W, but I’d argue that close still counts not only in horseshoes and hand grenades but also with inexpensive-but-still-impressive chargers:

• 9 V x 3 A = 27 W

But what’s the deal with that last one?

• 5 V x 3 A = 15 W

Hmmm…mebbe just a quirk of this particular charger? How about this big bad boy from Anker?

Single output. 100 W. Surely, it’ll pump out more than 3 A at 5 V, right? Nope:

• 5 V x 3 A = 15 W
• 9 V x 3 A = 27 W
• 12 V x 3 A = 36 W
• 15 V x 3 A = 45 W
• 20 V x 5 A = 100 W

And just determining this information necessitated tedious searching for a user manual online at a third-party site. I couldn’t even find mention of the product (via either its 317 product code or A2672 model number) on the manufacturer’s own website! And at this point, I’ll cut to the chase: they’re pretty much all like this.

That a charger will only output 100 W to a device that indicates it can handle 20 V is no shortage of smoke and mirrors in and of itself. But I’m actually willing to give the charger suppliers at least something of a “pass” here. Consumers value not only output power but also size, weight, and the all-important price tag, among other things. These factors likely constrain per-port (if not per-device) output current to 5 A or so. If I’m a portable computer manufacturer and I need 100vW of input power to support not only AC-connected operation but also in-parallel battery recharge at a reasonable rate, I’m going to make darn sure my device can handle a 20 V input!

But what about this seeming 3 A limitation for the 5 V output option? It’s not universal, obviously, since the Raspberry Pi 27 W USB-C power supply supports the following options:

• 1 V x 5 A = 25.5 W
• 9 V x 3 A = 27 W
• 12 V x 2.25 A = 27 W
• 15 V x 1.8 A = 27 W

In contrast, BTW, the official Raspberry Pi 15 W USB-C power supply only does this:

• 1 V x 3.0 A = 15.3 W

My guess as to the root cause of this 5 V@3 A preponderance comes from a clue in a post on the Electrical Engineering Stack Exchange site that I stumbled across while researching this writeup:

The question is about USB Type-C connectivity.

The Type-C connectivity provides two methods of determining source capability.

The primary method is the value of pull-up on HOST side on CC pins. Type-C specifications define three levels of capability: 500/900 mA (56k pull-up to 5V), 1.5 A (22k pull-up), and 3A (10k pull-up). The connecting device pulls down this with 5.1k to ground, and the resulting voltage level tells the device how much current it can take over the particular connection. When the host sees the pull-down, it will turn on “+5Vsafe” VBUS. This is per Type-C protocol.

The secondary method is provided by nearly independent Power Delivery specification. If the consumer implements PD, it still need to follow Type-C specifications for CC pull-up-down protocol, and will receive “+5Vsafe” VBUS.

Only then the consumer will send serial PD-defined messages over CC pin to discover source capabilities. If provider responds, then negotiations for power contract will proceed.

If the consumer is not PD-agnostic, no messages will be generated and no responses will be returned, and no contract will be negotiated. The link power will stay at the default “Safe+5VBUS” power schema, per DC levels on CC pins.

Here’s the irony…my Raspberry Pi 4 board that I mentioned earlier? It’s the rare, early “Model A” variant, which contained an insufficient number and types of resistors to work correctly with some USB-C cables. But that’s not what’s going on here. As the above explanation elucidates, USB-C chargers must (ideally) at minimum support 5 V@3 A for broadest device compatibility. What I’m guessing mostly happens beyond this point is that charger manufacturers focus their development attention on other voltage/current combinations enabled by the secondary compatibility negotiation, leaving the 5 V circuitry implementation well enough alone as-is.

Agree or disagree, readers? Anything more to add here? I look forward to your thoughts in the comments! Meanwhile, I have a Raspberry Pi 27 W USB-C power supply on order from an overseas supplier…and I wait…

—Brian Dipert is the Editor-in-Chief of the Edge AI and Vision Alliance, and a Senior Analyst at BDTI and Editor-in-Chief of InsideDSP, the company’s online newsletter.

Related Content

• A holiday shopping guide for engineers: 2023 edition
• Ungluing a GaN charger
• Why the Raspberry Pi 4 should catch your eye
• The many uses of the Raspberry Pi
• 10 amazing Raspberry Pi-based Kickstarter projects
• Cutting into a conventional USB-C charger

The post Sorting out USB-C power supplies: Specification deceptions and confusing implementations appeared first on EDN.

Discrete semiconductor and passive electronic component maker Vishay Intertechnology Inc of Malvern, PA, USA has completed its acquisition of the wafer fabrication facility and operations in Newport, South Wales, UK of Netherlands-based Nexperia B.V. for about $177m in cash on hand (net of cash acquired)...

Вебінар “Дослідницькі дані: право на конфіденційність” kpi ср, 03/06/2024 - 11:24

submitted by /u/punchki [link] [comments]

Soon after Synopsys snapped up multiphysics simulation toolmaker Ansys, Cadence has responded by announcing the acquisition of engineering simulation supplier BETA CAE Systems International AG for approximately $1.24 billion. BETA CAE, which provides simulation software solutions for automotive and other industries like aerospace and industrial, is based in Lucerne, Switzerland.

BETA CAE’s solutions encompass the entire simulation and analysis flow for multiphysics system simulations, spanning mechanical/structural, computational fluid dynamics (CFD), and electromagnetics (EM). Take, for instance, ANSA, a multidisciplinary computer-aided engineering (CAE) pre-processor that facilitates functionality for full-model build-up in an integrated environment.

Cadence, which entered the multiphysics space several years ago, apparently wants to expand its multiphysics system analysis portfolio and enter structural analysis, the largest system analysis segment. The EDA firm aims to combine its computational software expertise with BETA CAE’s technology to tap into the structural analysis segment.

That’s especially critical for automotive, where the convergence of electrical and mechanical designs is further driven by an increasing shift toward electric vehicles (EVs). BETA CAE has a strong presence in the automotive and aerospace markets, and its customers include Honda Motor, General Motors, Stellantis, Renault, Volvo, and Lockheed Martin.

Multi-domain engineering simulation solutions recently came into the limelight after Cadence’s archrival Synopsys acquired Ansys. Their critical importance amid the mechanical and electrical hyperconvergence is once more affirmed by Cadence’s decision to buy BETA CAE. The acquisition, subject to regulatory approval, is expected to close in the second quarter of 2024.

Related Content

• Ansys, Inc. Acquires Ansoft Corporation
• Analysis: Acquisitions reflect broadening view of EDA
• Expect aftershocks from Synopsys’ Magma acquisition
• Synopsys Acquires RISC-V Processor Simulation Tools Firm
• Electromagnetic Simulation Tools Help Optimize Chip Design

The post Cadence taps into structural analysis by acquiring BETA CAE appeared first on EDN.

submitted by /u/AdamLevy [link] [comments]

Ahead of the IEEE 1.6 TbE standard, Synopsys has developed a complete 1.6 T solution that includes multi-rate, multi-channel 1.6 T Ethernet MAC and PCS controllers, 224-G Ethernet PHY IP, and verification IP.

submitted by /u/Polia31 [link] [comments]

The National Institute for Innovation and Technology (NIIT) and the United States Department of Labor (USDOL) has applauded Wolfspeed Inc of Durham, NC, USA — which makes silicon carbide (SiC) materials and power semiconductor devices — for the establishment of its New York Registered Apprenticeship Program (RAP). As part of its role in the USA’s semiconductor talent pipeline development, the Institute serves as the USDOL’s national Intermediary responsible for expanding Registered Apprenticeships (RAs) throughout the semiconductor and nanotechnology industry supply chains...

Засідання Вченої ради 4 березня medialab вт, 03/05/2024 - 17:45

The schematic below was screen-shot from a LinkedIn group. I heard alarm bells go off in my head when I saw it (Figure 1).

Figure 1 A suggested application note diagram found in a LinkedIn group with a floating node between C4 and C5 that could lead to voltage breakdown.

Capacitors C4 and C5 are placed in series with each other so that their common node has no DC path to anywhere. When I worked on some spacecraft projects, this was absolutely a forbidden thing to do because any floating node like this could drift to an indeterminately high voltage and lead to voltage breakdown.

Even in an earthly milieu, this can be a problem. Imagine something being used or merely being transported or shipped in a thunderstorm environment. Dr. Frankenstein’s lightning bolts could do some real harm.

I have no idea why in the above schematic the series pair of C4 and C5 wasn’t simply made a single 0.5 pF capacitance.

The basic badness of letting something float has been looked at before in “Design precaution: Leave nothing floating”.

It looks like someone didn’t get the message.

John Dunn is an electronics consultant, and a graduate of The Polytechnic Institute of Brooklyn (BSEE) and of New York University (MSEE).

 Related Content

• Design precaution: Leave nothing floating
• Floats like a butterfly, stings like a bee
• The ground illusion: Don’t let it come back to get you
• Electrical noise and mitigation – Part 2: Ground loops, noise transmission and shielding

The post No floating nodes appeared first on EDN.

For several decades, the semiconductor industry has been looking for alternative memory technologies to fill the gap between dynamic random-access memory (DRAM), the compute system’s main memory, and NAND flash—the system’s storage medium—in traditional high-performance computing system architectures.

Such an alternative memory—historically referred to as storage class memory—should outperform DRAM in terms of density and cost and, at the same time, be accessible much faster than NAND flash. The demand for these memories has recently been fueled by a surge in data-intensive applications like generative AI, requiring vast amounts of data to be accessed quickly.

The 1-PCM/1-OTS device: An intermediate solution

Around 2015, the answer came from a new type of non-volatile memory technology, called 3D XPoint, with phase-change memory (PCM) cells arranged at the ‘cross points’ of word and bit lines. PCM memory cells are made of chalcogenide ‘phase-change’ materials, such as germanium antimony telluride (GeSbTe), sandwiched between two electrodes. The material can quickly and reversibly switch between a high-conductive crystalline phase and a low-conductive amorphous phase, and this resistance contrast is used to store information.

Each PCM memory cell is put in series with a selector device, which is needed to address/select the memory cell in the array for program and read operations and to avoid interactions with adjacent cells. While previous versions of PCM used a transistor as a selector device, 3D XPoint memory makers took a different approach: they used so-called ovonic threshold switching (OTS) devices, made of the same class of material—chalcogenides—as the PCM bit cell itself.

The technology became available as a commercial product under the brand name Optane from 2017 onwards. While the first generation was introduced at the NAND side of the DRAM-NAND gap, a later generation was pushed toward the DRAM side. This move was facilitated by the simultaneous introduction of the double data rate (DDR) memory interface, providing a much-needed increase in the speed and bandwidth at which data could be transferred between the PCM memory and the memory controller.

Despite the performance improvement, the technology struggled to deliver the required speed, power, and reliability and to retain its place in the memory market. The power issue mainly arises from the high current needed to switch the PCM bit cell. But there were also constraints related to size and cost. One of the major bottlenecks came from the device architecture itself—the ‘serial’ combination of the bit cell and the OTS selector device.

On first consideration, the 1-PCM/1-OTS outperforms DRAM in terms of cost and area, fostered by the ability to stack the memory array on top of the peripheral circuit. However, these benefits would fade out when one would further increase the density by scaling the bit cell and stacking multiple cross-point layers.

The presence of the additional selector device in series with the PCM bit cell would lead to high-aspect-ratio structures and induce expensive lithography and patterning steps in each of the stacked 2D planar layers. Not to mention the increase in complexity when aiming for true 3D devices, where PCM and OTS materials are mounted on a vertical ‘wall’ by conformal deposition—in a 3D-NAND-like fashion. In 2022, the product was withdrawn from the market.

The OTS selector: its role and operation in a cross-point array

When resistive types of memories such as PCM are arranged in a cross-point array, reading, and writing of the memory cells ideally takes place only on the selected cell, leaving the rest of the cells unaffected. However, in reality, sneak currents run through the unselected cells during memory operation, degrading selectivity and leading to incorrect information retrieval.

Selector devices—usually transistors or diodes—are, therefore, connected serially with each resistive memory element. Their role is to address (or select) the memory bit cell for programming/reading and suppress unwanted sneak currents.

Figure 1 Illustration of the role of a selector device (S) in a cross-point architecture is shown along with resistive memory elements (R). On top, sneak currents run through the unselected cells without a selector, while on bottom, a selector device serially connected to a resistive memory element prevents the occurrence of unwanted sneak currents. Source: imec

Ovonic threshold switching (OTS) devices can be a good alternative to transistor-based selectors. OTS devices are named after Stanford Ovshinsky, who discovered reversible electrical switching phenomena in various amorphous chalcogenide materials in the late 1960s. About 50 years later, interest in these materials led to the development of the OTS selector, an OTS material sandwiched between two metal electrodes.

When the applied voltage exceeds a specific threshold voltage (Vth), the OTS material experiences a fast drop in resistivity, enabling a high current to flow. This current (Ion) is used to program and read the serially connected memory cell. The other devices in the array are biased in such a way that the voltage is only half of the threshold voltage. At this voltage, the (leakage) current (or Ioff) is extremely low (due to the OTS behavior), and this prevents the undesired programming of adjacent cells.

Figure 2 In a typical I-V characteristic of an OTS selector device, at half the threshold voltage, the Ioff current is sufficiently low to prevent interaction with adjacent cells. Source: imec

OTS selectors have several advantages compared to transistor-based solutions. Unlike transistors, which are three-terminal devices, OTS devices are two-terminal devices. This considerably saves area and enables higher densities. The fabrication of an OTS device is also less expensive. Moreover, OTS materials exhibit a high non-linearity—enabled by the low off current at half the threshold voltage—leading to high selectivity.

In addition, they have a large drive current (Ion), can operate at high speed, and have a sufficiently high endurance. And they enable a 3D-compatible solution by stacking 2D planar arrays or enabling true 3D solutions.

The performance and scalability of OTS selectors have improved much over the years, thanks to the past efforts to enable successive generations of the 1-PCM/1-OTS-based Optane memory. In 2015, imec began investigating and developing improved versions of the OTS selector. For example, engineering the material stack for enhanced performance and (thermal) stability, developing new process flows, exploring 3D integration routes, and examining the underlying physical mechanism.

Turning point: the observation of a memory effect in OTS devices

While trying to identify the switching mechanism in OTS selectors, researchers at imec observed an interesting phenomenon. When applying a voltage pulse of a certain polarity—so, either a positive or a negative voltage pulse—they observed that the threshold voltage of the OTS device changed noticeably if the previous pulse had the opposite polarity.

In other words, the threshold voltage seemed to ‘remember’ the polarity of the previous pulse, even after several hours. This discovery opened doors to the development of ‘OTS-only memories’ that exploit this polarity-induced shift in threshold voltage to store and read information. The beauty of the concept? This single element can act as a memory and a selector in cross-point architectures.

Figure 3 In the graph showing the polarity-induced shift in OTS devices, if the read pulse has a different polarity compared to the write pulse, a larger threshold voltage is observed compared to a write-read sequence with the same polarity. Source: imec

This new memory technology can potentially overcome some of the limitations of 1-PCM/1-OTS memories. Having only one material system for selection and memory makes these devices much easier to fabricate and integrate, benefiting cost and density, especially in 3D configurations. In addition, the current needed to write the device promises to be much lower than the current needed for switching PCM cells, resulting in a more energy-efficient memory technology.

Figure 4 The material system of the OTS-only memory (right) is much simpler than the material system needed to fabricate 1S1R cells (left). Source: imec

Imec was the first to publicly report this memory effect in SiGeAsTe-based OTS devices in 2021. After more extensive work, an alternative, Se-based material system led to a practically usable memory window of 1 V, defined by the shift in threshold voltage.

Meanwhile, other research groups have started to report a similar observation, using a variety of names to describe the memory: OTS-only memory, self-selecting memory, self-rectifying memory, or selector-less memory. This also led to an increased number of contributions at the recent 2023 IEDM conference, illustrating the growing interest of the semiconductor community in this promising OTS-only memory technology.

Making OTS-only memory technology suitable for CXL memories

A few years ago, the introduction of memory technologies toward the DRAM side of the DRAM-NAND gap was further supported by introducing the compute express link (CXL) interconnect. This open industry standard interconnect offers low-latency and high-bandwidth connections between the memory and the processor in high-performance computing applications. It also resulted in a new name for the class of memories in the DRAM-NAND gap: CXL memories.

While the OTS device had been optimized for selector applications, new requirements were imposed on the technology to be suitable as a CXL memory. The challenge is to find the most optimal tradeoff between endurance, retention, and power consumption. For CXL-type applications, power consumption (mainly determined by the current needed to switch the memory element) and endurance (targeting at least 1012 write/read cycles before failure) are the most critical parameters, while some compromise is allowed on the retention.

The retention time determines how long the memory can remain in a well-defined state without being refreshed. For CXL-type applications, a retention of a few hours or days is sufficient. This means the stored information must be refreshed periodically but less frequently than in ‘leaky’ DRAM devices.

Imec’s OTS-only memory devices are made of a SiGeAsSe OTS material system sandwiched between carbon-based bottom and top electrodes. The devices, manufactured on a 300-mm wafer, are scalable and easy to fabricate and integrate. They exhibit an endurance of >108 cycles, fast read/write operation ensuring low latency (read and write pulses are as short as 10 ns), and an ultra-low write current <15 µA (i.e., <0.6 MA/cm2).

The latter corresponds to a ~10x energy reduction compared to a typical PCM device. With a half-bias non-linearity NL1/2 ~104, good selectivity is provided, also when operated in memory mode. The polarity-induced voltage shift persists over time, allowing the achievement of a reasonable retention time (>1 month at room temperature). The memory can operate at positive and negative read polarity, showing memory windows of around 1 V and 0.5 V, respectively.

Figure 5 TEM image of the fabricated SiGeAsSe device is shown along with C-based electrodes. Source: T-ED

Figure 6 Demonstration of switching at ultra-low write current with sufficiently large memory window is shown on left and memory window for both read polarities as a function of write current on right. Source: T-ED

Material research a route to 3D integration

The above results highlight the potential of OTS-only memories for CXL applications. So, imec has identified critical directions for further research to advance the devices toward industrial uptake.

Material research is needed for several reasons. First, current OTS material systems contain elements such as As and Se that are toxic and not environmentally friendly. Finding alternative eco-friendly material systems that perform as good, or even better, than current OTS materials therefore is a priority.

Second, material and device design optimizations are needed to improve the reliability to further enhance the endurance to >1012 and lower the cell-to-cell variability. In addition, the threshold voltage is observed to drift over time, contributing to a cycle-to-cycle variability and impacting the retention time.

Reliability improvement goes hand in hand with a fundamental understanding of the physical mechanism that determines the polarity effect in OTS-only memories. So far, this mechanism is not completely clear. Learning what causes the threshold voltage shift is crucial to explain and predict the observed failures and identify the fundamental tradeoffs that limit device performance.

Figure 7 Cartoon of an OTS-only memory is shown in a true 3D architecture. Source: imec

Finally, imec is exploring routes toward true 3D integration, which will be needed to boost the density of the memory bit cells for next-gen compute system architectures.

Daniele Garbin is an R&D Engineer with research interests in OTS and various emerging memory device technologies.

Gouri Sankar Kar is VP of memory and program director of exploratory logic at imec.

Related Content

• Can the Optane Gap Be Filled?
• Emerging memories move to replace embedded NOR flash
• Processor Startup Innovates Memory Allocation Management
• Emerging Memories May Never Go Beyond Niche Applications
• How Emerging Memory Supports Next-Gen Computing in the Data Explosion Era

The post The promise of OTS-only memories for next-gen compute appeared first on EDN.

Infineon Technologies AG of Munich, Germany has introduced its next generation of silicon carbide (SiC) MOSFET trench technology. The new CoolSiC MOSFET 650V and 1200V Generation 2 is said to improve MOSFET key performance figures such as stored energies and charges by up to 20% compared with the prior generation without compromising quality and reliability levels, leading to higher overall energy efficiency...

Riber S.A. of Bezons, France — which makes molecular beam epitaxy (MBE) systems as well as evaporation sources — has received a multi-million Euro order from a new customer in Asia for an automated MBE 412 system in order to strengthen its fundamental and advanced nitride research capabilities...

As FPGAs target more applications, AMD’s newest family—launched today—balances cost and power with performance.

Протокол засідання ректорату від 4 березня 2024 року kpi вт, 03/05/2024 - 15:59

Опубліковано положення щодо виборів ректора Університету kpi вт, 03/05/2024 - 15:20

Телеграм-канал благодійного фонду КПІ medialab вт, 03/05/2024 - 15:11

At the EMV show 2024 in Cologne, Rohde & Schwarz showcases a comprehensive range of EMC test and measurement solutions – ranging from standalone instruments and software to application-specific systems. The company dedicates a large part of the booth to demonstrations that show EMI compliance testing, EMC test automation, EMS immunity test, EMI debugging and EMF. The Rohde & Schwarz solutions are on display from March 12 to 14, 2024 at the Cologne Exhibition Center, hall 11.1, booth 106.

Rohde & Schwarz provides outstanding EMC and field strength testing solutions, ranging from measurement devices to comprehensive testing systems. The company’s testing solutions fulfil all relevant commercial, medical, automotive, military, and aerospace regulations, as well as ETSI and FCC standards for radiated spurious emissions and audio interference measurements.

For both device developers and test houses the R&S EPL1000 EMI test receiver offers fast, accurate and full CISPR 16-1-1 compliant measurements up to 30 MHz at the best price in its class. In addition, The R&S EPL1000 now also features 4 channel click rate measurements in line with the latest CISPR 14-1:2020 version, mandatory for household appliances and electric power tools.

EMI compliance testing ensures devices operate without causing electromagnetic interference. The key component of an EMI system is the test receiver. The R&S ESW EMI test receiver can expand its FFT bandwidth to 970 MHz, enabling it to measure the CISPR frequency of Bands C and D in a single operation. The wide bandwidth ensures sporadic interference is intercepted and enables the highest reliability and repeatability in commercial and MIL-STD testing. In addition, the measurement speed of the R&S ESW FFT bandwidth extension enables new possibilities in EMI compliance testing, emission analysis and debugging.

EMC test automation is essential for achieving reliable and repeatable measurement results. The R&S ELEKTRA test software controls the entire EMC system, automating measurements of the equipment under test (EUT) for emissions (EMI) and immunity (EMS). ELEKTRA now supports measurements in reverberation chambers (RVC) and will be demonstrated at the R&S booth. The R&S AdVISE visual inspection software will also be showcased at the show. This software automates the visual monitoring of an EUT during a test sequence, eliminating human error, ensuring reproducible results, and simplifying test documentation.

Another highlight will be on advancements in EMS immunity testing, with a particular focus on broadband amplifiers and bulk current injection (BCI) systems. The R&S BBA300 family is a new generation of solid-state broadband amplifiers that offer improved robustness and availability in the frequency range from 380 MHz to 6 GHz. Attendees will also have the opportunity to explore a compact rack solution for BCI. This comprehensive solution includes a signal generator, broadband amplifier, power sensor, and software, providing a streamlined approach to EMS immunity testing.

Insightful demonstrations on EMI debugging will be shown by the Rohde & Schwarz oscilloscopes. One such demonstration will involve the oscilloscope R&S RTO6, which provides in-depth information on conducted emissions during device debugging. Also on display will be the new R&S MXO series of oscilloscopes, available in both 4 and 8-channel options. With the expended FFT processing power and advanced triggering options, the R&S MXO oscilloscopes are designed to expedite the EMI debugging process as well as DUT observation for EMS testing.

For EMF testing, Rohde & Schwarz showcases the R&S FPH handheld spectrum analyzer in combination with the R&S TS- EMF isotropic antenna up to 8 GHz: A solution to measure electromagnetic fields easily, covering the new radio services such as WiFi 6E and the complete 5G FR1 Frequency band up to 7.125 GHz. Higher frequencies up to 44 GHz can be measured with a handheld directional antenna such as the R&S HE800-PA. The EMF measurement option for the R&S FPH provides automated testing and a customizable report.

The post Rohde & Schwarz at EMV 2024: Outstanding T&M solutions from the market leader in EMC appeared first on ELE Times.