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Looks like the fuse burnt and spit out the board's protective epoxy or flux near the AC voltage terminals. submitted by /u/ExBx [link] [comments]

🎅 Рекомендації щодо заходів безпеки під час зимових канікул kpi пн, 12/16/2024 - 17:04

On the October 14, 2024, a design idea (DI) by Nick Cornford entitled “To press ON or hold OFF? This does both” appeared. It is a very interesting DI for DC voltages, but what about AC voltages?

Wow the engineering world with your unique design: Design Ideas Submission Guide

After reading this DI, I decided to design a circuit with similar operation for the much-needed AC voltages since many of our gadgets are connected to 110V/230V AC mains. In Figure 1’s circuit, if the single push button SW1 is pressed momentarily once, the mains AC voltage is extended to the output where a gadget is connected. If push button SW1 is pressed for a long time—4 to 5 seconds—power is disconnected. In my opinion, a shiny modern push button looks more attractive and elegant than a toggle switch.

Figure 1 If you press SW1 once, the AC output terminal J2 gets AC supply. If you hold SW1 for a long time, i.e., 4 to 5 seconds, the path from the power supply to terminal J2 gets disconnected. One single pushbutton provides both ON and OFF functions for AC voltage.

In this circuit, mains AC is fed to output terminal through the U5 triac. It should be selected according to voltage and current requirement. When you press SW1 once momentarily, it triggers a monostable U2A. Its raising edge pulse output sets the flip-flop U4A. Q2 becomes ON and current flows through the photodiode of U1. Optotriac U1 conducts and hence triac U5 also conducts. Thus, mains voltage is extended to output terminal.

If you press SW1 for a long time, i.e., 4 to 5 seconds (this time can be adjusted by changing R4, R5), capacitor C1 charges. When its voltage reaches the reference voltage set by the R4, R5 division, the comparator U3A output goes HIGH which resets flip-flop U4A. Thus, the flip-flop output goes LOW, switching Q2 OFF. At this point, no current flows through photodiode of U1, hence U1 and U5 are switched OFF. This way, the mains voltage to output is disconnected.

When you press SW1, C1 is charged. When SW1 is open, there must be a path to discharge C1 for proper operation of the next cycle. This is done by Q1. When SW1 is open, current flows from C1 through the emitter-base of Q1 and R1. Hence Q1 gets saturated and discharges C1. When SW1 is pressed, voltage is applied to base of Q1 via R7 and hence Q1 becomes open and allows C1 to charge. Being CMOS IC-based, the entire circuit draws very little current.

VDD here is 5 VDC. The VDD and VSS pins of U2, U3, and U4 are not shown in the circuit. They must be wired to VDD and VSS inputs shown. If you want a more simple circuit, the U1, U5 circuit can be replaced with a simple relay.

Jayapal Ramalingam has over three decades of experience in designing electronics systems for power & process industries and is presently a freelance automation consultant.

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At a time when traditional approaches such as Moore’s Law and process scaling are struggling to keep up with performance demands, XUPs emerge as a viable candidate for artificial intelligence (AI) and high-performance computing (HPC) applications.

But what’s an XPU? The broad consensus on its composition calls it the stitching of CPU, GPU, and memory dies on a single package. Here, X stands for application-specific units critical for AI infrastructure.

Figure 1 An XPU integrates CPU and GPU in a single package to better serve AI and HPC workloads. Source: Broadcom

An XPU comprises four layers: compute, memory, network I/O, and reliable packaging technology. Industry watchers call XPU the world’s largest processor. But it must be designed with the right ratio of accelerator, memory and I/O bandwidth. And it comes with the imperative of direct or indirect memory ownership.

Below is an XPU case study that demonstrates sophisticated integration of compute, memory, and I/O capabilities.

What’s 3.5D and F2F?

The 2.5D integration, which involves integrating multiple chiplets and high-bandwidth memory (HBM) modules on an interposer, has initially served AI workloads well. However, increasingly complex LLMs and their training necessitate 3D silicon stacking for more powerful silicon devices. Next, 3.5D integration, which combines 3D silicon stacking with 2.5D packaging, takes silicon devices to the next level with the advent of XPUs.

That’s what Broadcom’s XDSiP claims to achieve by integrating more than 6000 mm2 of silicon and up to 12 HBM stacks in a single package. And it does that by developing a face-to-face (F2F) device to accomplish significant improvements in interconnect density and power efficiency compared to the face-to-back (F2B) approach.

While F2B packaging is a 3D integration technique that connects the top metal of one die to the backside of another die, F2F connection assembles two dies ended by a high-level metal interconnection without a thinning step. In other words, F2F stacking directly connects the top metal layers of the top and bottom dies. That provides a dense, reliable connection with minimal electrical interference and exceptional mechanical strength.

Figure 2 The F2F XPU integrates four compute dies with six HBM dies using 3D die stacking for power, clock, and signal interconnects. Source: Broadcom

Broadcom’s F2F 3.5D XPU integrates four compute dies, one I/O die, and six HBM modules while utilizing TSMC’s chip-on-wafer-on-substrate (CoWoS) advanced packaging technology. It claims to minimize latency between compute, memory, and I/O components within the 3D stack while achieving a 7x increase in signal density between stacked dies compared to F2B technology.

“Advanced packaging is critical for next-generation XPU clusters as we hit the limits of Moore’s Law,” said Frank Ostojic, senior VP and GM of the ASIC Products Division at Broadcom. “By stacking chip components vertically, Broadcom’s 3.5D platform enables chip designers to pair the right fabrication processes for each component while shrinking the interposer and package size, leading to significant improvements in performance, efficiency, and cost.”

The XPU nomenclature

Intel’s ambitious take on XPUs hasn’t gone much far as its Falcon Shores platform is no longer proceeding. On the other hand, AMD’s CPU-GPU combo has been making inroads during the past couple of years. Though AMD calls it an accelerated processing unit or APU. It partly comes from the industry nomenclature where AI-specific XPUs are called custom AI accelerators. In other words, it’s the custom chip that provides the processing power to drive AI infrastructure.

Figure 3 MI300A integrates CPU and GPU cores on a single package to accelerate the training of the latest AI models. Source: AMD

AMD’s MI300A combines the company’s CDNA 3 GPU cores and x86-based Zen 4CPU cores with 128 GB of HBM3 memory to deliver HPC and AI workloads. El Capitan—a supercomputer housed at Lawrence Livermore National Laboratory—is powered by AMD’s MI300A APUs and is expected to deliver more than two exaflops of double precision performance when fully deployed.

The AI infrastructure increasingly demands specialized compute accelerators interconnected to form massive clusters. Here, while GPUs have become the de facto hardware, XPUs seem to represent another viable approach for heavy lifting in AI applications.

XPUs are here, and now it’s time for software to catch up and effectively use this brand-new processing venue for AI workloads.

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КПІ ім. Ігоря Сікорського та УСПП підписали меморандум про співпрацю kpi пн, 12/16/2024 - 13:46

Fabless company Wise-integration of Hyeres, France — which was spun off from CEA-Leti in 2020 and designs and develops digital-control of gallium nitride (GaN) and GaN integrated circuits for power conversion — has agreed a strategic distribution partnership covering Europe, the Middle East and Africa (EMEA) with global electronics distributor and supply chain solutions provider Astute Group of Stevenage, UK...

Infineon Technologies AG and Eve Energy Co., Ltd. (EVE Energy), a manufacturer of lithium batteries, have signed a memorandum of understanding (MoU). The two companies aim at enabling comprehensive battery management system solutions for the automotive market. As part of the MoU, Infineon will supply a complete chipset, including microcontroller units, balancing and monitoring ICs, power management ICs, drivers, MOSFETs, controller area networks and sensor products. Equipped with these solutions, EVE Energy’s battery management system can provide high safety, high reliability and optimized cost. It also enables more accurate monitoring, protection and optimization of electric vehicle battery performance and improves driving experience and energy efficiency.

“The rapid growth in electrification has driven the need for advanced battery solutions. The partnership between Infineon’s advanced battery management ICs and EVE Energy`s advanced battery technologies will pave the way for the next generation of intelligent battery packs,” said Andreas Doll, Senior Vice President and General Manager Smart Power at Infineon. “Infineon offers a comprehensive and advanced system-level solution that meets the diverse needs of customers. We believe that further cooperation between the two sides will foster positive interaction and collaborative development at various levels.”

“EVE Energy has experienced rapid growth in the field of battery management systems in recent years, and we are determined to continue this development. Therefore, we highly value the partnership with Infineon,” said Liu Jianhua, co-founder and president of EVE Energy. “Our goal is to jointly introduce more advanced solutions to the market that meet customers’ needs and drive the development of reliable and efficient systems.”

BMS solutions from Infineon

Electrification and battery management systems are key focus areas for Infineon. Infineon has a complete portfolio for battery management systems, including wired and wireless BMS solutions. The wired BMS solution is based on AURIX, PMIC and Balancing and Monitoring IC products, and others. TLE9012DQU and TLE9015DQU provide an optimized solution for battery cell monitoring and balancing. They combine excellent measurement performance with highest quality standards and application robustness, enabling the implementation of lean and cost-efficient designs. The ICs are suitable for a wide range of industrial, consumer and automotive battery applications and fulfill safety requirements up to ASIL-D. The wireless BMS solution, on the other hand, utilizes Infineon’s latest low-power CWY89829 chip to create an interconnected mesh network that ensures maximum node connectivity while maintaining sensor efficiency. In addition, Infineon offers reliable LV MOSFET and EiceDRIVER solutions including 2ED2410 and 2ED4820 products designed for future applications such as the electrification of 24V/48V BMS main switches.

The post Infineon and EVE Energy collaborate to enable the next generation of battery management systems appeared first on ELE Times.

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This is one real-life quest: How do we increase the output voltage of a step-up converter? If you have unlimited access to the right ICs, you are one lucky dog, but what if you don’t? Or maybe you are limited to a specific chip due to particular requirements, for instance, it is stable under some environmental conditions or, it has some specific features/interfaces or maybe, it’s easily accessible or cheap. Here, the ADP1611 step-up converter, is taken as an example. An application circuit can be seen in Figure 1.

Figure 1: An application circuit for the 5 to 15 V ADP1611 step-up regulator.

Wow the engineering world with your unique design: Design Ideas Submission Guide

It has a 20-V limit on its output voltage; this limit is mainly due to the output switch of the ADP1611. Adding a tiny GaN FET such as the EPC2051 to the ADP1611 can increase this limit to above 100 V (Figure 2).

Figure 2: A 5 V to 40 V step-up regulator with the addition of the GaN FET.

The cascode, shown in Figure 2 consists of an internal switch transistor and the newcomer FET; to have better frequency characteristics than the internal switch alone. So, if the newly added GaN FET also has much lower on-resistance (Rds(on)), then the internal switch, it will not reduce the efficiency.

To make the trick possible, the step-up converter should have an open drain (or open collector) output. Also, the connection of the inductor, diode, and the output of the chip must be reconfigured as shown in Figure 2. Diode D2 protects the internal switch from over-voltage.

Don’t forget to use this new value of the output voltage in your calculations. The output diode, capacitor, and inductor should also be rated to the new voltage. For the output diode, I used the HER107.

The addition of this GaN FET adds only 15 mΩ to the switch resistance of ADP1611 (0.23 Ω)—an increase of less than 10%. Please note, the gate-source voltage (VGS) of EPC2051 cannot exceed +6V, so be careful.

—Peter Demchenko studied math at the University of Vilnius and has worked in software development.

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• Thermal design for a high density GaN-based power stage

The post Expanding output range of step-up converter appeared first on EDN.

The US Department of Commerce has signed a non-binding preliminary memorandum of terms (PMT) to provide up to $225m in proposed direct funding under the CHIPS and Science Act to tier-1 automotive supplier Bosch. The investment would support Bosch’s planned investment of $1.9bn to transform its manufacturing facility in Roseville, California, for production of silicon carbide (SiC) power semiconductors. This direct funding would support the expansion of Bosch’s largest SiC device factory globally, which would significantly increase the firm’s production capacity and create up to 1000 construction jobs and up to 700 manufacturing, engineering and R&D jobs in California...

After beginning construction in November 2023, the new €100m Innovation Center of deposition equipment maker Aixtron SE in Herzogenrath, near Aachen, Germany has been opened by Mona Neubaur, Minister for Economic Affairs, Industry, Climate Protection and Energy & Deputy Prime Minister of the State of North Rhine-Westphalia...