Новини світу мікро- та наноелектроніки

Hey everyone! I've been diving into some high-voltage (HV) power electronics experiments recently. I wanted to share a project I've been tinkering with: a custom step-up converter. We all know that step-up (Boost) circuits are excellent for boosting low-voltage inputs (like 12V), but I had a different idea: what if I use the Boost topology on an already high DC voltage? My goal is to take a 100V DC input (or ∼167V DC if I rectify and filter a 120V AC line) and significantly boost it. I'm currently deep in the simulation phase and plan to build a physical prototype soon. I'm looking for feedback from anyone experienced with HV DC/DC conversion on my approach. here is the diagram for circuitJS: txt $ 1 0.000005 3.046768661252054 50 5 43 5e-11 w 752 0 752 32 0 w 752 -32 752 -128 0 f 928 -16 752 -16 32 1.5 0.02 w 752 32 752 48 0 w 704 32 752 32 0 w 704 64 704 32 0 w 752 192 816 192 0 w 752 80 752 144 0 r 752 144 752 192 0 100 t 704 64 752 64 0 1 0 0 100 default g 560 192 528 192 0 0 w 752 192 688 192 0 r 816 -64 816 192 0 22 w 560 80 560 96 0 w 560 48 560 32 0 t 704 64 560 64 0 1 0 0 100 default w 560 192 688 192 0 r 688 144 688 192 0 100 r 560 144 560 192 0 100 w 560 96 560 112 0 w 624 96 560 96 0 w 624 128 624 96 0 t 624 128 560 128 0 1 0 0 100 default t 624 128 688 128 0 1 0 0 100 default r 560 -64 560 32 0 10000000 w 704 -64 704 -144 0 R 560 -64 512 -64 0 0 40 100 0 0 0.5 f 688 32 688 -64 40 1.5 0.02 l 560 -64 672 -64 0 0.1 0 0 d 672 -64 672 -128 2 default c 672 -128 560 -128 4 0.000009999999999999999 0.001 0.001 0.1 g 560 -128 528 -128 0 0 w 672 -128 752 -128 0 w 816 -128 816 -64 0 w 688 32 688 112 0 w 688 32 560 32 0 g 704 -144 704 -176 0 0 w 816 -128 752 -128 0 w 1088 0 1104 0 0 w 1040 0 1088 0 0 w 1088 -160 1088 0 0 r 1280 -160 1088 -160 0 3300 w 1280 -32 1280 -160 0 w 1280 -32 1232 -32 0 w 1232 -128 1232 -64 0 w 1168 -128 1232 -128 0 165 1104 -96 1120 -96 6 0 R 1040 -128 1008 -128 0 0 40 5 0 0 0.5 w 1040 -128 1168 -128 0 r 1040 0 1040 -128 0 1000000 g 1040 96 1040 112 0 0 c 1040 32 1040 96 4 3e-7 0.001 0.001 0 w 1040 32 1104 32 0 w 1040 0 1040 32 0 w 1280 -32 1280 192 0 w 1280 192 928 192 0 w 928 192 928 -16 0 w 1040 96 1200 96 0 w 1200 96 1200 64 0 submitted by /u/Inevitable-Round9995 [link] [comments]

The circuit presented by Cor Van Rij for characterizing JFETs is a clever solution. Noteworthy is the use of a five-pin test socket wired to accommodate all of the possible JFET pinout arrangements.

This idea uses that socket arrangement in a simpler circuit. The only requirement is the availability of two digital multimeters (DMMs), which add the benefit of having a hold function to the measurements. In addition to accuracy, the other goals in developing this tester were:

• It must be simple enough to allow construction without a custom printed circuit board, as only one tester was required.
• Use components on hand as much as possible.
• Accommodate both N- and P-channel devices while using a single voltage supply.
• Use a wide range of supply voltages.
• Incorporate a current limit with LED indication when the limit is reached.

The circuit

The resulting circuit is shown in Figure 1.

Figure 1 Characterizing JFETs using a socket arrangement. The fixture requires the use of two DMMs.

Wow the engineering world with your unique design: Design Ideas Submission Guide

Q1, Q2, R1, R3, R5, D2, and TEST pushbutton S3 comprise the simple current limit circuit (R4 is a parasitic Q-killer).

S3 supplies power to S1, the polarity reversal switch, and S2 selects the measurement. J1 and J2 are banana jacks for the DMM set to read the drain current. J3 and J4 are banana jacks for the DMM set to read Vgs(off). 

Note the polarities of the DMM jacks. They are arranged so that the drain current and Vgs(off) read correctly for the type of JFET being tested—positive IDSS and negative Vgs(off) for N-channel devices and negative IDSS and positive Vgs(off) for P-channel devices.

R2 and D1 indicate the incoming power, while R6 provides a minimum load for the current limiter. Resistor R8 isolates the DUT from the effects of DMM-lead parasitics, and R9 provides a path to earth ground for static dissipation.

Testing JFETs

Figure 2 shows the tester setup measuring Vgs(off) and IDSS for an MPF102, an N-channel device. The specified values of this device are Vgs(off) of -8v maximum and IDSS of 2 to 20 mA. Note that the hold function of the meters was used to maintain the measurements for the photograph. The supply for this implementation is a nominal 12-volt “wall wart” salvaged from a defunct router. 

Figure 2 The test of an MPF302 N-Channel JFET using the JFET characterization circuit.

Figure 3 shows the current limit in action by setting the N-JFET/P-JFET switch to P-JFET for the N-channel MPF102. The limit is 52.2 mA, and the I-LIMIT LED is brightly lit. 

Figure 3 The current limit test that sets the N-JFET/P-JFET switch to P-JFET for the N-channel MPF102.

John L. Waugaman’s love of electronics began when I built a crystal set at age 10 with my father’s help. Earning a BSEE from Carnegie-Mellon University led to a 30-year career in industry designing product inspection equipment and four patents. After being RIF’d, I spent the next 20 years as a consultant specializing in analog design in industrial and military projects. Now I’m retired, sort of, but still designing.  It’s in my blood, I guess.

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• Discrete JFETs still prominent in design: Low input voltage power supply

The post A simpler circuit for characterizing JFETs appeared first on EDN.

“Gold-plated” without the gold plating

Alright, I admit that the title is a bit over the top. So, what do I mean by it? I mean that:

(1) The application of PWM control to a regulator does not significantly degrade the inherent DC accuracy of its output voltage,

(2) Any ability of the regulator’s output voltage to reach below that of its internal reference is supported, and

(3) This is accomplished without the addition of a new reference voltage.

Refer to Figure 1.

Figure 1 This circuit meets the requirements of “Gold-Plated PWM control” as stated above.

Wow the engineering world with your unique design: Design Ideas Submission Guide

How it works

The values of components Cin, Cout, Cf, and L1 are obtained from the regulator’s datasheet. (Note that if the regulator is linear, L1 is replaced with a short.)

The datasheet typically specifies a preferred value of Rg, a single resistor between ground and the feedback pin FB. 

Taking the DC voltage VFB of the regulator’s FB pin into account, R3 is selected so that U2a supplies a V_sup voltage greater than or equal to 3.0 V. C7 and R3 ensure that the composite is non-oscillatory, even with decoupling capacitor C6 in place.C6 is required for the proper operation of the SN74AC04 IC U1.

The following equations govern the circuit’s performance, where Vmax is the desired maximum regulator output voltage:

R3   = ( Vsup / VFB – 1 ) · 10k
Rg1 = Rg / ( 1 – ( VFB / Vsup ) / ( 1 – VFB/Vmax ))
Rg2 = Rg · Rg1 / ( Rg1 – Rg )
Rf = Rg · ( Vmax / VFB – 1 )

They enable the regulator output to reach zero volts (if it is capable of such) when the PWM inputs are at their highest possible duty cycle. 

U1 is part of two separate PWMs whose composite output can provide up to 16 bits of resolution. Ra and Rb + Rc establish a factor of 256 for the relative significance of the PWMs.

If eight bits or less of resolution is required, Rb and Rc, and the least significant PWM, can be eliminated, and all six inverters can be paralleled.

The PWMs’ minimum frequency requirements shown are important because when those are met, the subsequent filter passes a peak-to-peak ripple less than 2-16 of the composite PWM’s full-scale range. This filter consists of Ra, Rb + Rc, R5 to R7, C3 to C5, and U2b.

Errors

The most stringent need to minimize errors comes from regulators with low and highly accurate reference voltages. Let’s consider 600 mV and 0.5% from which we arrive at a 3-mV output error maximum inherent to the regulator. (This is overly restrictive, of course, because it assumes zero-tolerance resistors to set the output voltage. If 0.1% resistors were considered, we’d add 0.2% to arrive at 0.7% and more than 4 mV.)

Broadly, errors come from imperfect resistor ratios and component tolerances, op-amp input offset voltages and bias currents, and non-linear SN74AC04 output resistances. The 0.1% resistors are reasonably cheap.

Resistor ratios

If nominally equal in value, such resistors, forming a ratio, contribute a worst-case error of ± 0.1%. For those of different values, the worst is ± 0.2%. Important ratios involve:

• Rg1, Rg2, and Rf
• R3 and R4
• Ra and Rb + Rc

Various Rf, Rg ratios are inherent to regulator operation.

The Rg1, Rg2; R3, R4; and Ra, Rb + Rc pairs have been introduced as requirements for PWM control.

The Ra / (Rb + Rc) error is ± 0.2%, but since this involves a ratio of 8-bit PWMs at most, it incurs less than 1 least significant bit (LSbit) of error.

The Rg1, Rg2 pair introduces an error of ±0.2 % at most.

The R3, R4 pair is responsible for a worst-case ±0.2 %. All are less than the 0.5% mentioned earlier.

Temperature drift

The OPA2376 has a worst-case input offset voltage of 25 µV over temperature. Even if U2a has a gain of 5 to convert FB’s 600 mV to 3 V, this becomes only 125 µV.

Bias current is 10-pA maximum at 25°C, but we are given a typical value only at 125°C of 250 pA.

Of the two op-amps, U2b sees the higher input resistance. But its current would have to exceed 6 nA to produce even 1-mV of offset, so these op-amps are blameless.

To determine U1’s output resistance, its spec shows that its minimum logic high voltage for a 3-V supply is 2.46 V under a 12-mA load. This means that the maximum for each inverter is 45 Ω, which gives us 9 Ω for five in parallel. (The maximum voltage drop is lower for a logic low 12 mA, resulting in a lower resistance, but we don’t know how much lower, so we are forced to worst-case it at a ridiculous 0 V!)

Counting C3 as a short under dynamic conditions, the five inverters see a 35-kΩ load, leading to a less than 0.03% error.

Wrapping up

The regulator and its output range might need an even higher voltage, but the input voltage IN has been required to exceed 3.2 V. This is because U1 is spec’d to swing to no further than 80 mV from its supply rails under loads of 2 kΩ or more. (I’ve added some margin, but it’s needed only for the case of maximum output voltage.)

You should specify Vmax to be slightly higher than needed so that U2b needn’t swing all the way to ground. This means that a small negative supply for U2 is unnecessary. IN must also be less than 5.5 V to avoid exceeding U2’s spec. If a larger value of IN is required by the regulator, an inexpensive LDO can provide an appropriate U2 supply.

I grant that this design might be overkill, but I wanted to see what might be required to meet the goals I set. But who knows, someone might find it or some aspect of it useful.

Christopher Paul has worked in various engineering positions in the communications industry for over 40 years.

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• Another PWM controls a switching voltage regulator

The post Gold-plated PWM-control of linear and switching regulators appeared first on EDN.

The Ministry of Electronics and IT announced for the clearance of 17 additional proposals, worth Rs. 7,172 crore under the Electronics Components Manufacturing Scheme (ECMS). The projects are expected to generate production worth Rs 65,111 crore and 11,808 direct jobs across the country, according to the ministry.

The approved projects are spread across 9 states from Jammu and Kashmir to Tamil Nadu, focusing on the government’s commitment towards a ‘balanced regional growth’ and creation of high-skill jobs beyond metropolitan clusters.

This approval focuses on developing key technologies used in various IT hardware, wearables, telecom, EVs, industrial electronics, defence, medical electronics, and renewable energy, like oscillators, enclosures, camera modules, connectors, Optical Transceiver (SFP), and multi-layered PCBs.

Minister of Electronics and IT, Ashwini Vaishnaw highlighted that the next phase of value chain integration is being unravelled, from devices to components and sub-assemblies which will ensure that India’s electronics sector reaches $500 billion in manufacturing value by 2030–31.

The Minister also launched the 1st Generation Energy-Efficient Edge Silicon Chip (SoC) (ARKA-GKT1), jointly developed by Cyient semiconductors Pvt Ltd and Azimuth AI along with the projects. The Platform-on-a-Chip SoC integrates advanced computing cores, hardware accelerators, power-efficient design, and secure sensing into a single chip, delivering up to 10x better performance while reducing cost and complexity. It supports smart utilities, cities, batteries, and industrial IoT, showcasing India’s shift toward a product-driven, high-performance semiconductor ecosystem.

The post Government approves 17 projects worth Rs. 7,172 crore under ECMS appeared first on ELE Times.

On 13 November, over 100 industry leaders, researchers, policymakers and educators gathered in Cardiff to celebrate the 10-year anniversary of CSconnected, the world’s first compound semiconductor cluster. This included reflections from founding figures, recognition of ‘Cluster Champions’, and a keynote address from Jack Sargeant MS, Wales’ Minister for Culture, Skills and Social Partnership, whose portfolio aligns with the cluster’s focus on talent pipelines and skills development...